Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329048
E. Dubrova, M. Teslenko, A. Martinelli
This paper addresses the problem of non-disjoint decomposition of Boolean functions. Decomposition has multiple applications in logic synthesis, testing and formal verification. First, we show that the problem of computing non-disjoint decompositions of Boolean functions can be reduced to the problem of finding multiple-vertex dominators of circuit graphs. Then, we prove that there exists an algorithm for computing all multiple-vertex dominators of a fixed size in polynomial time. Our result is important because no polynomial-time algorithm for non-disjoint decomposition of Boolean functions is known. A set of experiments on benchmark circuits illustrates our approach.
{"title":"On relation between non-disjoint decomposition and multiple-vertex dominators","authors":"E. Dubrova, M. Teslenko, A. Martinelli","doi":"10.1109/ISCAS.2004.1329048","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329048","url":null,"abstract":"This paper addresses the problem of non-disjoint decomposition of Boolean functions. Decomposition has multiple applications in logic synthesis, testing and formal verification. First, we show that the problem of computing non-disjoint decompositions of Boolean functions can be reduced to the problem of finding multiple-vertex dominators of circuit graphs. Then, we prove that there exists an algorithm for computing all multiple-vertex dominators of a fixed size in polynomial time. Our result is important because no polynomial-time algorithm for non-disjoint decomposition of Boolean functions is known. A set of experiments on benchmark circuits illustrates our approach.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"12 1","pages":"IV-493"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74281149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329112
V. Aparin, Gary Brown, L. Larson
A FET linearization technique based on optimum gate biasing is investigated at RF. A novel bias circuit is proposed to generate the gate voltage for zero 3rd-order nonlinearity of the FET transconductance. The measured data show that a peak in IIP/sub 3/ occurs at a gate voltage slightly different from the one predicted by the dc theory. The origins of this offset are explained based on a Volterra series analysis and confirmed experimentally. The technique was used in a 0.25 /spl mu/m CMOS cellular-band CDMA LNA. At the optimum bias, the amplifier achieved a NF of 1.8 dB, an IIP/sub 3/ of +10.5 dBm, and a power gain of 14.6 dB with a current consumption of only 2 mA from 2.7 V supply.
{"title":"Linearization of CMOS LNA's via optimum gate biasing","authors":"V. Aparin, Gary Brown, L. Larson","doi":"10.1109/ISCAS.2004.1329112","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329112","url":null,"abstract":"A FET linearization technique based on optimum gate biasing is investigated at RF. A novel bias circuit is proposed to generate the gate voltage for zero 3rd-order nonlinearity of the FET transconductance. The measured data show that a peak in IIP/sub 3/ occurs at a gate voltage slightly different from the one predicted by the dc theory. The origins of this offset are explained based on a Volterra series analysis and confirmed experimentally. The technique was used in a 0.25 /spl mu/m CMOS cellular-band CDMA LNA. At the optimum bias, the amplifier achieved a NF of 1.8 dB, an IIP/sub 3/ of +10.5 dBm, and a power gain of 14.6 dB with a current consumption of only 2 mA from 2.7 V supply.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"30 1","pages":"IV-748"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72600356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329213
H. Gao, P. Xue, Weisi Lin
The marker-based watershed approach is a very efficient means for image segmentation and has been widely used in recent years. The conventional marker-based algorithms are realized using hierarchical queues. A new marker-based watershed algorithm based on the disjoint set data structure is proposed in this paper. It consists of two steps: the flooding step and the resolving step. This algorithm has significantly lower memory requirement as compared with the conventional algorithms while maintaining the computational complexity of O(N) where N is the image size. Experimental results further show that the new algorithm implemented in C language runs much faster than the conventional algorithm based on the hierarchical queues as a result of savings from huge memory allocation and releasing operations.
{"title":"A new marker-based watershed algorithm","authors":"H. Gao, P. Xue, Weisi Lin","doi":"10.1109/ISCAS.2004.1329213","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329213","url":null,"abstract":"The marker-based watershed approach is a very efficient means for image segmentation and has been widely used in recent years. The conventional marker-based algorithms are realized using hierarchical queues. A new marker-based watershed algorithm based on the disjoint set data structure is proposed in this paper. It consists of two steps: the flooding step and the resolving step. This algorithm has significantly lower memory requirement as compared with the conventional algorithms while maintaining the computational complexity of O(N) where N is the image size. Experimental results further show that the new algorithm implemented in C language runs much faster than the conventional algorithm based on the hierarchical queues as a result of savings from huge memory allocation and releasing operations.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"18 1","pages":"II-81"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78750730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329018
Xuezhen Wang, R. Weber, Degang Chen
This paper presents a 5.8 GHz low voltage down-conversion mixer design integrated in a TSMC 0.18 /spl mu/m CMOS process. The proposed method features that an RF input stage converts the RF input voltage to current, which is coupled to the core of Gilbert Cell using current mirror. This implementation eliminates the current source transistor at bottom and furthermore reduces the supply voltage. Common-mode feedback is used for the active load of the mixer. The LO frequency is at 5.6 GHz. The designed mixer requires only a 1.5 V supply voltage and consumes 11.78 mW DC power. At 5.8 GHz, this mixer has single-sideband noise figure (SSB NF) of 13.6 dB, with input return loss of -18 dB, with output return loss of -26.4 dB, Third-order Input Intercept Point (IIP3) of -10.66 dBm, and conversion gain of 10.4 dB.
{"title":"A novel 1.5 V CMFB CMOS down-conversion mixer design for IEEE 802.11 A WLAN systems","authors":"Xuezhen Wang, R. Weber, Degang Chen","doi":"10.1109/ISCAS.2004.1329018","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329018","url":null,"abstract":"This paper presents a 5.8 GHz low voltage down-conversion mixer design integrated in a TSMC 0.18 /spl mu/m CMOS process. The proposed method features that an RF input stage converts the RF input voltage to current, which is coupled to the core of Gilbert Cell using current mirror. This implementation eliminates the current source transistor at bottom and furthermore reduces the supply voltage. Common-mode feedback is used for the active load of the mixer. The LO frequency is at 5.6 GHz. The designed mixer requires only a 1.5 V supply voltage and consumes 11.78 mW DC power. At 5.8 GHz, this mixer has single-sideband noise figure (SSB NF) of 13.6 dB, with input return loss of -18 dB, with output return loss of -26.4 dB, Third-order Input Intercept Point (IIP3) of -10.66 dBm, and conversion gain of 10.4 dB.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"14 1","pages":"IV-373"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78230077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329527
Jian Wang, Xuan Zeng, W. Cai, C. Chiang, J. Tong, Dian Zhou
In this paper, a frequency domain fast wavelet collocation method with GMRES (FFWCM-G) is proposed for the simulation of high-speed large-scale linear VLSI circuits. Taking advantages of wavelet expansion and adaptive scheme, the number of frequency points for calculating frequency response is minimized. Moreover, due to the efficiency of GMRES as the internal iterative solver, the proposed method can achieve nearly linear time complexity, which undoubtedly would be more promising to simulate large-scale integrated circuits.
{"title":"Frequency domain wavelet method with GMRES for large-scale linear circuit simulation","authors":"Jian Wang, Xuan Zeng, W. Cai, C. Chiang, J. Tong, Dian Zhou","doi":"10.1109/ISCAS.2004.1329527","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329527","url":null,"abstract":"In this paper, a frequency domain fast wavelet collocation method with GMRES (FFWCM-G) is proposed for the simulation of high-speed large-scale linear VLSI circuits. Taking advantages of wavelet expansion and adaptive scheme, the number of frequency points for calculating frequency response is minimized. Moreover, due to the efficiency of GMRES as the internal iterative solver, the proposed method can achieve nearly linear time complexity, which undoubtedly would be more promising to simulate large-scale integrated circuits.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"16 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78504994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328129
L. Najafizadeh, I. Filanovsky
A sub-1-V CMOS voltage reference which takes advantage of summing the gate-source voltages of two NMOS transistors operating in saturation region is presented. Both transistors are working below zero temperature coefficient point and thus the voltage reference is able to operate with low supply voltage. The circuit is implemented in a standard 0.18-/spl mu/m CMOS process and gives a temperature coefficient of 4 ppm//spl deg/C in the range of -50/spl deg/C to 150/spl deg/C.
提出了一种亚1伏的CMOS基准电压，该基准电压利用两个工作在饱和区的NMOS晶体管的栅极源电压之和。两个晶体管都工作在零下温度系数点，因此基准电压能够在低电源电压下工作。该电路在标准的0.18-/spl μ m CMOS工艺中实现，在-50/spl°C至150/spl°C范围内给出4 ppm//spl°C的温度系数。
{"title":"Towards a sub-1 V CMOS voltage reference","authors":"L. Najafizadeh, I. Filanovsky","doi":"10.1109/ISCAS.2004.1328129","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328129","url":null,"abstract":"A sub-1-V CMOS voltage reference which takes advantage of summing the gate-source voltages of two NMOS transistors operating in saturation region is presented. Both transistors are working below zero temperature coefficient point and thus the voltage reference is able to operate with low supply voltage. The circuit is implemented in a standard 0.18-/spl mu/m CMOS process and gives a temperature coefficient of 4 ppm//spl deg/C in the range of -50/spl deg/C to 150/spl deg/C.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"7 1","pages":"I-I"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75120472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329284
R. Katti, Xiaoyu Ruan
In this paper we present a new left-to-right (i.e., from the most significant bit to the least significant bit) algorithm to compute the binary signed-digit representations of two integers g and h such that their joint weight is optimal. This method has lower complexity compared to the best known method JSF (Joint Sparse Form) algorithm. This method can be easily extended to the case of finding the signed-digit representation of more than two integers. In [1] Solinas left this as an open problem. Such an algorithm is useful in simplifying the circuits for the implementation of elliptic curve cryptosystems (ECC).
{"title":"Left-to-right binary signed-digit recoding for elliptic curve cryptography","authors":"R. Katti, Xiaoyu Ruan","doi":"10.1109/ISCAS.2004.1329284","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329284","url":null,"abstract":"In this paper we present a new left-to-right (i.e., from the most significant bit to the least significant bit) algorithm to compute the binary signed-digit representations of two integers g and h such that their joint weight is optimal. This method has lower complexity compared to the best known method JSF (Joint Sparse Form) algorithm. This method can be easily extended to the case of finding the signed-digit representation of more than two integers. In [1] Solinas left this as an open problem. Such an algorithm is useful in simplifying the circuits for the implementation of elliptic curve cryptosystems (ECC).","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"34 1","pages":"II-365"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77402485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329949
S. Yuvarajan, Dachuan Yu
PEM fuel cells are being used in a variety of applications including transportation and back-up power systems. The paper presents the complete experimental characteristics of a 1.2kW PEM fuel including its overload capability and dynamic performance. A circuit model for the fuel cell module that can be used to analyze and design fuel-cell power systems is also given. The model includes the mass transport effect and the pressure regulator effect. Simulated characteristics of the fuel cell are compared with the experimental results obtained on a commercial fuel cell.
{"title":"Characteristics and modelling of PEM fuel cells","authors":"S. Yuvarajan, Dachuan Yu","doi":"10.1109/ISCAS.2004.1329949","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329949","url":null,"abstract":"PEM fuel cells are being used in a variety of applications including transportation and back-up power systems. The paper presents the complete experimental characteristics of a 1.2kW PEM fuel including its overload capability and dynamic performance. A circuit model for the fuel cell module that can be used to analyze and design fuel-cell power systems is also given. The model includes the mass transport effect and the pressure regulator effect. Simulated characteristics of the fuel cell are compared with the experimental results obtained on a commercial fuel cell.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"49 1","pages":"V-V"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77619137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328252
X. Fan, P. K. Chan
A new multistage preamplifier with offset reduction for use in high-speed comparator is presented. The proposed circuit is based on the cascade of the modified input offset storage amplifiers and the output offset storage amplifier in pipeline arrangement. Not only does the topology maintain a good input common-mode range, it exhibits faster speed due to the reduced capacitive loads. Using AMS 0.35 /spl mu/m CMOS process model, the simulation result has shown that the new preamplifier has achieved a settling time of 3.5 ns at 1% accuracy for a transient step of 400 mV, which is faster than the conventional works at identical power consumption.
{"title":"A CMOS high-speed multistage preamplifier for comparator design","authors":"X. Fan, P. K. Chan","doi":"10.1109/ISCAS.2004.1328252","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328252","url":null,"abstract":"A new multistage preamplifier with offset reduction for use in high-speed comparator is presented. The proposed circuit is based on the cascade of the modified input offset storage amplifiers and the output offset storage amplifier in pipeline arrangement. Not only does the topology maintain a good input common-mode range, it exhibits faster speed due to the reduced capacitive loads. Using AMS 0.35 /spl mu/m CMOS process model, the simulation result has shown that the new preamplifier has achieved a settling time of 3.5 ns at 1% accuracy for a transient step of 400 mV, which is faster than the conventional works at identical power consumption.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"457 1","pages":"I-545"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79782579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328953
K. Chang, G. Sobelman, E. Saberinia, A. Tewfik
We consider the properties of a class of non-oversampling N-tone sigma-delta modulators which have applications in the design of UWB-OFDM communications systems. The spectrum gaps that exist in such systems are well-matched to the noise shaping properties of these modulators and their non-oversampling nature makes them practical for use with these ultra wideband signals. Performance results for first-order, second-order and L/sup th/-order modulators are presented, and a general expression for the excess resolution that can be gained in such systems is obtained.
{"title":"Analysis of higher-order N-tone sigma-delta modulators for ultra wideband communications","authors":"K. Chang, G. Sobelman, E. Saberinia, A. Tewfik","doi":"10.1109/ISCAS.2004.1328953","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328953","url":null,"abstract":"We consider the properties of a class of non-oversampling N-tone sigma-delta modulators which have applications in the design of UWB-OFDM communications systems. The spectrum gaps that exist in such systems are well-matched to the noise shaping properties of these modulators and their non-oversampling nature makes them practical for use with these ultra wideband signals. Performance results for first-order, second-order and L/sup th/-order modulators are presented, and a general expression for the excess resolution that can be gained in such systems is obtained.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"411 1","pages":"IV-113"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79918566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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