Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329425
K. Seshadri, Adrianne Pontarelli, G. Joglekar, G. Sobelman
This paper gives new results in the design of Pulsed Static CMOS circuits. In particular, a new method of circuit duplication has been proposed which is particularly useful for the implementation of arithmetic functions. An array multiplier and a carry-select adder are used as representative design examples. Simulation results confirm that these Pulsed Static CMOS circuits operate correctly and have greater throughput than traditional static designs.
{"title":"Design techniques for Pulsed Static CMOS","authors":"K. Seshadri, Adrianne Pontarelli, G. Joglekar, G. Sobelman","doi":"10.1109/ISCAS.2004.1329425","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329425","url":null,"abstract":"This paper gives new results in the design of Pulsed Static CMOS circuits. In particular, a new method of circuit duplication has been proposed which is particularly useful for the implementation of arithmetic functions. An array multiplier and a carry-select adder are used as representative design examples. Simulation results confirm that these Pulsed Static CMOS circuits operate correctly and have greater throughput than traditional static designs.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"2002 1","pages":"II-929"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82883114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328676
D. L. Vilariño, C. Rekeczky
In this paper, an improved algorithm for the cellular active contour technique called pixel-level snakes is proposed. The motivation is twofold: on the one hand a higher efficiency and flexibility in the contour evolution towards the boundaries of interest is pursued. On the other hand a higher performance and suitability for its hardware implementation onto a CNN chip-set architecture is required. To illustrate the validity of the proposal some examples and data about the computation time from the implementation of the algorithm on the 64/spl times/64 CNNUM chip have been included.
{"title":"Efficient hardware-oriented cellular active contours","authors":"D. L. Vilariño, C. Rekeczky","doi":"10.1109/ISCAS.2004.1328676","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328676","url":null,"abstract":"In this paper, an improved algorithm for the cellular active contour technique called pixel-level snakes is proposed. The motivation is twofold: on the one hand a higher efficiency and flexibility in the contour evolution towards the boundaries of interest is pursued. On the other hand a higher performance and suitability for its hardware implementation onto a CNN chip-set architecture is required. To illustrate the validity of the proposal some examples and data about the computation time from the implementation of the algorithm on the 64/spl times/64 CNNUM chip have been included.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"09 1","pages":"III-33"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82893442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329030
R. Murji, M. Deen
This paper presents the design results of a 10 GHz CMOS voltage-controlled oscillator (VCO) with automatic amplitude control (AAC). The circuit is an LC oscillator using an integrated octagonal inductor. The VCO is fully integrated and simulation results are shown for a deep n-well 0.18 /spl mu/m CMOS process which allows access to the body of NMOS transistors. The frequency is tuned using the back-gated voltages of the NMOS cross-coupled differential pair in the oscillator. Over temperature variations, the frequency of operation is 10.02 GHz, with a tuning range of 500 MHz, phase noise of -102 dBc/Hz@1MHz and power dissipation of 3.7 mW from a 1.8 V supply.
{"title":"A low-power, 10 GHz back-gated tuned voltage controlled oscillator with automatic amplitude and temperature compensation","authors":"R. Murji, M. Deen","doi":"10.1109/ISCAS.2004.1329030","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329030","url":null,"abstract":"This paper presents the design results of a 10 GHz CMOS voltage-controlled oscillator (VCO) with automatic amplitude control (AAC). The circuit is an LC oscillator using an integrated octagonal inductor. The VCO is fully integrated and simulation results are shown for a deep n-well 0.18 /spl mu/m CMOS process which allows access to the body of NMOS transistors. The frequency is tuned using the back-gated voltages of the NMOS cross-coupled differential pair in the oscillator. Over temperature variations, the frequency of operation is 10.02 GHz, with a tuning range of 500 MHz, phase noise of -102 dBc/Hz@1MHz and power dissipation of 3.7 mW from a 1.8 V supply.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"63 1","pages":"IV-421"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82607667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329315
F. Mendoza-Hernandez, M. L. Aranda, V. Champac
Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues emerge as an important cost in deep submicron circuits. In this paper we propose an improved noise-tolerant dynamic digital circuit technique. By using a charge redistribution process together with the conventional precharge of internal nodes in logic gates, the noise immunity is increased. Simulation results show an improvement of up to 8.6/spl times/over conventional dynamic logic.
{"title":"An improved technique to increase noise-tolerance in dynamic digital circuits","authors":"F. Mendoza-Hernandez, M. L. Aranda, V. Champac","doi":"10.1109/ISCAS.2004.1329315","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329315","url":null,"abstract":"Due to the rapid scaling of the transistor and interconnect dimensions the VLSI circuit technology is having an impressive advancement. However, noise issues emerge as an important cost in deep submicron circuits. In this paper we propose an improved noise-tolerant dynamic digital circuit technique. By using a charge redistribution process together with the conventional precharge of internal nodes in logic gates, the noise immunity is increased. Simulation results show an improvement of up to 8.6/spl times/over conventional dynamic logic.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"44 2 1","pages":"II-489"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82837995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329138
A. Fish, Vadim Milrud, O. Yadid-Pecht
A CMOS high performance current mode winner-take-all (WTA) circuit is presented. The circuit employs a novel technique for inhibitory and excitatory feedbacks based on input currents average computation, achieving both high speed and high resolution. The proposed WTA circuit can be used in a wide variety of applications, while its architecture allows implementation of adaptive thresholding, making it also suitable for visual attention and tracking applications, where "background" inhibition and false alarm reduction are required. The circuit is designed for operation with a wide range of input current values, allowing its integration with circuits operating both in subthreshold and strong inversion regions. Two circuits, each for a different range of input currents, have been implemented in a standard 0.35 /spl mu/m CMOS process available through MOSIS and are operated via a 3.3 V supply. Their operation is discussed and simulation results are reported.
{"title":"High speed and high resolution current winner-take-all circuit in conjunction with adaptive thresholding","authors":"A. Fish, Vadim Milrud, O. Yadid-Pecht","doi":"10.1109/ISCAS.2004.1329138","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329138","url":null,"abstract":"A CMOS high performance current mode winner-take-all (WTA) circuit is presented. The circuit employs a novel technique for inhibitory and excitatory feedbacks based on input currents average computation, achieving both high speed and high resolution. The proposed WTA circuit can be used in a wide variety of applications, while its architecture allows implementation of adaptive thresholding, making it also suitable for visual attention and tracking applications, where \"background\" inhibition and false alarm reduction are required. The circuit is designed for operation with a wide range of input current values, allowing its integration with circuits operating both in subthreshold and strong inversion regions. Two circuits, each for a different range of input currents, have been implemented in a standard 0.35 /spl mu/m CMOS process available through MOSIS and are operated via a 3.3 V supply. Their operation is discussed and simulation results are reported.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"5 1","pages":"IV-852"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90141816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329371
K. Maharatna, A. Troya, M. Krstic, E. Grass, U. Jagdhold
In this paper, we propose a CoOrdinate Rotation DIgital Computer (CORDIC) like processor for computing absolute magnitude of a vector and its corresponding phase angle. It does not require the scale factor compensation step and addition/subtraction operation along the z datapath, has a convergence range over the entire coordinate space and shows similar error characteristics as that of the conventional CORDIC. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications.
{"title":"A CORDIC like processor for computation of arctangent and absolute magnitude of a vector","authors":"K. Maharatna, A. Troya, M. Krstic, E. Grass, U. Jagdhold","doi":"10.1109/ISCAS.2004.1329371","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329371","url":null,"abstract":"In this paper, we propose a CoOrdinate Rotation DIgital Computer (CORDIC) like processor for computing absolute magnitude of a vector and its corresponding phase angle. It does not require the scale factor compensation step and addition/subtraction operation along the z datapath, has a convergence range over the entire coordinate space and shows similar error characteristics as that of the conventional CORDIC. The synthesis result shows that the proposed processor is hardware economic and suitable for low power applications.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"92 1","pages":"II-713"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83804311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328974
Haiqiao Xiao, R. Schaumann, W. R. Daasch, P. Wong, B. Pejcinovic
An all-transistor CMOS active inductor with a self-resonance frequency f/sub R/=5.7 GHz is presented. Large f/sub R/ is achieved by forming an all-NMOS signal path. The measured quality factor, Q, is as high as 665, but Q can be infinite theoretically. Both f/sub R/ and Q are tunable via biasing and on-chip varactors. As an example for using the active inductor, a high-Q bandpass filter for radio-frequency applications is designed. The inductor circuit was implemented in TSMC 0.18-/spl mu/m standard digital CMOS technology and occupies an area of 26.6 /spl mu/m/spl times/30 /spl mu/m including double guardrings. For a supply voltage of 1.8 V, the circuit consumes 4.4 mW, and IIP3 is measured at V/sub pp/=270 mV.
{"title":"A radio-frequency CMOS active inductor and its application in designing high-Q filters","authors":"Haiqiao Xiao, R. Schaumann, W. R. Daasch, P. Wong, B. Pejcinovic","doi":"10.1109/ISCAS.2004.1328974","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328974","url":null,"abstract":"An all-transistor CMOS active inductor with a self-resonance frequency f/sub R/=5.7 GHz is presented. Large f/sub R/ is achieved by forming an all-NMOS signal path. The measured quality factor, Q, is as high as 665, but Q can be infinite theoretically. Both f/sub R/ and Q are tunable via biasing and on-chip varactors. As an example for using the active inductor, a high-Q bandpass filter for radio-frequency applications is designed. The inductor circuit was implemented in TSMC 0.18-/spl mu/m standard digital CMOS technology and occupies an area of 26.6 /spl mu/m/spl times/30 /spl mu/m including double guardrings. For a supply voltage of 1.8 V, the circuit consumes 4.4 mW, and IIP3 is measured at V/sub pp/=270 mV.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"111 1","pages":"IV-197"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79206239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1328940
Shuang Gao, Yang Xiao, Shaohai Hu
We investigate two registration methods for ultrasound image relying on the intensity-based similarity measure. In the first method intensity information is given by feature points which have been extracted by using Harris corner detector. The registration similarity measure is then defined as a cost-function - error cost function. In the latter method we use the same cost-function, but the uniqueness control and region correspondence are not uniform with the first method. Given this similarity measure, parametric ultrasound image registration is stated as a minimization issue. We even exploit the polynomial technique to transform the whole image dataset and estimate the sum of square error in the first measure. The result indicates that the two methods are robust and of the order of our requirements, but the latter measure outperforms the first one.
{"title":"A comparison of two similarity measures in intensity-based ultrasound image registration","authors":"Shuang Gao, Yang Xiao, Shaohai Hu","doi":"10.1109/ISCAS.2004.1328940","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1328940","url":null,"abstract":"We investigate two registration methods for ultrasound image relying on the intensity-based similarity measure. In the first method intensity information is given by feature points which have been extracted by using Harris corner detector. The registration similarity measure is then defined as a cost-function - error cost function. In the latter method we use the same cost-function, but the uniqueness control and region correspondence are not uniform with the first method. Given this similarity measure, parametric ultrasound image registration is stated as a minimization issue. We even exploit the polynomial technique to transform the whole image dataset and estimate the sum of square error in the first measure. The result indicates that the two methods are robust and of the order of our requirements, but the latter measure outperforms the first one.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"6 1","pages":"IV-61"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83183679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329143
T. Pirinen, J. Yli-Hietanen, Pasi Pertilä, A. Visa
There is an increasing need for robust localization of signal sources of various types. With recent developments in sensory instrumentation, some of these needs can be answered. These new developments have also introduced new requirements. Sensor arrays and networks operate for long periods of time, perhaps unattended, and hardware malfunctions may occur between scheduled maintenance. Sensor systems should be able to detect and compensate for hardware failures. This paper presents a new method to detect and compensate for a failure of one sensor in an array performing time delay based direction of arrival (DOA) estimation. The method utilizes confidence factors based on the planar wave assumption. The proposed method is combined with time delay based DOA estimators and tested with simulations. Results indicate that the given method can be used to detect the failed sensor and improve DOA estimation performance when a failure has occurred.
{"title":"Detection and compensation of sensor malfunction in time delay based direction of arrival estimation","authors":"T. Pirinen, J. Yli-Hietanen, Pasi Pertilä, A. Visa","doi":"10.1109/ISCAS.2004.1329143","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329143","url":null,"abstract":"There is an increasing need for robust localization of signal sources of various types. With recent developments in sensory instrumentation, some of these needs can be answered. These new developments have also introduced new requirements. Sensor arrays and networks operate for long periods of time, perhaps unattended, and hardware malfunctions may occur between scheduled maintenance. Sensor systems should be able to detect and compensate for hardware failures. This paper presents a new method to detect and compensate for a failure of one sensor in an array performing time delay based direction of arrival (DOA) estimation. The method utilizes confidence factors based on the planar wave assumption. The proposed method is combined with time delay based DOA estimators and tested with simulations. Results indicate that the given method can be used to detect the failed sensor and improve DOA estimation performance when a failure has occurred.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"26 1","pages":"IV-872"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83262871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-05-23DOI: 10.1109/ISCAS.2004.1329385
R. Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen
This paper proposes a parameterized power-aware IP core generator for the 2-D 8/spl times/8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable Verilog code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.
{"title":"A parameterized power-aware IP core generator for the 2-D 8/spl times/8 DCT/IDCT","authors":"R. Ju, Jia-Wei Chen, Jiun-In Guo, Tien-Fu Chen","doi":"10.1109/ISCAS.2004.1329385","DOIUrl":"https://doi.org/10.1109/ISCAS.2004.1329385","url":null,"abstract":"This paper proposes a parameterized power-aware IP core generator for the 2-D 8/spl times/8 DCT/IDCT. For meeting different performance requirements, we provide a set of parameters in configuring the proposed IP generator including the types of DCT/IDCT architectures, the word-lengths of datapath, and the functions of transform. We adopt two different approaches in designing the 2-D DCT/IDCT including the high throughput adder-based approach and the low-cost group distributed arithmetic (GDA) approach, which exhibits different power dissipation and performance. In addition to generating the synthesizable Verilog code and the associated supporting files for the IP core, the proposed power-aware IP generator can also perform the data precision analysis for users when trading-off the hardware cost, power consumption, and data precision in designing the DCT/IDCT IP for the portable multimedia applications.","PeriodicalId":6445,"journal":{"name":"2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)","volume":"41 1","pages":"II-769"},"PeriodicalIF":0.0,"publicationDate":"2004-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83290275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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