Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9366039
Q. Gu, Byung-Wook Min, M. Tabesh
{"title":"Session 22 Overview: Terahertz for Communication and Sensing Wireless Subcommittee","authors":"Q. Gu, Byung-Wook Min, M. Tabesh","doi":"10.1109/ISSCC42613.2021.9366039","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366039","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"43 1","pages":"312-313"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87367163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-02-13DOI: 10.1109/ISSCC42613.2021.9365948
Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim
First devices for the new DRAM standards LPDDR5 and DDR5 are implementing improvements in bandwidth and power efficiency. The new devices will have a huge impact on a very wide range of applications, from IoT applications and smartphones to server and workstation applications. A new proposal for managed LRDIMM promises to reduce cost and power, and to provide capacities up to 512GB. For next generation DRAM interfaces a PAM-3 transceiver with 27Gb/s/pin on the base of 3 bits per 2 symbols is presented. -generation LPDDR5 the maximum bandwidth as WCK clocking and non-target ODT (NT-ODT). power consumption using techniques such as dynamic voltage frequency scaling (DVFS), and a deep-sleep mode (DSM). presents a DDR5 SDRAM to overcome bandwidth, power and capacity limitations of DDR4. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a phase-rotator-based DLL, write-level training, and RX/TX with the enhanced DFE/FFE. The energy efficiency is improved by more than 30% with 1.1V/1.8V VDD and VPP. a 3bit/2UI 1.03pJ/bit PAM-3 single-ended TRX. An 27Gb/s PAM-3 symbol is generated with an output driver voltage of 0.6V and a 1/3-rate forwarded clock frequency of 9GHz. The RX adopts a 1-tap tri-level DFE, which has the same complexity as for NRZ signaling to equalize the PAM-3 signal. Fabricated in a 28nm CMOS technology, the proposed PAM-3 TRX can be utilized for the next generation memory interface with low power. (ODP) structured (media) and ODP structure of for cost minimization, pre-CMD scheme for reduction. Dies per wafer increase of compared to conventional DRAM with same process and same capacity was achieved. DIMM power consumption is
{"title":"Session 25 Overview: DRAM Memory Subcommittee","authors":"Dong-Uk Lee, Bor-Doou Rong, Kyu-Hyoun Kim","doi":"10.1109/ISSCC42613.2021.9365948","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365948","url":null,"abstract":"First devices for the new DRAM standards LPDDR5 and DDR5 are implementing improvements in bandwidth and power efficiency. The new devices will have a huge impact on a very wide range of applications, from IoT applications and smartphones to server and workstation applications. A new proposal for managed LRDIMM promises to reduce cost and power, and to provide capacities up to 512GB. For next generation DRAM interfaces a PAM-3 transceiver with 27Gb/s/pin on the base of 3 bits per 2 symbols is presented. -generation LPDDR5 the maximum bandwidth as WCK clocking and non-target ODT (NT-ODT). power consumption using techniques such as dynamic voltage frequency scaling (DVFS), and a deep-sleep mode (DSM). presents a DDR5 SDRAM to overcome bandwidth, power and capacity limitations of DDR4. This paper presents a 16Gb 6.4Gb/s/pin DDR5 SDRAM with a phase-rotator-based DLL, write-level training, and RX/TX with the enhanced DFE/FFE. The energy efficiency is improved by more than 30% with 1.1V/1.8V VDD and VPP. a 3bit/2UI 1.03pJ/bit PAM-3 single-ended TRX. An 27Gb/s PAM-3 symbol is generated with an output driver voltage of 0.6V and a 1/3-rate forwarded clock frequency of 9GHz. The RX adopts a 1-tap tri-level DFE, which has the same complexity as for NRZ signaling to equalize the PAM-3 signal. Fabricated in a 28nm CMOS technology, the proposed PAM-3 TRX can be utilized for the next generation memory interface with low power. (ODP) structured (media) and ODP structure of for cost minimization, pre-CMD scheme for reduction. Dies per wafer increase of compared to conventional DRAM with same process and same capacity was achieved. DIMM power consumption is","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"26 1","pages":"342-343"},"PeriodicalIF":0.0,"publicationDate":"2021-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75713565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/ISSCC42613.2021.9365994
Min Chen, B. Wicht, K. Miyaji
{"title":"Session 33 Overview: High-Voltage, GaN and Wireless Power Power Management Subcommittee","authors":"Min Chen, B. Wicht, K. Miyaji","doi":"10.1109/ISSCC42613.2021.9365994","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365994","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"458-459"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84487763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/ISSCC42613.2021.9365805
Joonsung Bae, Jennifer Lloyd, C. Hoof
{"title":"Session 28 Overview: Biomedical Systems Imagers, Medical, Mems and Displays Subcommittee","authors":"Joonsung Bae, Jennifer Lloyd, C. Hoof","doi":"10.1109/ISSCC42613.2021.9365805","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365805","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"26 1","pages":"384-385"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84810000","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/ISSCC42613.2021.9365930
H. Shinohara, M. Alioto, I. Verbauwhede
{"title":"Session 36 Overview: Hardware Security Digital Architectures and Systems Subcommittee","authors":"H. Shinohara, M. Alioto, I. Verbauwhede","doi":"10.1109/ISSCC42613.2021.9365930","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365930","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"9 1","pages":"496-497"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78902143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/ISSCC42613.2021.9366007
H. Mair, S. Shiratake, Eric Karl, T. Burd, Jonathan Chang, Debbie Marr, S. Naffziger, H. Corporaal, K. Takeuchi, Naresh R Shanbhag
{"title":"SE1: What Technologies Will Shape the Future of Computing?","authors":"H. Mair, S. Shiratake, Eric Karl, T. Burd, Jonathan Chang, Debbie Marr, S. Naffziger, H. Corporaal, K. Takeuchi, Naresh R Shanbhag","doi":"10.1109/ISSCC42613.2021.9366007","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9366007","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"52 1","pages":"537-538"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86479702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-01-01DOI: 10.1109/ISSCC42613.2021.9365799
T. Georgantas, Y. Baeyens, Alice Wang
{"title":"Session 2 Overview: Highlighted Chip Releases: 5G and Radar Systems Invited Papers","authors":"T. Georgantas, Y. Baeyens, Alice Wang","doi":"10.1109/ISSCC42613.2021.9365799","DOIUrl":"https://doi.org/10.1109/ISSCC42613.2021.9365799","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"36 1","pages":"36-37"},"PeriodicalIF":0.0,"publicationDate":"2021-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85145504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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