Pub Date : 2019-01-01DOI: 10.1109/ISSCC.2019.8662417
B. Jann, Greg Chance, Ankur Guha Roy, Aishwarya Balakrishnan, Niranjan Karandikar, Thomas William Brown, Xi Li, Brandon Davis, Jose Luis Ceballos, Nebil Tanzi, Kurt Hausmann, Hyun Yoon, Yen-ling Huang, Amit Freiman, Bruce Geren, Peter Pawliuk, Wayne Ballantyne
{"title":"A 5G Sub-6GHz Zero-IF and mm-Wave IF Transceiver with MIMO and Carrier Aggregation","authors":"B. Jann, Greg Chance, Ankur Guha Roy, Aishwarya Balakrishnan, Niranjan Karandikar, Thomas William Brown, Xi Li, Brandon Davis, Jose Luis Ceballos, Nebil Tanzi, Kurt Hausmann, Hyun Yoon, Yen-ling Huang, Amit Freiman, Bruce Geren, Peter Pawliuk, Wayne Ballantyne","doi":"10.1109/ISSCC.2019.8662417","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662417","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"187 5 1","pages":"352-354"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80542676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-01-01DOI: 10.1109/ISSCC.2019.8662355
Robert K. Henderson, N. Johnston, S. W. Hutchings, I. Gyöngy, T. A. Abbas, N. Dutton, Max Tyler, Susan Chan, Jonathan Leach
{"title":"A 256×256 40nm/90nm CMOS 3D-Stacked 120dB Dynamic-Range Reconfigurable Time-Resolved SPAD Imager","authors":"Robert K. Henderson, N. Johnston, S. W. Hutchings, I. Gyöngy, T. A. Abbas, N. Dutton, Max Tyler, Susan Chan, Jonathan Leach","doi":"10.1109/ISSCC.2019.8662355","DOIUrl":"https://doi.org/10.1109/ISSCC.2019.8662355","url":null,"abstract":"","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"235 1","pages":"106-108"},"PeriodicalIF":0.0,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80946560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310320
Ki-Tae Park, Yan Li, Leland Chang
Continued proliferation of semiconductors for a smarter society drives the evolution of flash memory technologies towards higher density, lower power consumption, and lower cost. This year, a new generation of 3D NAND Flash memory with up to 96-stacked word-line layers is introduced. For the first time, a memory with over 1Tb density is demonstrated using a 4b/cell 3D NAND technology. An ultra-low latency flash controller with a new high-speed 3D NAND is proposed in order to fill a large performance gap between DRAM and Flash memories.
智能社会对半导体的持续发展推动了闪存技术向更高密度、更低功耗和更低成本的方向发展。今年，推出了新一代3D NAND闪存，最多可堆叠96层字行层。首次使用4b/cell 3D NAND技术展示了超过1Tb密度的存储器。为了填补DRAM和闪存之间的巨大性能差距，提出了一种具有新型高速3D NAND的超低延迟闪存控制器。
{"title":"Session 20 overview: Flash-memory solutions: Memory subcommittee","authors":"Ki-Tae Park, Yan Li, Leland Chang","doi":"10.1109/ISSCC.2018.8310320","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310320","url":null,"abstract":"Continued proliferation of semiconductors for a smarter society drives the evolution of flash memory technologies towards higher density, lower power consumption, and lower cost. This year, a new generation of 3D NAND Flash memory with up to 96-stacked word-line layers is introduced. For the first time, a memory with over 1Tb density is demonstrated using a 4b/cell 3D NAND technology. An ultra-low latency flash controller with a new high-speed 3D NAND is proposed in order to fill a large performance gap between DRAM and Flash memories.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"55 1","pages":"334-335"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77136010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310293
P. Mercier, Long Yan, M. Nagata
Advances in sensors, low-power circuits, and integration technologies are helping to revolutionize industries ranging from agriculture to healthcare. This session highlights innovations in connected sensors for improved food production, diagnostic imaging, physiochemical sensing, and neurophysiology. The first paper is an invited paper, and describes how advances in sensors, circuits, and algorithms can help improve the efficiency of food production. The second paper demonstrates a multi-camera capsule endoscope with integrated high-throughput communications. The next three papers describe sensing systems that are powered from and/or measure chemical parameters in gas for industrial applications, or in bodily fluids for healthcare applications. Subsequent papers demonstrate advances in transcranial communications, optoelectronic neural recorders, multi-modal wearable brain imagers, and closed-loop neural implants with integrated support vector machine classifiers.
{"title":"Session 17 overview: Technologies for health and society: Technology directions subcommittee","authors":"P. Mercier, Long Yan, M. Nagata","doi":"10.1109/ISSCC.2018.8310293","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310293","url":null,"abstract":"Advances in sensors, low-power circuits, and integration technologies are helping to revolutionize industries ranging from agriculture to healthcare. This session highlights innovations in connected sensors for improved food production, diagnostic imaging, physiochemical sensing, and neurophysiology. The first paper is an invited paper, and describes how advances in sensors, circuits, and algorithms can help improve the efficiency of food production. The second paper demonstrates a multi-camera capsule endoscope with integrated high-throughput communications. The next three papers describe sensing systems that are powered from and/or measure chemical parameters in gas for industrial applications, or in bodily fluids for healthcare applications. Subsequent papers demonstrate advances in transcranial communications, optoelectronic neural recorders, multi-modal wearable brain imagers, and closed-loop neural implants with integrated support vector machine classifiers.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"33 1","pages":"280-281"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87500876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310373
H. Luong, Kyoohyun Lim, S. Pellerano
Connecting things wirelessly requires optimization from multidisciplinary areas. This session will introduce state-of-the-art wireless transceivers supporting ultra-lower-power IoT and connectivity solutions. In this session, a high-performance WLAN SoC supporting up to 802.11ax 1024QAM will be presented. Then, two-blockers-tolerant high-sensitivity Bluetooth Low-Energy (BLE) transceivers in 65nm and 40nm CMOS will be presented followed by a best-in-class performance all-digital PLL for BLE in 16nm FinFET technology, and an energy-harvesting BLE transmitter in 28nm CMOS. An ultra-low-power wakeup receiver enabling event-driven sensor nodes and an ultrasonic wake-up receiver using a precharged capacitive micro-machined ultrasound transducer will be shown. Finally, a 5.8GHz near-field radio achieving the smallest die size of 116μm×116μm will be presented in this session.
{"title":"Session 28 overview: Wireless connectivity: Wireless subcommittee","authors":"H. Luong, Kyoohyun Lim, S. Pellerano","doi":"10.1109/ISSCC.2018.8310373","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310373","url":null,"abstract":"Connecting things wirelessly requires optimization from multidisciplinary areas. This session will introduce state-of-the-art wireless transceivers supporting ultra-lower-power IoT and connectivity solutions. In this session, a high-performance WLAN SoC supporting up to 802.11ax 1024QAM will be presented. Then, two-blockers-tolerant high-sensitivity Bluetooth Low-Energy (BLE) transceivers in 65nm and 40nm CMOS will be presented followed by a best-in-class performance all-digital PLL for BLE in 16nm FinFET technology, and an energy-harvesting BLE transmitter in 28nm CMOS. An ultra-low-power wakeup receiver enabling event-driven sensor nodes and an ultrasonic wake-up receiver using a precharged capacitive micro-machined ultrasound transducer will be shown. Finally, a 5.8GHz near-field radio achieving the smallest die size of 116μm×116μm will be presented in this session.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"135 1","pages":"440-441"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86734423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310396
N. Verma, F. Hamzaoglu, M. Nagata, Leland Chang
Many state-of-the-art systems for machine learning are limited by memory in terms of the energy they require and the performance they can achieve. This session explores how this bottleneck can be overcome by emerging architectures that perform computation inside the memory array. This necessitates unconventional, typically mixed-signal, circuits for computation, which exploit the statistical nature of machine-learning applications to achieve high algorithmic performance with substantial energy and throughput gains. Further, the architectures serve as a driver for emerging memory technologies, exploiting the high-density and nonvolatility these offer towards increased scale and efficiency of computation. The innovative papers in this session provide concrete demonstrations of this promise, by going beyond conventional architectures.
{"title":"Session 31 overview: Computation in memory for machine learning: Technology directions and memory subcommittees","authors":"N. Verma, F. Hamzaoglu, M. Nagata, Leland Chang","doi":"10.1109/ISSCC.2018.8310396","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310396","url":null,"abstract":"Many state-of-the-art systems for machine learning are limited by memory in terms of the energy they require and the performance they can achieve. This session explores how this bottleneck can be overcome by emerging architectures that perform computation inside the memory array. This necessitates unconventional, typically mixed-signal, circuits for computation, which exploit the statistical nature of machine-learning applications to achieve high algorithmic performance with substantial energy and throughput gains. Further, the architectures serve as a driver for emerging memory technologies, exploiting the high-density and nonvolatility these offer towards increased scale and efficiency of computation. The innovative papers in this session provide concrete demonstrations of this promise, by going beyond conventional architectures.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"75 1","pages":"486-487"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83221403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310335
Hyunchol Shin, A. Bevilacqua, P. Wambacq
The session presents LO-generation systems aimed at 5G communications and sub-mm-wave sensing systems. The first three papers focus on mm-wave CMOS LOs for multiband 5G systems and highlight the importance of injection-locked frequency multipliers and accurate quadrature generation for the 28-to-44GHz band. Then, the session continues with a BiCMOS 301.7-to-331.8GHz source and a 4GHz inverse-Class-F CMOS VCO. A quad-core BiCMOS 15GHz VCO is presented next, while a 7.4-to-14GHz CMOS PLL concludes the session.
{"title":"Session 23 overview: LO generation: RF subcommittee","authors":"Hyunchol Shin, A. Bevilacqua, P. Wambacq","doi":"10.1109/ISSCC.2018.8310335","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310335","url":null,"abstract":"The session presents LO-generation systems aimed at 5G communications and sub-mm-wave sensing systems. The first three papers focus on mm-wave CMOS LOs for multiband 5G systems and highlight the importance of injection-locked frequency multipliers and accurate quadrature generation for the 28-to-44GHz band. Then, the session continues with a BiCMOS 301.7-to-331.8GHz source and a 4GHz inverse-Class-F CMOS VCO. A quad-core BiCMOS 15GHz VCO is presented next, while a 7.4-to-14GHz CMOS PLL concludes the session.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"1 1","pages":"364-365"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90296687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310267
M. Straayer, S. Ryu, U. Moon
This session's high-resolution analog-to-digital converters (ADCs) with 12 to 19b ENOB introduce a number of advanced circuit design techniques to achieve very high performance with low power consumption. While many of the proposed designs use an efficient SAR architecture where possible for moderate resolution, higher performance is consistently enabled by delta-sigma and pipeline architectures. Precision is further enabled by techniques such as hardware re-use, calibration, dynamic element matching, chopping, and correlated double-sampling.
{"title":"Session 14 overview: High-resolution ADCs: Data converter subcommittee","authors":"M. Straayer, S. Ryu, U. Moon","doi":"10.1109/ISSCC.2018.8310267","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310267","url":null,"abstract":"This session's high-resolution analog-to-digital converters (ADCs) with 12 to 19b ENOB introduce a number of advanced circuit design techniques to achieve very high performance with low power consumption. While many of the proposed designs use an efficient SAR architecture where possible for moderate resolution, higher performance is consistently enabled by delta-sigma and pipeline architectures. Precision is further enabled by techniques such as hardware re-use, calibration, dynamic element matching, chopping, and correlated double-sampling.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"5 1","pages":"228-229"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78555394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310192
H. Wakabayashi, M. Ikeda
The session presents advances in image sensors covering BSI, global shuttering, organic photoconductive film, pixel scaling, dynamic vision, high frame rate imaging, 3D time-of-flight, and SPADs. The first paper, by Sony, presents a BSI global shutter with in-pixel ADC. Then, Panasonic presents a global shutter using organic film with in-pixel noise cancellation. Samsung presents a 0.9μm pixel with complete deep-trench isolation. Sony presents a low-power event-driven imager with motion detection. TSMC presents a 13.5Mpixel BSI image sensor with a readout subsampling architecture that allows 514fps at 720p. NHK presents a high-speed image sensor achieving 8K video up to 480fps. Toshiba presents a LiDAR SoC enabling range measurements up to 200m. Microsoft presents a BSI time-of-flight image sensor with 3.5μm global-shutter pixels with modulation frequencies up to 320MHz. Delft University presents a direct time-of-flight image sensor with modular SPAD-based pixel arrays fabricated in 3D-stacked 45/65nm CMOS. Finally, FBK presents a SPAD array coupled with TDCs to measure spatial correlations of entangled photons at a rate of 800kHz.
{"title":"Session 5 overview: Image sensors: IMMD subcommittee","authors":"H. Wakabayashi, M. Ikeda","doi":"10.1109/ISSCC.2018.8310192","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310192","url":null,"abstract":"The session presents advances in image sensors covering BSI, global shuttering, organic photoconductive film, pixel scaling, dynamic vision, high frame rate imaging, 3D time-of-flight, and SPADs. The first paper, by Sony, presents a BSI global shutter with in-pixel ADC. Then, Panasonic presents a global shutter using organic film with in-pixel noise cancellation. Samsung presents a 0.9μm pixel with complete deep-trench isolation. Sony presents a low-power event-driven imager with motion detection. TSMC presents a 13.5Mpixel BSI image sensor with a readout subsampling architecture that allows 514fps at 720p. NHK presents a high-speed image sensor achieving 8K video up to 480fps. Toshiba presents a LiDAR SoC enabling range measurements up to 200m. Microsoft presents a BSI time-of-flight image sensor with 3.5μm global-shutter pixels with modulation frequencies up to 320MHz. Delft University presents a direct time-of-flight image sensor with modular SPAD-based pixel arrays fabricated in 3D-stacked 45/65nm CMOS. Finally, FBK presents a SPAD array coupled with TDCs to measure spatial correlations of entangled photons at a rate of 800kHz.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"19 1","pages":"78-79"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72558770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310254
Seung-Jun Bae, W. Spirkl, Leland Chang
Demand for high-performance and high-capacity DRAMs is increasing more dramatically than in the past, due to the emergence of new areas such as machine learning, VR and AR. In line with this trend, new innovations with capacities of 16Gb and data-rate speeds of 18Gb/s/pin are introduced this year. These changes are common to high-performance computing, gaming graphics, mobile, and server fields, including artificial intelligence. Two graphics DRAM papers of the next generation GDDR6 standard show a maximum data rate of 16 to 18Gb/s/pin with single-ended signaling, and 16Gb high-density DRAMs in a 10nm process node are introduced in LPDDR4X and DDR4. HBM2 is extended to an 8H stack for 64Gb density while keeping a BW of 341GB/s.
{"title":"Session 12 overview: DRAM: Memory subcommittee","authors":"Seung-Jun Bae, W. Spirkl, Leland Chang","doi":"10.1109/ISSCC.2018.8310254","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310254","url":null,"abstract":"Demand for high-performance and high-capacity DRAMs is increasing more dramatically than in the past, due to the emergence of new areas such as machine learning, VR and AR. In line with this trend, new innovations with capacities of 16Gb and data-rate speeds of 18Gb/s/pin are introduced this year. These changes are common to high-performance computing, gaming graphics, mobile, and server fields, including artificial intelligence. Two graphics DRAM papers of the next generation GDDR6 standard show a maximum data rate of 16 to 18Gb/s/pin with single-ended signaling, and 16Gb high-density DRAMs in a 10nm process node are introduced in LPDDR4X and DDR4. HBM2 is extended to an 8H stack for 64Gb density while keeping a BW of 341GB/s.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"108 1","pages":"202-203"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79333113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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