Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310165
B. D. Salvo
The advent of the Internet-of-Things has introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics processing occurs at the edge and at the end-devices instead of in the Cloud. To map the embedded-systems requirements, we present a holistic research approach to the development of low-power architectures inspired by the human brain, where process development and integration, circuit design, system architecture, and learning algorithms are simultaneously optimized. This paper is organized as follows: We begin with a survey of recent research on the human brain and a historical perspective of cognitive neuroscience. Then, artificial intelligence is introduced, and the challenges of Deep Learning systems (in terms of power requirements) are addressed. The key reasons to distribute intelligence over the whole network are discussed. To emphasize the need for low-power solutions, a quantitative benchmark of existing specialized edge platforms that can execute machine-learning algorithms on conventional embedded hardware is presented. The primary focus of this paper will be on the implementation of optimized neuromorphic hardware as a highly promising solution for future ultra-low-power cognitive systems. We show that emerging technologies (such as advanced CMOS, 3D technologies, emerging resistive memories, and Silicon photonics), coupled with novel brain-inspired paradigms, such as spike-coding and spike-time-dependent-plasticity, have extraordinary potential to provide intelligent features in hardware, approaching the way knowledge is created and processed in the human brain. Finally, we conclude with our vision of the enabled future disruptive applications and a discussion of the main challenges which should be tackled to exploit the full potential of brain-inspired technologies.
{"title":"Brain-Inspired technologies: Towards chips that think?","authors":"B. D. Salvo","doi":"10.1109/ISSCC.2018.8310165","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310165","url":null,"abstract":"The advent of the Internet-of-Things has introduced a new paradigm that supports a decentralized and hierarchical communication architecture, where a great deal of analytics processing occurs at the edge and at the end-devices instead of in the Cloud. To map the embedded-systems requirements, we present a holistic research approach to the development of low-power architectures inspired by the human brain, where process development and integration, circuit design, system architecture, and learning algorithms are simultaneously optimized. This paper is organized as follows: We begin with a survey of recent research on the human brain and a historical perspective of cognitive neuroscience. Then, artificial intelligence is introduced, and the challenges of Deep Learning systems (in terms of power requirements) are addressed. The key reasons to distribute intelligence over the whole network are discussed. To emphasize the need for low-power solutions, a quantitative benchmark of existing specialized edge platforms that can execute machine-learning algorithms on conventional embedded hardware is presented. The primary focus of this paper will be on the implementation of optimized neuromorphic hardware as a highly promising solution for future ultra-low-power cognitive systems. We show that emerging technologies (such as advanced CMOS, 3D technologies, emerging resistive memories, and Silicon photonics), coupled with novel brain-inspired paradigms, such as spike-coding and spike-time-dependent-plasticity, have extraordinary potential to provide intelligent features in hardware, approaching the way knowledge is created and processed in the human brain. Finally, we conclude with our vision of the enabled future disruptive applications and a discussion of the main challenges which should be tackled to exploit the full potential of brain-inspired technologies.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"57 1","pages":"12-18"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84802807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310284
A. Emami-Neyestanak, A. Joy, F. O’Mahony
Electrical and optical links continue to provide challenges that cannot be overcome by process technology advances alone. The ingenuity of the designer is a major contribution, and this is clearly demonstrated by the papers in this session. The first is an invited paper that reviews state-ofthe-art optical interconnects in scalable, high-density standards-based switching fabrics for networking systems and cloud computing. The second paper describes the first electrical domain solution to the non-linear dispersion for both transient and adiabatic chirp of directly modulated lasers. This is followed by a paper that describes the first optical burst-mode receiver with rapid power on/off functionality for a data-rate of 56Gb/s and a power efficiency of 2.2pJ/b in always-on mode.
{"title":"Session 16 overview: Advanced optical and wireline techniques: Wireline subcommittee","authors":"A. Emami-Neyestanak, A. Joy, F. O’Mahony","doi":"10.1109/ISSCC.2018.8310284","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310284","url":null,"abstract":"Electrical and optical links continue to provide challenges that cannot be overcome by process technology advances alone. The ingenuity of the designer is a major contribution, and this is clearly demonstrated by the papers in this session. The first is an invited paper that reviews state-ofthe-art optical interconnects in scalable, high-density standards-based switching fabrics for networking systems and cloud computing. The second paper describes the first electrical domain solution to the non-linear dispersion for both transient and adiabatic chirp of directly modulated lasers. This is followed by a paper that describes the first optical burst-mode receiver with rapid power on/off functionality for a data-rate of 56Gb/s and a power efficiency of 2.2pJ/b in always-on mode.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"14 1","pages":"262-263"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81757699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310311
M. Law, Taeik Kim, K. Makinwa
This session highlights the advances in state-of-the-art temperature, current, physical and chemical sensors. Three energy-efficient CMOS temperature sensors with the best figures of merit down to 34fJ·K2 are reported. Two current sensors (Papers 19.4 and 19.5) are presented, one demonstrating a high room-temperature gain accuracy with a ±4A input range, while the other shows a 160dB DR biosensor readout with 7ppm INL. An energy-efficient pressure-sensing system (Paper 19.6) and a high-resolution readout IC (Paper 19.7) are also reported. An energy-efficient CO2 sensor achieving 2x better resolution (94ppm) and >10x lower energy consumption (12mJ/meas) than the prior art is also described (Paper 19.8).
{"title":"Session 19 overview: Sensors and interfaces: Analog subcommittee","authors":"M. Law, Taeik Kim, K. Makinwa","doi":"10.1109/ISSCC.2018.8310311","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310311","url":null,"abstract":"This session highlights the advances in state-of-the-art temperature, current, physical and chemical sensors. Three energy-efficient CMOS temperature sensors with the best figures of merit down to 34fJ·K2 are reported. Two current sensors (Papers 19.4 and 19.5) are presented, one demonstrating a high room-temperature gain accuracy with a ±4A input range, while the other shows a 160dB DR biosensor readout with 7ppm INL. An energy-efficient pressure-sensing system (Paper 19.6) and a high-resolution readout IC (Paper 19.7) are also reported. An energy-efficient CO2 sensor achieving 2x better resolution (94ppm) and >10x lower energy consumption (12mJ/meas) than the prior art is also described (Paper 19.8).","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"49 1","pages":"316-317"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90509138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310169
T. Burd, M. Khellah, Byeong-Gyu Nam
Continued growth in cloud-to-edge applications is driving innovations in digital processors. The first two papers of this session cover next-generation server-class processors. This is followed by an energy-efficient 14nm graphics processor. An SoC configurable with 1–4 chips on an MCM to service multiple markets is described next. The last three papers demonstrate the first implementation of the datagram transport layer security (DTLS) protocol in hardware, an MSP430-compatible microcontroller with dual-mode enabling minimum-power and minimum-energy, and a net-zero-energy (NZE) smart mote SiP for IoT applications.
{"title":"Session 2 overview: Processors: Digital architectures and systems subcommittee","authors":"T. Burd, M. Khellah, Byeong-Gyu Nam","doi":"10.1109/ISSCC.2018.8310169","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310169","url":null,"abstract":"Continued growth in cloud-to-edge applications is driving innovations in digital processors. The first two papers of this session cover next-generation server-class processors. This is followed by an energy-efficient 14nm graphics processor. An SoC configurable with 1–4 chips on an MCM to service multiple markets is described next. The last three papers demonstrate the first implementation of the datagram transport layer security (DTLS) protocol in hardware, an MSP430-compatible microcontroller with dual-mode enabling minimum-power and minimum-energy, and a net-zero-energy (NZE) smart mote SiP for IoT applications.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"14 1","pages":"32-33"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86727991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310382
P. Mohseni, N. V. Helleputte, M. Ikeda
Advances in biomedical circuits and systems are essential technology drivers in addressing critical societal needs to increase the effectiveness and lower the cost of healthcare. This session highlights the latest advances in implantable, high-density, and wearable systems for neural recording, optogenetics, multimodal cell interfacing, and heart-rate monitoring.
{"title":"Session 29 overview: Advanced biomedical systems: IMMD subcommittee","authors":"P. Mohseni, N. V. Helleputte, M. Ikeda","doi":"10.1109/ISSCC.2018.8310382","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310382","url":null,"abstract":"Advances in biomedical circuits and systems are essential technology drivers in addressing critical societal needs to increase the effectiveness and lower the cost of healthcare. This session highlights the latest advances in implantable, high-density, and wearable systems for neural recording, optogenetics, multimodal cell interfacing, and heart-rate monitoring.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"74 1","pages":"458-459"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76195584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310363
M. Takamiya, Yen Hsun Hsu, A. Thomsen
The session on Power Converter Techniques presents improvements of power density, power efficiency and power dissipation in switched-capacitor, hybrid, linear and inductor-based DC-DC converters and power modulators. The first paper addresses the fully integrated fine-grained rational buck-boost converter with switched capacitor. The next four papers present innovative ideas in inductor-based DC-DC converters including capacitor-assisted hybrid DC-DC converters. This is followed by two high-frequency HPUE-capable envelope-tracking power modulators. An LDO is also presented that achieves good transient response under Hi-Lo-Hi transient stimulus. Finally, the last paper introduces the on-chip resonant-gate-drive SC converter for near-threshold computing.
{"title":"Session 27 overview: Power-converter techniques: Power management subcommittee","authors":"M. Takamiya, Yen Hsun Hsu, A. Thomsen","doi":"10.1109/ISSCC.2018.8310363","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310363","url":null,"abstract":"The session on Power Converter Techniques presents improvements of power density, power efficiency and power dissipation in switched-capacitor, hybrid, linear and inductor-based DC-DC converters and power modulators. The first paper addresses the fully integrated fine-grained rational buck-boost converter with switched capacitor. The next four papers present innovative ideas in inductor-based DC-DC converters including capacitor-assisted hybrid DC-DC converters. This is followed by two high-frequency HPUE-capable envelope-tracking power modulators. An LDO is also presented that achieves good transient response under Hi-Lo-Hi transient stimulus. Finally, the last paper introduces the on-chip resonant-gate-drive SC converter for near-threshold computing.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"11 1","pages":"420-421"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87069330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310347
R. Nonis, P. Hanumolu, F. O’Mahony
Clock generation circuits are ubiquitous building blocks in all electronic systems and are the fundamental performance limiters in many of them. This session covers the latest advances in clock generation for high-speed links. The first paper addresses a precision quadrature generator in the latest CMOS process, making use of injection-locking techniques. The second paper presents a technique for generating high-frequency reference clocks by quadrupling the frequency of commonly used, low-cost, crystal oscillators. The third paper demonstrates a fractional PLL that uses reference clock dithering and calibrated dither cancellation in the feedback loop to effectively attenuate fractional spurs. And the final paper describes a digital ring PLL that uses a fast phase correction method and proportional pulse calibration to reduce jitter.
{"title":"Session 25 overview: Clock generation for high-speed links: Wireline subcommittee","authors":"R. Nonis, P. Hanumolu, F. O’Mahony","doi":"10.1109/ISSCC.2018.8310347","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310347","url":null,"abstract":"Clock generation circuits are ubiquitous building blocks in all electronic systems and are the fundamental performance limiters in many of them. This session covers the latest advances in clock generation for high-speed links. The first paper addresses a precision quadrature generator in the latest CMOS process, making use of injection-locking techniques. The second paper presents a technique for generating high-frequency reference clocks by quadrupling the frequency of commonly used, low-cost, crystal oscillators. The third paper demonstrates a fractional PLL that uses reference clock dithering and calibrated dither cancellation in the feedback loop to effectively attenuate fractional spurs. And the final paper describes a digital ring PLL that uses a fast phase correction method and proportional pulse calibration to reduce jitter.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"90 1","pages":"388-389"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91029493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310331
K. Doris, Jan J. Westra, U. Moon
Extensive calibrations, the use of FinFET technology and architectural innovations continue to push the bandwidth and dynamic range envelopes of high-speed data converters. This session covers gigahertz data converters with resolutions from 8b up to 16b and sampling rates up to 72GS/s.
{"title":"Session 22 overview: Gigahertz data converters: Data converter subcommittee","authors":"K. Doris, Jan J. Westra, U. Moon","doi":"10.1109/ISSCC.2018.8310331","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310331","url":null,"abstract":"Extensive calibrations, the use of FinFET technology and architectural innovations continue to push the bandwidth and dynamic range envelopes of high-speed data converters. This session covers gigahertz data converters with resolutions from 8b up to 16b and sampling rates up to 72GS/s.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"82 1","pages":"356-357"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84347416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310231
A. Wong, Xin He, S. Pellerano
Wireless technologies continue to penetrate and support a wide range of application areas. This session includes state-of-the-art wireless transceivers for car radar, synthetic-aperture imaging radar, RF-to-bits cellular base stations, and 60GHz dual polarization MIMO. Furthermore, wireless techniques to enhance performance are presented, including a full duplex self-interference-cancellation FDD transceiver, an automatic tracking 3flo suppression notch filter technique for LTE HPUE and a high-efficiency outphasing PA using a triaxial balun combiner.
{"title":"Session 9 overview: Wireless transceivers and techniques: Wireless subcommittee","authors":"A. Wong, Xin He, S. Pellerano","doi":"10.1109/ISSCC.2018.8310231","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310231","url":null,"abstract":"Wireless technologies continue to penetrate and support a wide range of application areas. This session includes state-of-the-art wireless transceivers for car radar, synthetic-aperture imaging radar, RF-to-bits cellular base stations, and 60GHz dual polarization MIMO. Furthermore, wireless techniques to enhance performance are presented, including a full duplex self-interference-cancellation FDD transceiver, an automatic tracking 3flo suppression notch filter technique for LTE HPUE and a high-efficiency outphasing PA using a triaxial balun combiner.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"9 1","pages":"156-157"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81514723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-02-01DOI: 10.1109/ISSCC.2018.8310324
Jan Genoe, F. Gianesello, M. Nagata
This session includes six papers from the Technology Directions subcommittee at ISSCC 2018. The first two papers present advances in mixed signal processing for machine learning, the third paper describe a 32GHz mechanical resonator achieved for the first time in 14nm FinFET technology, the fourth paper reviews a 10Gb/s Si Photonics transceiver targeting 1Tb/s/mm2 die-to-die communication, the fifth paper describes an innovative sensor to detect laser fault injection attack on a cryptographic core in order to avoid any information exposure and the final paper presents an injection-locked VCO array targeting ESR application.
本次会议包括来自ISSCC 2018技术方向小组委员会的六篇论文。前两篇论文介绍了用于机器学习的混合信号处理的进展，第三篇论文描述了在14nm FinFET技术中首次实现的32GHz机械谐振器，第四篇论文回顾了10Gb/s Si Photonics收发器，目标是1Tb/s/mm2 die-to-die通信。第五篇论文描述了一种创新的传感器，用于检测加密核心上的激光故障注入攻击，以避免任何信息泄露;最后一篇论文提出了一种针对ESR应用的注入锁定VCO阵列。
{"title":"Session 21 overview: Extending silicon and its applications: Technology directions subcommittee","authors":"Jan Genoe, F. Gianesello, M. Nagata","doi":"10.1109/ISSCC.2018.8310324","DOIUrl":"https://doi.org/10.1109/ISSCC.2018.8310324","url":null,"abstract":"This session includes six papers from the Technology Directions subcommittee at ISSCC 2018. The first two papers present advances in mixed signal processing for machine learning, the third paper describe a 32GHz mechanical resonator achieved for the first time in 14nm FinFET technology, the fourth paper reviews a 10Gb/s Si Photonics transceiver targeting 1Tb/s/mm2 die-to-die communication, the fifth paper describes an innovative sensor to detect laser fault injection attack on a cryptographic core in order to avoid any information exposure and the final paper presents an injection-locked VCO array targeting ESR application.","PeriodicalId":6511,"journal":{"name":"2016 IEEE International Solid-State Circuits Conference (ISSCC)","volume":"15 1","pages":"342-343"},"PeriodicalIF":0.0,"publicationDate":"2018-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74173076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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