Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369272
Zheyu Zhang, Fred Wang, L. Tolbert, B. Blalock, D. Costinett
Four factors impact high speed switching of silicon carbide (SiC) devices in voltage source converters, including limited gate driving capability, cross-talk, parasitics associated in switching loop, and parasitics of inductive load. This paper focuses on a solution to mitigate the adverse impact of the aforementioned factors. First, an intelligent gate drive is developed for gate driving capability enhancement and cross-talk suppression. Second, placement and layout design of power devices, gate drive, and power stage board are proposed to minimize parasitics for fast switching and over-voltage mitigation. Third, an auxiliary filter is designed to mitigate the negative impact of inductive load's parasitics during the switching transient. Finally, by utilizing all techniques developed above, a three-phase voltage source inverter with Cree 1200-V/20-A SiC MOSFETs is established. Test results show that the switching behavior of SiC devices in actual three-phase voltage source inverter fed motor drives can mostly repeat the switching performance tested by the optimally-designed double pulse test.
影响电压源变换器中碳化硅器件高速开关性能的因素有四个:栅极驱动能力有限、串扰、开关回路中的寄生效应和感性负载的寄生效应。本文的重点是一个解决方案，以减轻上述因素的不利影响。首先，为了提高栅极驱动能力和抑制串扰，开发了一种智能栅极驱动器。其次，提出了功率器件、栅极驱动和功率级板的放置和布局设计，以最大限度地减少寄生，实现快速开关和过电压缓解。第三，设计了辅助滤波器，以减轻开关暂态过程中电感负载寄生的负面影响。最后，利用上述所有技术，建立了一个具有Cree 1200 v /20 a SiC mosfet的三相电压源逆变器。测试结果表明，SiC器件在实际三相电压源逆变器馈电电机驱动中的开关性能基本可以重复优化设计的双脉冲测试所测试的开关性能。
{"title":"Realization of high speed switching of SiC power devices in voltage source converters","authors":"Zheyu Zhang, Fred Wang, L. Tolbert, B. Blalock, D. Costinett","doi":"10.1109/WIPDA.2015.7369272","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369272","url":null,"abstract":"Four factors impact high speed switching of silicon carbide (SiC) devices in voltage source converters, including limited gate driving capability, cross-talk, parasitics associated in switching loop, and parasitics of inductive load. This paper focuses on a solution to mitigate the adverse impact of the aforementioned factors. First, an intelligent gate drive is developed for gate driving capability enhancement and cross-talk suppression. Second, placement and layout design of power devices, gate drive, and power stage board are proposed to minimize parasitics for fast switching and over-voltage mitigation. Third, an auxiliary filter is designed to mitigate the negative impact of inductive load's parasitics during the switching transient. Finally, by utilizing all techniques developed above, a three-phase voltage source inverter with Cree 1200-V/20-A SiC MOSFETs is established. Test results show that the switching behavior of SiC devices in actual three-phase voltage source inverter fed motor drives can mostly repeat the switching performance tested by the optimally-designed double pulse test.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"5 1","pages":"28-33"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87942039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369306
S. A. Moeini, Hannes Greve, F. McCluskey
The continuous increase in application temperatures of power electronic devices demands new packaging technologies capable of working reliably at high temperatures. Most critical among these new packaging technologies is the need for a new kind of interconnection due to the expanding ban on application of currently used lead containing solders in electronics. In this paper, the performance of a potential interconnect technology (TLPS) with low processing and high application temperatures is investigated under power cycling loading conditions. A test setup compatible with power packages was designed and assembled for this study. This test setup cycles and continuously monitors the temperature of power packages fabricated from a commercially available power diode, TLPS joints, and three types of substrates. Devices are cycled under constant current condition until failure. The failure criterion is defined as either an excessive (> 30%) increase in the maximum temperature of the power device or complete electrical failure of the device. The failed samples were destructively analyzed to identify failure modes and mechanisms. Optical Microscopy, Scanning Electron Microscopy (SEM), and Energy Dispersive Spectrometry (EDS) were used to perform a comprehensive failure analysis. The results show that the stiffness of Cu-Sn TLPS joints can result in fracture of the semiconductor device. The prevalent failure mode was diode failure (short-circuit) and fracture of the device under thermo-mechanical loading was identified as the failure mechanism. Finally, the reliability effects of using different substrates were investigated and compared.
{"title":"Reliability and failure analysis of Cu-Sn transient liquid phase sintered (TLPS) joints under power cycling loads","authors":"S. A. Moeini, Hannes Greve, F. McCluskey","doi":"10.1109/WIPDA.2015.7369306","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369306","url":null,"abstract":"The continuous increase in application temperatures of power electronic devices demands new packaging technologies capable of working reliably at high temperatures. Most critical among these new packaging technologies is the need for a new kind of interconnection due to the expanding ban on application of currently used lead containing solders in electronics. In this paper, the performance of a potential interconnect technology (TLPS) with low processing and high application temperatures is investigated under power cycling loading conditions. A test setup compatible with power packages was designed and assembled for this study. This test setup cycles and continuously monitors the temperature of power packages fabricated from a commercially available power diode, TLPS joints, and three types of substrates. Devices are cycled under constant current condition until failure. The failure criterion is defined as either an excessive (> 30%) increase in the maximum temperature of the power device or complete electrical failure of the device. The failed samples were destructively analyzed to identify failure modes and mechanisms. Optical Microscopy, Scanning Electron Microscopy (SEM), and Energy Dispersive Spectrometry (EDS) were used to perform a comprehensive failure analysis. The results show that the stiffness of Cu-Sn TLPS joints can result in fracture of the semiconductor device. The prevalent failure mode was diode failure (short-circuit) and fracture of the device under thermo-mechanical loading was identified as the failure mechanism. Finally, the reliability effects of using different substrates were investigated and compared.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"15 1","pages":"383-389"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89992419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369303
Lingxiao Xue, D. Boroyevich, P. Mattavelli
The approach of integrating a GaN phaseleg, current-boost drivers, and decoupling capacitors can significantly minimize the power loop inductance and the gate loop inductance. However, the driving scheme and sensing scheme are still critical and challenging in order to survive the highly noisy environment due to the GaN switching. A driving scheme of digital isolator plus isolated power supply is used for both switches of the phaseleg. To suppress the noise propagated to the PWM generating board, a common-mode choke and two Y-capacitors are used. A GaN boost converter proved the reduction of noise current through the PWM cables. For the sensing circuit design, filtering is necessary for all the sensors. Even with the filters, it turns out that only the DC current sensor can be placed with the phaseleg while the DC voltage sensor and AC current sensor have to stay away from the high dv/dt and di/dt nodes.
{"title":"Driving and sensing design of an enhancement-mode-GaN phaseleg as a building block","authors":"Lingxiao Xue, D. Boroyevich, P. Mattavelli","doi":"10.1109/WIPDA.2015.7369303","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369303","url":null,"abstract":"The approach of integrating a GaN phaseleg, current-boost drivers, and decoupling capacitors can significantly minimize the power loop inductance and the gate loop inductance. However, the driving scheme and sensing scheme are still critical and challenging in order to survive the highly noisy environment due to the GaN switching. A driving scheme of digital isolator plus isolated power supply is used for both switches of the phaseleg. To suppress the noise propagated to the PWM generating board, a common-mode choke and two Y-capacitors are used. A GaN boost converter proved the reduction of noise current through the PWM cables. For the sensing circuit design, filtering is necessary for all the sensors. Even with the filters, it turns out that only the DC current sensor can be placed with the phaseleg while the DC voltage sensor and AC current sensor have to stay away from the high dv/dt and di/dt nodes.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"1 1","pages":"34-40"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81974234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369273
K. Schoder, M. Steurer, F. Bogdan, J. Hauer, J. Langston, D. Boroyevich, R. Burgos, I. Cvetkovic, Zhiyu Shen, C. Dimarino
In recent years the interest in deriving new concepts for electric distribution systems that build on power electronics converter interfaces for system components has increased rapidly. This interest is based on the promise that the power electronics based interfaces between distribution and generation/loads bring about higher efficiency, compacter implementation, and improved controllability. Nevertheless, ensuring stability of these converter dominated systems is a challenge. One means of analyzing stability properties is through measuring impedances, i.e., measuring input and output impedances of connected components. This paper presents results of testing the first available medium voltage impedance measurement unit.
{"title":"Testing of a novel medium voltage impedance measurement unit","authors":"K. Schoder, M. Steurer, F. Bogdan, J. Hauer, J. Langston, D. Boroyevich, R. Burgos, I. Cvetkovic, Zhiyu Shen, C. Dimarino","doi":"10.1109/WIPDA.2015.7369273","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369273","url":null,"abstract":"In recent years the interest in deriving new concepts for electric distribution systems that build on power electronics converter interfaces for system components has increased rapidly. This interest is based on the promise that the power electronics based interfaces between distribution and generation/loads bring about higher efficiency, compacter implementation, and improved controllability. Nevertheless, ensuring stability of these converter dominated systems is a challenge. One means of analyzing stability properties is through measuring impedances, i.e., measuring input and output impedances of connected components. This paper presents results of testing the first available medium voltage impedance measurement unit.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"27 1","pages":"287-290"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80202885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369305
E. Zanoni, M. Meneghini, G. Meneghesso, D. Bisi, I. Rossetto, A. Stocco
Recent studies on the reliability of power Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs), Metal Insulator Semiconductor-HEMTs (MISHEMTs) and p-gate HEMTs are reviewed. When submitted to high electric field values, gate and insulating dielectrics as well as defective epitaxial layers are prone to time dependent breakdown mechanisms, charge trapping phenomena and generation of deep levels or interface states. This may originate degradation effects such as threshold voltage shifts and gate-drain or drain-source catastrophic breakdown. For most mechanisms, time to failure follows a Weibull distribution and lifetime extrapolation is possible using Arrhenius law and common electric field acceleration models.
{"title":"Reliability and failure physics of GaN HEMT, MIS-HEMT and p-gate HEMTs for power switching applications: Parasitic effects and degradation due to deep level effects and time-dependent breakdown phenomena","authors":"E. Zanoni, M. Meneghini, G. Meneghesso, D. Bisi, I. Rossetto, A. Stocco","doi":"10.1109/WIPDA.2015.7369305","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369305","url":null,"abstract":"Recent studies on the reliability of power Gallium Nitride (GaN) High Electron Mobility Transistors (HEMTs), Metal Insulator Semiconductor-HEMTs (MISHEMTs) and p-gate HEMTs are reviewed. When submitted to high electric field values, gate and insulating dielectrics as well as defective epitaxial layers are prone to time dependent breakdown mechanisms, charge trapping phenomena and generation of deep levels or interface states. This may originate degradation effects such as threshold voltage shifts and gate-drain or drain-source catastrophic breakdown. For most mechanisms, time to failure follows a Weibull distribution and lifetime extrapolation is possible using Arrhenius law and common electric field acceleration models.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"12 1","pages":"75-80"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73787206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369299
Tian Tian, L. Liang, Wei Xin, F. Luo
This paper presents a study of the influences of DBC metal trace layout on the reliability of the high power IGBT module. The research is conducted on a seven-layer IGBT package model using finite element analysis simulation. A parametric study is carried out at different temperatures to simulate the thermal-cycling scenario. It shows in simulation that both total deformation and thermal stress are not balanced even at the symmetrical edges of the module. The stress is related to the metal trace area on the DBC, and larger metal area results in higher thermal stress. Thermal-cycling experiment results verify the analysis to a certain extent. With this knowledge, the paper proposes an improved layout by adding grids to the metal area. The new design can reduce thermal stress and achieve higher reliability of the module.
{"title":"Influences of DBC metal layout on the reliability of IGBT power modules","authors":"Tian Tian, L. Liang, Wei Xin, F. Luo","doi":"10.1109/WIPDA.2015.7369299","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369299","url":null,"abstract":"This paper presents a study of the influences of DBC metal trace layout on the reliability of the high power IGBT module. The research is conducted on a seven-layer IGBT package model using finite element analysis simulation. A parametric study is carried out at different temperatures to simulate the thermal-cycling scenario. It shows in simulation that both total deformation and thermal stress are not balanced even at the symmetrical edges of the module. The stress is related to the metal trace area on the DBC, and larger metal area results in higher thermal stress. Thermal-cycling experiment results verify the analysis to a certain extent. With this knowledge, the paper proposes an improved layout by adding grids to the metal area. The new design can reduce thermal stress and achieve higher reliability of the module.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"96 3 1","pages":"166-169"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80556758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369284
Mohammed Alsolami, Jin Wang, L. Herrera
This paper presents a new approach for DC-link 120 Hz ripple power cancellation in single-phase DC/AC converter for renewable energy applications. The converter utilizes the superior features of the switched capacitor circuit and the gallium nitride devices to achieve high efficiency and power density. The system has two-port, the first acts as a pure capacitor and can achieve continuous variable ac capacitor 0 ~ Cac to absorb the 120 Hz dc ripple power whereas the second port is designed to be the output. A small size DC-link capacitor can be achieved through adjusting the phase angle between the two-ac port voltages of the converter to cancel the second-order frequency. The theoretical analysis confirms that the 2ω component can be entirely eliminated from the system and a 2 kW prototype is built to verify the circuit analysis. Comparing to the conventional H-bridge converter, the ac capacitance can be reduced by 80 times.
{"title":"DC ripple current reduction on multilevel, multiport, single-phase DC/AC converter for renewable energy applications","authors":"Mohammed Alsolami, Jin Wang, L. Herrera","doi":"10.1109/WIPDA.2015.7369284","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369284","url":null,"abstract":"This paper presents a new approach for DC-link 120 Hz ripple power cancellation in single-phase DC/AC converter for renewable energy applications. The converter utilizes the superior features of the switched capacitor circuit and the gallium nitride devices to achieve high efficiency and power density. The system has two-port, the first acts as a pure capacitor and can achieve continuous variable ac capacitor 0 ~ Cac to absorb the 120 Hz dc ripple power whereas the second port is designed to be the output. A small size DC-link capacitor can be achieved through adjusting the phase angle between the two-ac port voltages of the converter to cancel the second-order frequency. The theoretical analysis confirms that the 2ω component can be entirely eliminated from the system and a 2 kW prototype is built to verify the circuit analysis. Comparing to the conventional H-bridge converter, the ac capacitance can be reduced by 80 times.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"66 1","pages":"312-318"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90256930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369323
A. Rahman, K. Addington, M. Barlow, S. Ahmed, H. Mantooth, A. M. Francis
This paper demonstrates the first reported high temperature voltage comparator in CMOS silicon carbide. The comparator was designed in a 1.2 μm CMOS SiC process and has been tested for a voltage supply of 12 V to 15 V. The rail to rail voltage comparator has been tested up to 450°C with rise and fall times of 31 ns and 22 ns respectively, and positive and negative propagation delays of 108 ns and 107 ns respectively.
{"title":"A high temperature comparator in CMOS SiC","authors":"A. Rahman, K. Addington, M. Barlow, S. Ahmed, H. Mantooth, A. M. Francis","doi":"10.1109/WIPDA.2015.7369323","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369323","url":null,"abstract":"This paper demonstrates the first reported high temperature voltage comparator in CMOS silicon carbide. The comparator was designed in a 1.2 μm CMOS SiC process and has been tested for a voltage supply of 12 V to 15 V. The rail to rail voltage comparator has been tested up to 450°C with rise and fall times of 31 ns and 22 ns respectively, and positive and negative propagation delays of 108 ns and 107 ns respectively.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"8 1","pages":"236-240"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90812491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369289
Xiaoqing Song, A. Huang, Xijun Ni, Liqi Zhang
In order to better assist researchers to select the appropriate power device for medium voltage power electronics applications, this paper presents a comparative evaluation on three typical 6kV level Si and SiC power devices, including 6.5kV/25A Si IGBT from ABB, 6.5kV/15A normally off SiC JFET from USCi and a FREEDM System Center developed 6kV/26A SiC series-connected JFET. The 6.5kV Si IGBT and 6.5kV SiC JFET are packaged in the same module to minimize the effect of different parasitic inductance on the comparison. The 6kV SiC series-connected JFET is developed based on one 1.2kV SiC MOSFET from Cree and four 1.2kV SiC JFETs from Infineon, in this paper, named FREEDM Super-Cascode. A short introduction on the three selected devices are first given, then their forward conduction and switching performances are compared. Also, some additional features are discussed and compared, including the device size, cost, gate driver circuit complexity.
为了更好地帮助研究人员为中压电力电子应用选择合适的功率器件，本文对ABB公司的6.5kV/25A Si IGBT、USCi公司的6.5kV/15A常断SiC JFET和FREEDM系统中心开发的6kV/26A SiC串联JFET三种典型的6kV级Si和SiC功率器件进行了对比评估。6.5kV Si IGBT和6.5kV SiC JFET封装在同一个模块中，以尽量减少不同寄生电感对比较的影响。本文以Cree公司的一个1.2kV SiC MOSFET和英飞凌公司的四个1.2kV SiC JFET为基础，开发了6kV SiC串联JFET，命名为FREEDM Super-Cascode。首先对三种器件进行了简要介绍，然后比较了它们的正向导通和开关性能。此外，还讨论和比较了一些附加特性，包括器件尺寸、成本、栅极驱动电路的复杂性。
{"title":"Comparative evaluation of 6kV Si and SiC power devices for medium voltage power electronics applications","authors":"Xiaoqing Song, A. Huang, Xijun Ni, Liqi Zhang","doi":"10.1109/WIPDA.2015.7369289","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369289","url":null,"abstract":"In order to better assist researchers to select the appropriate power device for medium voltage power electronics applications, this paper presents a comparative evaluation on three typical 6kV level Si and SiC power devices, including 6.5kV/25A Si IGBT from ABB, 6.5kV/15A normally off SiC JFET from USCi and a FREEDM System Center developed 6kV/26A SiC series-connected JFET. The 6.5kV Si IGBT and 6.5kV SiC JFET are packaged in the same module to minimize the effect of different parasitic inductance on the comparison. The 6kV SiC series-connected JFET is developed based on one 1.2kV SiC MOSFET from Cree and four 1.2kV SiC JFETs from Infineon, in this paper, named FREEDM Super-Cascode. A short introduction on the three selected devices are first given, then their forward conduction and switching performances are compared. Also, some additional features are discussed and compared, including the device size, cost, gate driver circuit complexity.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"16 1","pages":"150-155"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90881522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-11-01DOI: 10.1109/WIPDA.2015.7369304
L. Liang, Ming Pan, Ludan Zhang, Yuxiong Shu
This paper focuses on the several key problems in the design and process for the new type pulsed power switch SiC RSD(reversely switched dynistor). By establishing the two-dimensional electro-thermal coupling model, the temperature rise during the turn-on process is discussed. The feasibility of the reverse injection pre-charge caused by avalanche breakdown is proved. The big influence of the carrier lifetime in drift layer and the proper distribution of the cell structure at anode are analyzed. Reasonable ohmic contact results suitable both for P and N type are acquired by process exploring. The surface breakdown voltage is enhanced by the bevel edge termination. The above work has provided basis for realizing the pulse turn-on of SiC RSD.
{"title":"Key structure and process for pulsed power switch SiC RSD","authors":"L. Liang, Ming Pan, Ludan Zhang, Yuxiong Shu","doi":"10.1109/WIPDA.2015.7369304","DOIUrl":"https://doi.org/10.1109/WIPDA.2015.7369304","url":null,"abstract":"This paper focuses on the several key problems in the design and process for the new type pulsed power switch SiC RSD(reversely switched dynistor). By establishing the two-dimensional electro-thermal coupling model, the temperature rise during the turn-on process is discussed. The feasibility of the reverse injection pre-charge caused by avalanche breakdown is proved. The big influence of the carrier lifetime in drift layer and the proper distribution of the cell structure at anode are analyzed. Reasonable ohmic contact results suitable both for P and N type are acquired by process exploring. The surface breakdown voltage is enhanced by the bevel edge termination. The above work has provided basis for realizing the pulse turn-on of SiC RSD.","PeriodicalId":6538,"journal":{"name":"2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA)","volume":"97 1","pages":"170-173"},"PeriodicalIF":0.0,"publicationDate":"2015-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81246818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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