Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351550
Long D. Nguyen, Dongyun Lin, Zhiping Lin, Jiuwen Cao
Deep convolutional neural networks (CNNs) have become one of the state-of-the-art methods for image classification in various domains. For biomedical image classification where the number of training images is generally limited, transfer learning using CNNs is often applied. Such technique extracts generic image features from nature image datasets and these features can be directly adopted for feature extraction in smaller datasets. In this paper, we propose a novel deep neural network architecture based on transfer learning for microscopic image classification. In our proposed network, we concatenate the features extracted from three pretrained deep CNNs. The concatenated features are then used to train two fully-connected layers to perform classification. In the experiments on both the 2D-Hela and the PAP-smear datasets, our proposed network architecture produces significant performance gains comparing to the neural network structure that uses only features extracted from single CNN and several traditional classification methods.
{"title":"Deep CNNs for microscopic image classification by exploiting transfer learning and feature concatenation","authors":"Long D. Nguyen, Dongyun Lin, Zhiping Lin, Jiuwen Cao","doi":"10.1109/ISCAS.2018.8351550","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351550","url":null,"abstract":"Deep convolutional neural networks (CNNs) have become one of the state-of-the-art methods for image classification in various domains. For biomedical image classification where the number of training images is generally limited, transfer learning using CNNs is often applied. Such technique extracts generic image features from nature image datasets and these features can be directly adopted for feature extraction in smaller datasets. In this paper, we propose a novel deep neural network architecture based on transfer learning for microscopic image classification. In our proposed network, we concatenate the features extracted from three pretrained deep CNNs. The concatenated features are then used to train two fully-connected layers to perform classification. In the experiments on both the 2D-Hela and the PAP-smear datasets, our proposed network architecture produces significant performance gains comparing to the neural network structure that uses only features extracted from single CNN and several traditional classification methods.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"16 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82643770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351650
Ka-Meng Lei, Pui-in Mak, R. Martins
Wearable and sensing electronics are evolving towards energy harvesting from the environment (e.g. thermal and solar energy). Ultra-low-voltage (ULV) circuits that allow direct-powering by sub-0.5 V energy sources can maximize the power efficiency. This work is a 0.4 V 65 nm CMOS relaxation oscillator with bootstrapped logic gates and outputs. The bootstrapped logic gates enable an output swing of 1.15 V surmounting the adverse effect of ULV digital circuits without extra voltage source. The ULV comparator with bulk-driven-inputs shows an 18 dB gain with 3 cascaded stages. Also, featuring a background delay-time cancellation scheme, the 3.3 MHz relaxation oscillator with built-in calibration exhibits a frequency deviation of ±0.71% and ±0.57% against temperature (−30 to 100 °C) and voltage (0.36 to 0.44 V) variations, respectively, from Monte-Carlo simulations (N=30). The simulated power consumption is 6.4 μW, resulting in an energy efficiency of 1.9 pJ per cycle.
{"title":"A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over −30 to 100 °C for Wearable and Sensing Applications","authors":"Ka-Meng Lei, Pui-in Mak, R. Martins","doi":"10.1109/ISCAS.2018.8351650","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351650","url":null,"abstract":"Wearable and sensing electronics are evolving towards energy harvesting from the environment (e.g. thermal and solar energy). Ultra-low-voltage (ULV) circuits that allow direct-powering by sub-0.5 V energy sources can maximize the power efficiency. This work is a 0.4 V 65 nm CMOS relaxation oscillator with bootstrapped logic gates and outputs. The bootstrapped logic gates enable an output swing of 1.15 V surmounting the adverse effect of ULV digital circuits without extra voltage source. The ULV comparator with bulk-driven-inputs shows an 18 dB gain with 3 cascaded stages. Also, featuring a background delay-time cancellation scheme, the 3.3 MHz relaxation oscillator with built-in calibration exhibits a frequency deviation of ±0.71% and ±0.57% against temperature (−30 to 100 °C) and voltage (0.36 to 0.44 V) variations, respectively, from Monte-Carlo simulations (N=30). The simulated power consumption is 6.4 μW, resulting in an energy efficiency of 1.9 pJ per cycle.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"19 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81228065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351586
Alfio Di Mauro, D. Rossi, A. Pullini, P. Flatresse, L. Benini
Energy efficiency is a crucial aspect in modern SoCs. Common strategies like aggressive voltage scaling and parallel processing have enabled major improvements in active energy efficiency. However, the big impact of process variations, as well as the temperature sensitivity of devices operating in near threshold force digital designers to adopt very conservative margins for timing closure.
{"title":"Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology","authors":"Alfio Di Mauro, D. Rossi, A. Pullini, P. Flatresse, L. Benini","doi":"10.1109/ISCAS.2018.8351586","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351586","url":null,"abstract":"Energy efficiency is a crucial aspect in modern SoCs. Common strategies like aggressive voltage scaling and parallel processing have enabled major improvements in active energy efficiency. However, the big impact of process variations, as well as the temperature sensitivity of devices operating in near threshold force digital designers to adopt very conservative margins for timing closure.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"19 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85158156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351137
J. Mishra, M. Jalili, Xinghuo Yu
This paper describes pinning synchronization of a complex dynamical network consisting of N identical nodes. The nodes are interconnected by a time-varying non-linear coupling terms, which has a general type with some constraints. Many non-linear coupling forms can be modeled as the one considered in this work. The network synchronization is achieved by using non-linear switching control. The stability of the synchronization is proven mathematically using Lyapunov analysis. It is shown that the proposed controller performs well in the presence of disturbances. Finally, simulation examples of Lorenz oscillator networks are given to verify the theoretical results. The simulations show that the proposed switching control outperforms classical linear control by providing not only faster synchronization, but also better robustness against external disturbances.
{"title":"Robust Pinning Synchronization of Complex Network with Non-linear Coupling using Switching Control","authors":"J. Mishra, M. Jalili, Xinghuo Yu","doi":"10.1109/ISCAS.2018.8351137","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351137","url":null,"abstract":"This paper describes pinning synchronization of a complex dynamical network consisting of N identical nodes. The nodes are interconnected by a time-varying non-linear coupling terms, which has a general type with some constraints. Many non-linear coupling forms can be modeled as the one considered in this work. The network synchronization is achieved by using non-linear switching control. The stability of the synchronization is proven mathematically using Lyapunov analysis. It is shown that the proposed controller performs well in the presence of disturbances. Finally, simulation examples of Lorenz oscillator networks are given to verify the theoretical results. The simulations show that the proposed switching control outperforms classical linear control by providing not only faster synchronization, but also better robustness against external disturbances.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89590413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The state-of-the-art High Efficiency Video Coding (HEVC) standard adopts the bi-prediction to improve the coding efficiency for B frame. However, the underlying assumption of this technique is that the motion field is characterized by the block-wise translational motion model, which may not be efficient in the challenging scenarios such as rotation and deformation. Inspired by the excellent signal level prediction capability of deep learning, we propose a bi-directional motion compensation algorithm with convolutional neural network, which is further incorporated into the video coding pipeline to improve the performance of video compression. Our network consists of six convolutional layers and a skip connection, which integrates the prediction error detection and non-linear signal prediction into an end-to-end framework. Experimental results show that by incorporating the proposed scheme into HEVC, up to 10.5% BD-rate savings and 3.1% BD-rate savings on average for random access (RA) configuration have been observed.
高效视频编码(High Efficiency Video Coding, HEVC)标准采用双预测技术来提高B帧的编码效率。然而，该技术的基本假设是运动场以块方向的平移运动模型为特征，这在旋转和变形等具有挑战性的场景中可能不是有效的。受深度学习出色的信号电平预测能力的启发，我们提出了一种基于卷积神经网络的双向运动补偿算法，并将其进一步整合到视频编码管道中，以提高视频压缩性能。我们的网络由六个卷积层和一个跳跃连接组成，它将预测误差检测和非线性信号预测集成到一个端到端框架中。实验结果表明，将所提出的方案纳入HEVC后，在随机接入(RA)配置下，平均可节省10.5%的bd速率和3.1%的bd速率。
{"title":"CNN-Based Bi-Directional Motion Compensation for High Efficiency Video Coding","authors":"Zhenghui Zhao, Shiqi Wang, Shanshe Wang, Xinfeng Zhang, Siwei Ma, Jiansheng Yang","doi":"10.1109/ISCAS.2018.8351189","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351189","url":null,"abstract":"The state-of-the-art High Efficiency Video Coding (HEVC) standard adopts the bi-prediction to improve the coding efficiency for B frame. However, the underlying assumption of this technique is that the motion field is characterized by the block-wise translational motion model, which may not be efficient in the challenging scenarios such as rotation and deformation. Inspired by the excellent signal level prediction capability of deep learning, we propose a bi-directional motion compensation algorithm with convolutional neural network, which is further incorporated into the video coding pipeline to improve the performance of video compression. Our network consists of six convolutional layers and a skip connection, which integrates the prediction error detection and non-linear signal prediction into an end-to-end framework. Experimental results show that by incorporating the proposed scheme into HEVC, up to 10.5% BD-rate savings and 3.1% BD-rate savings on average for random access (RA) configuration have been observed.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"7 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89661427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351028
Erwan Libessart, M. Arzel, C. Lahuec, F. Andriulli
The performance of non-invasive Brain-Computer Interface (BCI) depends on the computing performance of the system which solves the inverse problem. So the number of basic operations computed per second determines the BCI's resolution. An architecture with pipelined and parallelized flow is then required, and each operator in this architecture must be optimised to reach the highest possible computing performance. This paper presents the implementation of a fixed-point reciprocal and an inverse square root operators for the STMicroelectronics 65 nm CMOS technology. This paper follows previous works that optimise these operators on FPGA target. Each operator reaches a computing performance of about 40 Gop/s/mm2, which improves the literature results by a factor of 5. Thus, this works fits well for portable and high performance BCI applications.
{"title":"40 Gop/s/mm2 fixed-point operators for Brain Computer Interface in 65 nm CMOS","authors":"Erwan Libessart, M. Arzel, C. Lahuec, F. Andriulli","doi":"10.1109/ISCAS.2018.8351028","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351028","url":null,"abstract":"The performance of non-invasive Brain-Computer Interface (BCI) depends on the computing performance of the system which solves the inverse problem. So the number of basic operations computed per second determines the BCI's resolution. An architecture with pipelined and parallelized flow is then required, and each operator in this architecture must be optimised to reach the highest possible computing performance. This paper presents the implementation of a fixed-point reciprocal and an inverse square root operators for the STMicroelectronics 65 nm CMOS technology. This paper follows previous works that optimise these operators on FPGA target. Each operator reaches a computing performance of about 40 Gop/s/mm2, which improves the literature results by a factor of 5. Thus, this works fits well for portable and high performance BCI applications.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"95 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89507930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351566
A. Salimath, Giovanni Gonano, E. Bonizzoni, D. Brambilla, E. Botti, F. Maloberti
This paper presents two design considerations for integrated high-voltage DC-DC converters in automobile and industrial applications. The proposed solutions include (i) a quasi soft-start technique using over-current protection (OCP) circuits and limited duty cycle control and (ii) a technique to drive a floating load-side switch that suppresses the effect of bond-wire bouncing on its gate-source voltage. The first technique avoids the conventional, overhead start-up circuits and significantly reduces the converter startup time. The second technique gains importance primarily from device reliability viewpoint in high-voltage (HV) conditions. The effectiveness of the proposed techniques has been verified with simulations at the transistor level using a 110-nm BCD technology.
{"title":"Design Considerations for Integrated, High-Voltage DC-DC Converters","authors":"A. Salimath, Giovanni Gonano, E. Bonizzoni, D. Brambilla, E. Botti, F. Maloberti","doi":"10.1109/ISCAS.2018.8351566","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351566","url":null,"abstract":"This paper presents two design considerations for integrated high-voltage DC-DC converters in automobile and industrial applications. The proposed solutions include (i) a quasi soft-start technique using over-current protection (OCP) circuits and limited duty cycle control and (ii) a technique to drive a floating load-side switch that suppresses the effect of bond-wire bouncing on its gate-source voltage. The first technique avoids the conventional, overhead start-up circuits and significantly reduces the converter startup time. The second technique gains importance primarily from device reliability viewpoint in high-voltage (HV) conditions. The effectiveness of the proposed techniques has been verified with simulations at the transistor level using a 110-nm BCD technology.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"16 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87030151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351822
M. Franceschi, L. Seminara, S. Došen, L. Pinna, Luigi Fares, M. Saleh, M. Valle, D. Farina
Closing the prosthesis control loop by providing tactile sensory feedback to the user is a key point in research on active prosthetics as well as an often cited requirement of the prosthesis users.
通过向使用者提供触觉反馈来关闭义肢控制回路是主动义肢研究的重点，也是义肢使用者经常提出的要求。
{"title":"Live Demonstration: Electrotactile feedback from an electronic skin through flexible electrode matrix","authors":"M. Franceschi, L. Seminara, S. Došen, L. Pinna, Luigi Fares, M. Saleh, M. Valle, D. Farina","doi":"10.1109/ISCAS.2018.8351822","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351822","url":null,"abstract":"Closing the prosthesis control loop by providing tactile sensory feedback to the user is a key point in research on active prosthetics as well as an often cited requirement of the prosthesis users.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"12 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89845014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351842
Wenshuo Tang, M. Andoni, V. Robu, D. Flynn
In this paper we present a review into data driven prognostics and its relevance to resilience in energy systems. A data driven remaining useful life prediction for Li-ion batteries utilizing data analysis via a relevance vector machine (RVM) model is shown to be within 5% accuracy when applied to large lifecycle datasets. Results demonstrate that due to the agile nature of prognostic models and their accuracy, prognostics and health management methods will be vital to resilient and sustainable energy systems.
{"title":"Accurately Forecasting the Health of Energy System Assets","authors":"Wenshuo Tang, M. Andoni, V. Robu, D. Flynn","doi":"10.1109/ISCAS.2018.8351842","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351842","url":null,"abstract":"In this paper we present a review into data driven prognostics and its relevance to resilience in energy systems. A data driven remaining useful life prediction for Li-ion batteries utilizing data analysis via a relevance vector machine (RVM) model is shown to be within 5% accuracy when applied to large lifecycle datasets. Results demonstrate that due to the agile nature of prognostic models and their accuracy, prognostics and health management methods will be vital to resilient and sustainable energy systems.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"27 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90376398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent progress on quantum physics shows that quantum computers may be a reality in the not too distant future. Based on new mathematical hard problems, post-quantum cryptography (PQC) has been studied to make sure the attacks from quantum computers can be resistant. The latest supersingular isogeny Diffie-Hellman (SIDH) key exchange protocol shows promising security properties among various post-quantum cryptosystems. In this paper, we propose an improved modular multiplication algorithm with special primes that can be used in SIDH key exchange protocol. Both software and hardware implementations are provided and compared with original modular multiplication algorithm. The results show that the software results of improved algorithm can be 24% faster than the original software implementation, while the hardware implementation based on the proposed hardware architecture can be 6 times faster than previous hardware implementation.
{"title":"Design and Optimization of Modular Multiplication for SIDH","authors":"Chunyang Liu, Jian Ni, Weiqiang Liu, Zhe Liu, Máire O’Neill","doi":"10.1109/ISCAS.2018.8351082","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351082","url":null,"abstract":"Recent progress on quantum physics shows that quantum computers may be a reality in the not too distant future. Based on new mathematical hard problems, post-quantum cryptography (PQC) has been studied to make sure the attacks from quantum computers can be resistant. The latest supersingular isogeny Diffie-Hellman (SIDH) key exchange protocol shows promising security properties among various post-quantum cryptosystems. In this paper, we propose an improved modular multiplication algorithm with special primes that can be used in SIDH key exchange protocol. Both software and hardware implementations are provided and compared with original modular multiplication algorithm. The results show that the software results of improved algorithm can be 24% faster than the original software implementation, while the hardware implementation based on the proposed hardware architecture can be 6 times faster than previous hardware implementation.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"77 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90291372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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