Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351037
M. Gottardi, M. Lecca
This paper presents a 64 × 64 pixels vision sensor embedding pixel-wise computation of the Local Binary Pattern (LBP) code, which is an oriented, binary, vector contrast that is widely used for texture description and retrieval. For each pixel, the sensor estimates the LBP code over four neighbors in a 3×3 pixel kernel. The image processing is performed inside each pixel during the integration time over a dynamic range up to 98dB, thanks to a pixel-level auto-exposure control. The contrast detection relies on the estimation of the time difference between two pixels thresholded against two reference voltages. The four binary signed contrast vectors are delivered to the output, coded into 4-bit/pixel. The 0.35μm CMOS sensor features a power consumption of 35μW at 3.3V and 15fps.
{"title":"A 35μW 64 × 64 Pixels Vision Sensor Embedding Local Binary Pattern Code Computation","authors":"M. Gottardi, M. Lecca","doi":"10.1109/ISCAS.2018.8351037","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351037","url":null,"abstract":"This paper presents a 64 × 64 pixels vision sensor embedding pixel-wise computation of the Local Binary Pattern (LBP) code, which is an oriented, binary, vector contrast that is widely used for texture description and retrieval. For each pixel, the sensor estimates the LBP code over four neighbors in a 3×3 pixel kernel. The image processing is performed inside each pixel during the integration time over a dynamic range up to 98dB, thanks to a pixel-level auto-exposure control. The contrast detection relies on the estimation of the time difference between two pixels thresholded against two reference voltages. The four binary signed contrast vectors are delivered to the output, coded into 4-bit/pixel. The 0.35μm CMOS sensor features a power consumption of 35μW at 3.3V and 15fps.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"56 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77447936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351240
T. He, Runxi Zhang, Hui Yang, Jiefu Wang, C. Shi
This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is −114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than −51.3 dBc.
{"title":"A Ka-band Dual Co-tuning Frequency Synthesizer with 21.9% Locking Range and Sub-200 fs RMS Jitter in CMOS for 5G mm-Wave Applications","authors":"T. He, Runxi Zhang, Hui Yang, Jiefu Wang, C. Shi","doi":"10.1109/ISCAS.2018.8351240","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351240","url":null,"abstract":"This paper presents a Ka-band integer-N quadrature frequency synthesizer for 5G mm-wave communication applications. It utilizes a dual co-tuning in-phase injection-coupled quadrature voltage-controlled oscillator (IPIC-QVCO) including differential coplanar waveguide (DCPW), digitally-controlled coarse co-tuning varactor array (DCCVA), and analog-controlled fine co-tuning varactors (AFCV) and a matched injection-locked frequency divider (ILFD) to achieve wide locking range (LR), low phase noise, and small phase error. Even fabricated in low cost and large parasitic 0.13 μm CMOS, it still achieves 21.9% LR from 26.7 to 33.27 GHz, the phase noise is −114.06 dBc/Hz at 10 MHz offset from 29.832 GHz carrier, the RMS jitter is 198.8 fs, and the reference spurs are less than −51.3 dBc.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"197 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77748474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351247
Rongdi Sun, Peilin Liu, Cecil Accetti, A. Naqvi, Haroon Ahmed, J. Qian
Deep neural networks dominate in the machine learning field. However, deploying deep neural networks on mobile devices requires aggressive compression of models due to huge amounts of parameters. An extreme case is to restrict weights to binary values {+1/−1} without much loss of accuracy. This promising method not only reduces hardware overhead of memory and computation, but also improves the performance of network inference. In this work, a flexible architecture for binary weight network acceleration is proposed. The architecture fully exploits the inherent multi-level parallelism of neural networks, resulting in utilization of processing elements over 80% for different layers. In addition, we present efficient data placement and transmission methods in coordination with multi-level parallel processing. The accelerator is implemented using SMIC 40nm technology. It operates at 1.2V and achieves up to 974GOPS/W power efficiency.
{"title":"A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration","authors":"Rongdi Sun, Peilin Liu, Cecil Accetti, A. Naqvi, Haroon Ahmed, J. Qian","doi":"10.1109/ISCAS.2018.8351247","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351247","url":null,"abstract":"Deep neural networks dominate in the machine learning field. However, deploying deep neural networks on mobile devices requires aggressive compression of models due to huge amounts of parameters. An extreme case is to restrict weights to binary values {+1/−1} without much loss of accuracy. This promising method not only reduces hardware overhead of memory and computation, but also improves the performance of network inference. In this work, a flexible architecture for binary weight network acceleration is proposed. The architecture fully exploits the inherent multi-level parallelism of neural networks, resulting in utilization of processing elements over 80% for different layers. In addition, we present efficient data placement and transmission methods in coordination with multi-level parallel processing. The accelerator is implemented using SMIC 40nm technology. It operates at 1.2V and achieves up to 974GOPS/W power efficiency.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"130 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76263386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351725
Omer Tanovic, R. Ma, Huifang Sun
Radio frequency pulse-width modulation (RF-PWM) has been used as a power coding method in all-digital transmitters, which employ highly efficient switched-mode power amplifiers (SMPA). The main drawback of RF-PWM is the high level of in-band harmonic distortion when digitally implemented. In order to reduce spectral aliasing effects and produce acceptable levels of harmonic noise, ultra-fast clock speeds are required, making it commercially infeasible. In this paper, we derive a novel compact analytical model of a multilevel digital RF-PWM, driven by an arbitrary bounded baseband signal. We show that the spectral aliasing effects are equivalent to a particular amplitude quantization of the input baseband signal. This result implies that highly linear digital RF-PWM can be realized with modest clock speeds if and only if the input baseband signal is pre-quantized according to the inherent quantization process. We provide full description of this quantization process and describe its dependence on RF-PWM design parameters. Presented results enable a complete understanding of the nonlinear behavior of digitally implemented RF-PWM, and therefore can aid in optimal transceiver design. Numerical simulations in MATLAB were used to verify the derived analytical expressions.
{"title":"Compact Analytical Description of Digital Radio-Frequency Pulse-Width Modulated Signals","authors":"Omer Tanovic, R. Ma, Huifang Sun","doi":"10.1109/ISCAS.2018.8351725","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351725","url":null,"abstract":"Radio frequency pulse-width modulation (RF-PWM) has been used as a power coding method in all-digital transmitters, which employ highly efficient switched-mode power amplifiers (SMPA). The main drawback of RF-PWM is the high level of in-band harmonic distortion when digitally implemented. In order to reduce spectral aliasing effects and produce acceptable levels of harmonic noise, ultra-fast clock speeds are required, making it commercially infeasible. In this paper, we derive a novel compact analytical model of a multilevel digital RF-PWM, driven by an arbitrary bounded baseband signal. We show that the spectral aliasing effects are equivalent to a particular amplitude quantization of the input baseband signal. This result implies that highly linear digital RF-PWM can be realized with modest clock speeds if and only if the input baseband signal is pre-quantized according to the inherent quantization process. We provide full description of this quantization process and describe its dependence on RF-PWM design parameters. Presented results enable a complete understanding of the nonlinear behavior of digitally implemented RF-PWM, and therefore can aid in optimal transceiver design. Numerical simulations in MATLAB were used to verify the derived analytical expressions.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"32 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76775533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a low-power All-MOSFET voltage reference implemented on a 0.18-μm standard CMOS technology. In order to improve the temperature coefficient (TC) of voltage reference, a TC compensation technique based on controlling bulk voltage is proposed. The proposed voltage reference achieves a TC of 13 ppm/°C from −40 °C to 125 °C while dissipating a supply current of 70 nA in normal temperature. The line regulation is 0.02%/V when the supply voltage varies from 1.3 V to 2.1 V, and the power supply rejection ratio (PSRR) at 100Hz is 74 dB due to the cascode current mirror. Moreover, the current mirror can be reconfigured easily so that the output voltage can be trimmed in this design.
本文提出了一种基于0.18 μm标准CMOS技术实现的低功耗全mosfet基准电压。为了提高基准电压的温度系数，提出了一种基于控制整体电压的基准电压补偿技术。在- 40°C至125°C范围内，建议的基准电压达到13 ppm/°C，而在常温下耗散70 nA的电源电流。当电源电压在1.3 V ~ 2.1 V范围内变化时，线路稳压为0.02%/V，由于级联电流反射，100Hz时电源抑制比(PSRR)为74 dB。此外，电流反射镜可以很容易地重新配置，以便在该设计中可以修剪输出电压。
{"title":"A 70-nA 13-ppm/°C All-MOSFET Voltage Reference for Low-Power IoT Systems","authors":"Jianping Guo, Weimin Li, Yicheng Li, Siji Huang, Zhao Wang, Bing Mo, Dihu Chen","doi":"10.1109/ISCAS.2018.8351792","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351792","url":null,"abstract":"This paper presents a low-power All-MOSFET voltage reference implemented on a 0.18-μm standard CMOS technology. In order to improve the temperature coefficient (TC) of voltage reference, a TC compensation technique based on controlling bulk voltage is proposed. The proposed voltage reference achieves a TC of 13 ppm/°C from −40 °C to 125 °C while dissipating a supply current of 70 nA in normal temperature. The line regulation is 0.02%/V when the supply voltage varies from 1.3 V to 2.1 V, and the power supply rejection ratio (PSRR) at 100Hz is 74 dB due to the cascode current mirror. Moreover, the current mirror can be reconfigured easily so that the output voltage can be trimmed in this design.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"457 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77404954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351264
R. Figueras, J. M. Margarit, G. Vergara, V. Villamayor, R. Gutiérrez-Álvarez, C. Fernández-Montojo, L. Terés, F. Serra-Graells
This paper presents a 128 × 128-pix high-speed PbSe-CMOS uncooled MWIR imager with pixel digital output. The proposed in-pixel A/D converter based on integrate-and-fire modulation achieves good linearity even at 20 Meps thanks to its soft-reset mechanism. Class-AB CMOS circuits are proposed to keep static power consumption below 10 μW/pix. Each DPS cell also includes its own analog reference and bias generator. The resulting pixel digital-only I/O interface ensures low crosstalk at the FPA level. From post-layout simulation results, the imager is capable of delivering 14 bit up to 1 kfps or alternatively 4 kfps up to 10 bit. The presented MWIR imager is currently being integrated in the 0.18-μm 1P6M CMOS technology from X-FAB.
{"title":"A 128× 128-pix 4-kfps 14-bit Digital-Pixel PbSe-CMOS Uncooled MWIR Imager","authors":"R. Figueras, J. M. Margarit, G. Vergara, V. Villamayor, R. Gutiérrez-Álvarez, C. Fernández-Montojo, L. Terés, F. Serra-Graells","doi":"10.1109/ISCAS.2018.8351264","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351264","url":null,"abstract":"This paper presents a 128 × 128-pix high-speed PbSe-CMOS uncooled MWIR imager with pixel digital output. The proposed in-pixel A/D converter based on integrate-and-fire modulation achieves good linearity even at 20 Meps thanks to its soft-reset mechanism. Class-AB CMOS circuits are proposed to keep static power consumption below 10 μW/pix. Each DPS cell also includes its own analog reference and bias generator. The resulting pixel digital-only I/O interface ensures low crosstalk at the FPA level. From post-layout simulation results, the imager is capable of delivering 14 bit up to 1 kfps or alternatively 4 kfps up to 10 bit. The presented MWIR imager is currently being integrated in the 0.18-μm 1P6M CMOS technology from X-FAB.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"3 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80305537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351770
Vili Viitamäki, Panu Sjövall, Jarno Vanne, T. Hämäläinen, A. Kulmala
This paper describes a demonstration setup for real-time 4K HEVC intra coding. The system is built on Kvazaar open-source HEVC encoder partitioned between 22-core Xeon processor and two Arria 10 FPGAs. The demonstrator supports 1) live streaming of up to three 4K30p videos; or 2) offline video streaming up to 4K100p format. Live feeds are shot by three cameras whereas offline video is accessed from a local hard drive. In both cases, encoded bit stream is sent over a wired connection and played back by laptop(s). The demonstrated HEVC coding speed is over three times as fast as that of a pure software solution.
{"title":"Live Demonstration: 4K100p HEVC Intra Encoder","authors":"Vili Viitamäki, Panu Sjövall, Jarno Vanne, T. Hämäläinen, A. Kulmala","doi":"10.1109/ISCAS.2018.8351770","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351770","url":null,"abstract":"This paper describes a demonstration setup for real-time 4K HEVC intra coding. The system is built on Kvazaar open-source HEVC encoder partitioned between 22-core Xeon processor and two Arria 10 FPGAs. The demonstrator supports 1) live streaming of up to three 4K30p videos; or 2) offline video streaming up to 4K100p format. Live feeds are shot by three cameras whereas offline video is accessed from a local hard drive. In both cases, encoded bit stream is sent over a wired connection and played back by laptop(s). The demonstrated HEVC coding speed is over three times as fast as that of a pure software solution.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"17 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75762425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351775
N. Sidaty, Marko Viitanen, W. Hamidouche, Jarno Vanne, O. Déforges
This paper presents a demonstration setup for live HEVC video coding with Region of Interest (ROI) encryption. The showcased approach splits video frames into independent HEVC tiles and encrypts those belonging to the ROI. This end-to-end content protection scheme is put into practice by integrating the algorithms of selective encryption into Kvazaar HEVC encoder and decryption into openHEVC decoder. The shown implementation performs secure encryption of the ROI in real time with small bit rate and complexity overhead.
{"title":"Live Demonstration: End-to-End Real-Time ROI-based Encryption in HEVC Videos","authors":"N. Sidaty, Marko Viitanen, W. Hamidouche, Jarno Vanne, O. Déforges","doi":"10.1109/ISCAS.2018.8351775","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351775","url":null,"abstract":"This paper presents a demonstration setup for live HEVC video coding with Region of Interest (ROI) encryption. The showcased approach splits video frames into independent HEVC tiles and encrypts those belonging to the ROI. This end-to-end content protection scheme is put into practice by integrating the algorithms of selective encryption into Kvazaar HEVC encoder and decryption into openHEVC decoder. The shown implementation performs secure encryption of the ROI in real time with small bit rate and complexity overhead.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"22 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81756002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351193
V. Riess, P. V. Testa, C. Carta, F. Ellinger
This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of −4 dBm at the 1 dB compression point with a −3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of −15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.
{"title":"Analysis and Design of a 60 GHz Fully-Differential Frequency Doubler in 130 nm SiGe BiCMOS","authors":"V. Riess, P. V. Testa, C. Carta, F. Ellinger","doi":"10.1109/ISCAS.2018.8351193","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351193","url":null,"abstract":"This paper presents a fully-differential frequency doubler integrated in 130 nm SiGe BiCMOS technology. To obtain a differential output signal, the conventional push-push topology is extended. The benefits of this approach are investigated with non-linear circuit analysis and discussed. While both the conventional push-push doubler and the Gilbert-cell doubler only suppress the odd harmonics, the extended topology enables the further suppression of the fourth harmonic. The circuit requires a set of phase-shifted versions of the input signal, which are generated on-chip with a polyphase filter. The proposed approach is validated with measurements of the fabricated circuit: an output power of −4 dBm at the 1 dB compression point with a −3 dB output bandwidth of 10 GHz from 55.6 GHz to 65.6 GHz is reported. With a low power consumption of 23.5 mW, a conversion gain of −15 dB and a fundamental suppression of 42 dB are achieved around the center frequency. A method to improve the conversion gain is discussed in the conclusion.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"13 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79672534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351502
Axel Hanuschek, Martin Hantschke, I. Triantis, D. Sideris
Electrophoresis is a versatile method for the separation and analysis of proteins, DNA or RNA and other analytes. The applied electric field induces electric currents which generate Joule heating due to the buffer solution's resistance. The generated heat changes the mobility and diffusion coefficient of the analytes and therefore it degrades the system's performance. In order to investigate the spatial profile of temperature variations during electrophoresis, a comprehensive microfluidic system was modelled and validated. The physical characteristics such as electric field, current density, temperature generation, heat transfer and fluid flow were simulated in a vertical and horizontal two-dimensional working plane along the separation channel. An optimization study identified potential for improvement in order to reduce high temperature gradients and improve the heat transfer away from the separation channel. Due to the low thermal conductivity of air, a reduction in the chip thickness leads to an increase in temperature when not deploying sufficient cooling. Attaching a copper plate results in a maximal reduction of 49.1% due to its high thermal conductivity, while an active cooling 5°C below room temperature allows for an efficient heat dissipation resulting in 107% reduction in the highest temperature value.
{"title":"Simulation of Temperature Profiles due to Joule Heating in Microfluidic Systems","authors":"Axel Hanuschek, Martin Hantschke, I. Triantis, D. Sideris","doi":"10.1109/ISCAS.2018.8351502","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351502","url":null,"abstract":"Electrophoresis is a versatile method for the separation and analysis of proteins, DNA or RNA and other analytes. The applied electric field induces electric currents which generate Joule heating due to the buffer solution's resistance. The generated heat changes the mobility and diffusion coefficient of the analytes and therefore it degrades the system's performance. In order to investigate the spatial profile of temperature variations during electrophoresis, a comprehensive microfluidic system was modelled and validated. The physical characteristics such as electric field, current density, temperature generation, heat transfer and fluid flow were simulated in a vertical and horizontal two-dimensional working plane along the separation channel. An optimization study identified potential for improvement in order to reduce high temperature gradients and improve the heat transfer away from the separation channel. Due to the low thermal conductivity of air, a reduction in the chip thickness leads to an increase in temperature when not deploying sufficient cooling. Attaching a copper plate results in a maximal reduction of 49.1% due to its high thermal conductivity, while an active cooling 5°C below room temperature allows for an efficient heat dissipation resulting in 107% reduction in the highest temperature value.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81621944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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