Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351181
D. Biel, J. Scherpen
This work presents the design guidelines of a control for direct regulation of the voltage amplitude at the connection point of a single-phase grid-connected PV inverter. The parameters of the control are designed for ensuring local asymptotic stability for a given range of the impedance. Furthermore, the control includes a strategy of active power curtailment in order to avoid the injection of a large amount of reactive power to the grid. Numerical simulations confirm the expected voltage regulation and the control robustness with respect to the grid impedance variations without the requirement of any estimation or measure of the actual impedance.
{"title":"Voltage regulation with power curtailment in a single-phase grid-connected PV inverter","authors":"D. Biel, J. Scherpen","doi":"10.1109/ISCAS.2018.8351181","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351181","url":null,"abstract":"This work presents the design guidelines of a control for direct regulation of the voltage amplitude at the connection point of a single-phase grid-connected PV inverter. The parameters of the control are designed for ensuring local asymptotic stability for a given range of the impedance. Furthermore, the control includes a strategy of active power curtailment in order to avoid the injection of a large amount of reactive power to the grid. Numerical simulations confirm the expected voltage regulation and the control robustness with respect to the grid impedance variations without the requirement of any estimation or measure of the actual impedance.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89788225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351691
S. Lai, Giulia Casula, P. Cosseddu, A. Bonfiglio, M. Barbaro, F. D'Annunzio, C. Loussert, L. Basiricò, A. Ciavatti, B. Fraboni, Vincent Fischer
A custom, all-organic circuit based on low voltage Organic Field-Effect Transistors conceived for the monitoring of security check of luggage in airports is reported. The proposed circuit integrates on the same plastic substrate an X-Rays exposure detector, a digitization and storing module altogether with an interface to a commercial RFID chip for event readout. A complete description of the developed circuit is reported; simulations of each single block and of the whole system are presented. Fabrication and characterization of the circuit under X-Rays are described.
{"title":"All-Polymer Integrated Circuit for Monitoring the X-Ray Checking History of Luggages","authors":"S. Lai, Giulia Casula, P. Cosseddu, A. Bonfiglio, M. Barbaro, F. D'Annunzio, C. Loussert, L. Basiricò, A. Ciavatti, B. Fraboni, Vincent Fischer","doi":"10.1109/ISCAS.2018.8351691","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351691","url":null,"abstract":"A custom, all-organic circuit based on low voltage Organic Field-Effect Transistors conceived for the monitoring of security check of luggage in airports is reported. The proposed circuit integrates on the same plastic substrate an X-Rays exposure detector, a digitization and storing module altogether with an interface to a commercial RFID chip for event readout. A complete description of the developed circuit is reported; simulations of each single block and of the whole system are presented. Fabrication and characterization of the circuit under X-Rays are described.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"48 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86716019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351412
Kyle Juretus, I. Savidis
In this paper, the state space of an integrated circuit (IC) is used to increase the security of an IC against a variety of threats including intellectual property theft, IC counterfeiting, and IC overproduction. Hidden state transitions, state dependent keys, and temporal based transitions are implemented as a means to combat probing style attacks, such as the SAT attack. SPICE simulations are performed on modified state machines to characterize the overhead of implementing the three techniques in a circuit. Implementing temporal based transitions increases the area of the circuit by 68.42%, the power by 43.17%, and did not impact circuit delay. However, increasing the circuit size significantly reduces the overhead of state space encryption. For example, encrypting two registers in the s15850 ISCAS89 benchmark circuit resulted in an area overhead of 0.026%, presenting a low overhead means of securing sequential logic.
{"title":"Time Domain Sequential Locking for Increased Security","authors":"Kyle Juretus, I. Savidis","doi":"10.1109/ISCAS.2018.8351412","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351412","url":null,"abstract":"In this paper, the state space of an integrated circuit (IC) is used to increase the security of an IC against a variety of threats including intellectual property theft, IC counterfeiting, and IC overproduction. Hidden state transitions, state dependent keys, and temporal based transitions are implemented as a means to combat probing style attacks, such as the SAT attack. SPICE simulations are performed on modified state machines to characterize the overhead of implementing the three techniques in a circuit. Implementing temporal based transitions increases the area of the circuit by 68.42%, the power by 43.17%, and did not impact circuit delay. However, increasing the circuit size significantly reduces the overhead of state space encryption. For example, encrypting two registers in the s15850 ISCAS89 benchmark circuit resulted in an area overhead of 0.026%, presenting a low overhead means of securing sequential logic.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"11 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89487117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351883
K. Mamun, N. Mcfarlane
This live demonstration showcases a portable bowel sound identification system. The system consists of a charge amplifier interfaced with a piezoelectric sensor. An identification unit, consisting of peak and trough detectors, differentiators, integrators and comparators, combine to positively identify bowel sounds. The system has an 85% identification rate, uses 53 μW of power, and is implemented in a 0.96 mm2 area. The designed system is suitable for integration with other sensing systems.
{"title":"Live Demonstration: Portable Bowel Sound Idenfication System","authors":"K. Mamun, N. Mcfarlane","doi":"10.1109/ISCAS.2018.8351883","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351883","url":null,"abstract":"This live demonstration showcases a portable bowel sound identification system. The system consists of a charge amplifier interfaced with a piezoelectric sensor. An identification unit, consisting of peak and trough detectors, differentiators, integrators and comparators, combine to positively identify bowel sounds. The system has an 85% identification rate, uses 53 μW of power, and is implemented in a 0.96 mm2 area. The designed system is suitable for integration with other sensing systems.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88580418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351049
Deepak Mishra, S. Chaudhury, M. Sarkar, Sidharth Manohar, A. Soin
Vascular region segmentation in ultrasound images is necessary for applications like automatic registration, and surgical navigation. In this paper, a pipelined network comprising of a convolutional neural network (CNN) followed by unsupervised clustering is proposed to perform vessel segmentation in liver ultrasound images. The work is motivated by the tremendous success of CNNs in object detection and localization. CNN here is trained to localize vascular regions, which are subsequently segmented by the clustering. The proposed network results in 99.14% pixel accuracy and 69.62% mean region intersection over union on 132 images. These values are better than some existing methods.
{"title":"Segmentation of Vascular Regions in Ultrasound Images: A Deep Learning Approach","authors":"Deepak Mishra, S. Chaudhury, M. Sarkar, Sidharth Manohar, A. Soin","doi":"10.1109/ISCAS.2018.8351049","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351049","url":null,"abstract":"Vascular region segmentation in ultrasound images is necessary for applications like automatic registration, and surgical navigation. In this paper, a pipelined network comprising of a convolutional neural network (CNN) followed by unsupervised clustering is proposed to perform vessel segmentation in liver ultrasound images. The work is motivated by the tremendous success of CNNs in object detection and localization. CNN here is trained to localize vascular regions, which are subsequently segmented by the clustering. The proposed network results in 99.14% pixel accuracy and 69.62% mean region intersection over union on 132 images. These values are better than some existing methods.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78992191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351696
S. Menzel, A. Siemon, A. Ascoli, R. Tetzlaff
Developing highly accurate and predictive models of redox-based memristive devices is highly important to enable future memory and logic design. As the switching mechanism is not known in all details yet, accurate device modeling is quite challenging. Here, we introduce six evaluation criteria for modeling filamentary switching devices based on the valence change mechanism, which is a subclass of redox-based memristive devices. The criteria include the plausibility of the simulated I-V and I-t characteristics, the nonlinearity of the switching kinetics, the feasibility of predicting complementary resistive switching correctly, the possibility of programming different resistance states, the state-dependence of the resistive switching, and the occurrence of a fading memory behavior. Four different models that have been proposed in literature are analyzed with respect to these criteria. These models are Kvatinsky's VTEAM model, the Stanford RRAM model, Strachan's TaOx memristor model and a nonlinear physics-based model proposed by our group.
{"title":"Requirements and Challenges for Modelling Redox-based Memristive Devices","authors":"S. Menzel, A. Siemon, A. Ascoli, R. Tetzlaff","doi":"10.1109/ISCAS.2018.8351696","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351696","url":null,"abstract":"Developing highly accurate and predictive models of redox-based memristive devices is highly important to enable future memory and logic design. As the switching mechanism is not known in all details yet, accurate device modeling is quite challenging. Here, we introduce six evaluation criteria for modeling filamentary switching devices based on the valence change mechanism, which is a subclass of redox-based memristive devices. The criteria include the plausibility of the simulated I-V and I-t characteristics, the nonlinearity of the switching kinetics, the feasibility of predicting complementary resistive switching correctly, the possibility of programming different resistance states, the state-dependence of the resistive switching, and the occurrence of a fading memory behavior. Four different models that have been proposed in literature are analyzed with respect to these criteria. These models are Kvatinsky's VTEAM model, the Stanford RRAM model, Strachan's TaOx memristor model and a nonlinear physics-based model proposed by our group.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"34 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77506233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351124
Mahmoud A. A. Ibrahim, Nikita Mirchandani, Nasim Shafiee, M. Onabajo, A. Shrivastava
This paper studies the effects of DC-DC switching converters on RF and analog baseband circuits. Simulations of a low-noise amplifier, mixer, and lowpass filter have shown that the impact of switching supply noise can be kept to small levels by design. For the case of loads with frequency conversion, a boost converter design technique to shift the switching frequency of the converter out of the band of interest is proposed.
{"title":"Study of Performance Impact from Powering RF Receiver Front-End Circuits with a DC-DC Converter","authors":"Mahmoud A. A. Ibrahim, Nikita Mirchandani, Nasim Shafiee, M. Onabajo, A. Shrivastava","doi":"10.1109/ISCAS.2018.8351124","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351124","url":null,"abstract":"This paper studies the effects of DC-DC switching converters on RF and analog baseband circuits. Simulations of a low-noise amplifier, mixer, and lowpass filter have shown that the impact of switching supply noise can be kept to small levels by design. For the case of loads with frequency conversion, a boost converter design technique to shift the switching frequency of the converter out of the band of interest is proposed.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"15 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77671973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351818
Tanuja Shanmukhappa, I. W. Ho, C. Tse, Xingtang Wu, Hai-rong Dong
In this paper, we propose a novel method called supernode graph structure representation to model the public transport network structure of the London city. Supernode is a set of geographically closely associated nodes. Using the supernode graph structure, the bus transport and the metro transport network structures are analyzed by treating them as independent mono-layer or multi-layer network structures. A method of spatial amalgamation is proposed to integrate the two transport layers. A set of most influential nodes in the network is identified by assigning node weight to each node with respect to both mono-layer and multi-layer analysis. The behavior of these influential nodes is better characterized by categorizing them as either emitter, absorber or neutral zones.
{"title":"Multi-layer Public Transport Network Analysis","authors":"Tanuja Shanmukhappa, I. W. Ho, C. Tse, Xingtang Wu, Hai-rong Dong","doi":"10.1109/ISCAS.2018.8351818","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351818","url":null,"abstract":"In this paper, we propose a novel method called supernode graph structure representation to model the public transport network structure of the London city. Supernode is a set of geographically closely associated nodes. Using the supernode graph structure, the bus transport and the metro transport network structures are analyzed by treating them as independent mono-layer or multi-layer network structures. A method of spatial amalgamation is proposed to integrate the two transport layers. A set of most influential nodes in the network is identified by assigning node weight to each node with respect to both mono-layer and multi-layer analysis. The behavior of these influential nodes is better characterized by categorizing them as either emitter, absorber or neutral zones.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"3 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86979754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351693
Benjamin Lac, A. Canteaut, J. Fournier, Renaud Sirdey
A growing number of connected objects, with their high performance and low-resources constraints, are embedding lightweight ciphers for protecting the confidentiality of the data they manipulate or store. Since those objects are easily accessible, they are prone to a whole range of physical attacks, one of which are fault attacks against which countermeasures are usually expensive to implement, especially on off-the-shelf devices. For such devices, we propose a new generic software countermeasure, using SIMD instructions available in almost any off-the-shelf devices, to thwart most fault attacks while preserving the performances of the targeted cipher.
{"title":"Thwarting Fault Attacks against Lightweight Cryptography using SIMD Instructions","authors":"Benjamin Lac, A. Canteaut, J. Fournier, Renaud Sirdey","doi":"10.1109/ISCAS.2018.8351693","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351693","url":null,"abstract":"A growing number of connected objects, with their high performance and low-resources constraints, are embedding lightweight ciphers for protecting the confidentiality of the data they manipulate or store. Since those objects are easily accessible, they are prone to a whole range of physical attacks, one of which are fault attacks against which countermeasures are usually expensive to implement, especially on off-the-shelf devices. For such devices, we propose a new generic software countermeasure, using SIMD instructions available in almost any off-the-shelf devices, to thwart most fault attacks while preserving the performances of the targeted cipher.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"38 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87181324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351177
Juhyoung Lee, Changhyeon Kim, Sungpill Choi, Dongjoo Shin, Sanghoon Kang, H. Yoo
A real-time global matching optical flow estimation (OFE) processor is proposed for action recognition in mobile devices. The global OFE requires a large number of external memory accesses (EMAs) and matrix computations, thus it is incompatible on mobile devices with real-time constraints. For real-time OFE on mobile devices, this paper proposes two key features, both of which to reduce the required memory bandwidth and a number of computations: 1) Tile-based hierarchical OFE enables intermediate data to be processed within 328 KB on-chip memory without external memory access. 2) Background skipping eliminates redundant matrix computation for zero optical flow region. Therefore, the proposed features reduce external memory bandwidth and computation by 99.7 % and 50.7 %, respectively. The proposed 4 mm2 OFE processor is implemented in 65 nm CMOS technology, and it achieves real-time OFE of 46.1 frames-per-second (fps) throughput for an image resolution of QVGA (320×240) and the resulting optical flow can be successfully used for action recognition.
{"title":"A 46.1 fps Global Matching Optical Flow Estimation Processor for Action Recognition in Mobile Devices","authors":"Juhyoung Lee, Changhyeon Kim, Sungpill Choi, Dongjoo Shin, Sanghoon Kang, H. Yoo","doi":"10.1109/ISCAS.2018.8351177","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351177","url":null,"abstract":"A real-time global matching optical flow estimation (OFE) processor is proposed for action recognition in mobile devices. The global OFE requires a large number of external memory accesses (EMAs) and matrix computations, thus it is incompatible on mobile devices with real-time constraints. For real-time OFE on mobile devices, this paper proposes two key features, both of which to reduce the required memory bandwidth and a number of computations: 1) Tile-based hierarchical OFE enables intermediate data to be processed within 328 KB on-chip memory without external memory access. 2) Background skipping eliminates redundant matrix computation for zero optical flow region. Therefore, the proposed features reduce external memory bandwidth and computation by 99.7 % and 50.7 %, respectively. The proposed 4 mm2 OFE processor is implemented in 65 nm CMOS technology, and it achieves real-time OFE of 46.1 frames-per-second (fps) throughput for an image resolution of QVGA (320×240) and the resulting optical flow can be successfully used for action recognition.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"30 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87188824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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