Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351022
Scott Lerner, Vasil Pano, B. Taskin
Network-on-chip (NoC) routers have a non-uniform utilization based on the number of links, location, and the workload running. Uneven utilization can lead to reliability issues, namely Negative Bias Temperature Instability (NBTI), that results in a reduced lifetime for gates. To address this, a physical design-based solution using workload signatures and cell sizing is proposed to improve the lifetime of NoCs. Using real workloads in conjunction with logic simulation and physical design, this paper analyzes the utilization of each port of NoC routers and, based on a desired lifetime, resizes the physical design. Results using SPLASH2 benchmarks show that the NoC router lifetime can be increased by 3.4× over the default sized router with an average increase of 5.58% and 5.27% for area and power, respectively.
{"title":"NoC Router Lifetime Improvement using Per-Port Router Utilization","authors":"Scott Lerner, Vasil Pano, B. Taskin","doi":"10.1109/ISCAS.2018.8351022","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351022","url":null,"abstract":"Network-on-chip (NoC) routers have a non-uniform utilization based on the number of links, location, and the workload running. Uneven utilization can lead to reliability issues, namely Negative Bias Temperature Instability (NBTI), that results in a reduced lifetime for gates. To address this, a physical design-based solution using workload signatures and cell sizing is proposed to improve the lifetime of NoCs. Using real workloads in conjunction with logic simulation and physical design, this paper analyzes the utilization of each port of NoC routers and, based on a desired lifetime, resizes the physical design. Results using SPLASH2 benchmarks show that the NoC router lifetime can be increased by 3.4× over the default sized router with an average increase of 5.58% and 5.27% for area and power, respectively.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"6 4 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76717293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351737
Lukasz Farian, J. A. Leñero-Bardallo, P. Häfliger
This demo shows a first prototype two-axis miniaturized spiking sun sensor. The device is composed of spiking pixels, and uses a novel Time-to-First-n-Spikes with time-out readout mode to reduce bandwidth consumption and post-processing computation. Due to on-chip processing, and compressing the angle information, the sensor produces much less data and is much faster than digital sensors. Its response latency is 88 μW, and average power consumption is 6.3 μW. An integrated circuit with core electronics was fabricated in the AMS 0.35 μm CMOS image sensor process, and was integrated inside a very small QFN64 package with micro-optics on top.
{"title":"Live Demonstration: A Miniaturized Two-Axis Low Latency and Low-Power Sun Sensor for Attitude Determination of Sounding Rockets","authors":"Lukasz Farian, J. A. Leñero-Bardallo, P. Häfliger","doi":"10.1109/ISCAS.2018.8351737","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351737","url":null,"abstract":"This demo shows a first prototype two-axis miniaturized spiking sun sensor. The device is composed of spiking pixels, and uses a novel Time-to-First-n-Spikes with time-out readout mode to reduce bandwidth consumption and post-processing computation. Due to on-chip processing, and compressing the angle information, the sensor produces much less data and is much faster than digital sensors. Its response latency is 88 μW, and average power consumption is 6.3 μW. An integrated circuit with core electronics was fabricated in the AMS 0.35 μm CMOS image sensor process, and was integrated inside a very small QFN64 package with micro-optics on top.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"107 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77017255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351493
Guanxue Yang, L. Wang, X. Wang
Time-delayed interactions are of vital importance in analysis and control of real networked systems. As for the limited noisy observations, data-driven modeling of these complex time-delayed systems is a central and challenging topic in numerous fields of science and engineering. Due to nonuniform lags usually embedded in the real-world systems, the inclusion of all lagged components would result in the false causal analysis. In this paper, based on data-fusion strategy, we put forward a novel approach for identifying nonlinear continuous time-delayed dynamical systems with nonuniform lags, termed Feature Selection Nonlinear Conditional Granger Causality (FSNCGC). In detail, rather than treating all the lagged components equally, we present a feature selection method based on information theory to select the candidate lagged components of driving variables, which minimizes the criterion of the mean conditional mutual information between unselected lagged components and target variable. Moreover, for each target variable, we just consider the specific selected lagged components for nonlinear conditional Granger causal analysis with F-test judgement. Finally, we apply our proposed method to a canonical nonlinear continuous time-delayed dynamical system. All of the results demonstrate that our proposed method performs well and provides a viable perspective for time-delayed network reconstruction.
{"title":"Time-delayed Network Reconstruction based on Nonlinear Continuous Dynamical Systems","authors":"Guanxue Yang, L. Wang, X. Wang","doi":"10.1109/ISCAS.2018.8351493","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351493","url":null,"abstract":"Time-delayed interactions are of vital importance in analysis and control of real networked systems. As for the limited noisy observations, data-driven modeling of these complex time-delayed systems is a central and challenging topic in numerous fields of science and engineering. Due to nonuniform lags usually embedded in the real-world systems, the inclusion of all lagged components would result in the false causal analysis. In this paper, based on data-fusion strategy, we put forward a novel approach for identifying nonlinear continuous time-delayed dynamical systems with nonuniform lags, termed Feature Selection Nonlinear Conditional Granger Causality (FSNCGC). In detail, rather than treating all the lagged components equally, we present a feature selection method based on information theory to select the candidate lagged components of driving variables, which minimizes the criterion of the mean conditional mutual information between unselected lagged components and target variable. Moreover, for each target variable, we just consider the specific selected lagged components for nonlinear conditional Granger causal analysis with F-test judgement. Finally, we apply our proposed method to a canonical nonlinear continuous time-delayed dynamical system. All of the results demonstrate that our proposed method performs well and provides a viable perspective for time-delayed network reconstruction.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"182 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77096043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351315
Daniel García-Lesta, V. Brea, Paula López, D. Cabello
The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.
{"title":"Impact of Analog Memories Non-Idealities on the Performance of Foreground Detection Algorithms","authors":"Daniel García-Lesta, V. Brea, Paula López, D. Cabello","doi":"10.1109/ISCAS.2018.8351315","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351315","url":null,"abstract":"The high number of memory accesses in background subtraction algorithms constraints the choice of the memory topology of an analog implementation of a hardware-oriented version of the well-known PBAS algorithm (HO-PBAS). As the first step towards the implementation of a CMOS vision chip with per-pixel processing to run the HO-PBAS, this work assesses the impact of the circuit non-idealities of the three main analog memory topologies into the segmentation result on the CDNET database.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"27 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80926824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351752
Alessandro Truppi, C. Samori, A. Lacaita, S. Levantino, M. Ronchi, M. Sosio
This paper discusses the impact of CMOS scaling in the design and performance of switched-capacitor power amplifiers operating in the sub-GHz bands for Internet-of-Things applications. While the peak drain efficiency is found to improve by about 10% when the amplifier is scaled down from a 65-nm standard CMOS to a 28-nm fully-depleted SOI CMOS process, the average efficiency instead slightly degrades. Moreover, it is theoretically demonstrated that the power density (peak-power over area-occupation) is a function of the supply voltage and the dielectric constant of the switched capacitor insulator, and it is about 13% higher in the 65-nm CMOS node.
{"title":"Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers","authors":"Alessandro Truppi, C. Samori, A. Lacaita, S. Levantino, M. Ronchi, M. Sosio","doi":"10.1109/ISCAS.2018.8351752","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351752","url":null,"abstract":"This paper discusses the impact of CMOS scaling in the design and performance of switched-capacitor power amplifiers operating in the sub-GHz bands for Internet-of-Things applications. While the peak drain efficiency is found to improve by about 10% when the amplifier is scaled down from a 65-nm standard CMOS to a 28-nm fully-depleted SOI CMOS process, the average efficiency instead slightly degrades. Moreover, it is theoretically demonstrated that the power density (peak-power over area-occupation) is a function of the supply voltage and the dielectric constant of the switched capacitor insulator, and it is about 13% higher in the 65-nm CMOS node.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"58 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78363050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8350904
Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren
A split-based background calibration technique for pipelined-ADC is proposed in this brief to handle both capacitors' mismatches and non-linearity of residue amplifiers in multiple pipeline stages. Some concepts and approaches of machine learning, say multilayer perceptron and backpropagation algorithm, are introduced to deal with the problems appearing in modeling and solving the nonlinear calibration filter. Computer simulations demonstrate an exaltation of both SNDR and SFDR for more than 50dB in a 15-bit 7-stages pipelined-ADC with non-ideal first three stages.
{"title":"Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC","authors":"Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren","doi":"10.1109/ISCAS.2018.8350904","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8350904","url":null,"abstract":"A split-based background calibration technique for pipelined-ADC is proposed in this brief to handle both capacitors' mismatches and non-linearity of residue amplifiers in multiple pipeline stages. Some concepts and approaches of machine learning, say multilayer perceptron and backpropagation algorithm, are introduced to deal with the problems appearing in modeling and solving the nonlinear calibration filter. Computer simulations demonstrate an exaltation of both SNDR and SFDR for more than 50dB in a 15-bit 7-stages pipelined-ADC with non-ideal first three stages.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72834082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351393
M. Kawamoto, Ken Okayama, T. Okuma, Norihiko Kato, T. Kurata
The present paper addresses the problem of analyzing the work of forklift trucks. To solve the problem, a forklift truck working model based on a state transition model is constructed using human activity sensing data, where the key point is using forklift truck operating data to determine human intention. The novel contribution of the model is its use of data that express the intention of the forklift truck operator to categorize the work of the forklift truck. By using a graph model, the proposed method can be extended to analyzing the human characteristics of forklift truck work. With this technique, some features of the graph model can be used to distinguish the skill level of the forklift truck operator.
{"title":"Work Analysis Using Human Operating Data Based on a State Transition Model","authors":"M. Kawamoto, Ken Okayama, T. Okuma, Norihiko Kato, T. Kurata","doi":"10.1109/ISCAS.2018.8351393","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351393","url":null,"abstract":"The present paper addresses the problem of analyzing the work of forklift trucks. To solve the problem, a forklift truck working model based on a state transition model is constructed using human activity sensing data, where the key point is using forklift truck operating data to determine human intention. The novel contribution of the model is its use of data that express the intention of the forklift truck operator to categorize the work of the forklift truck. By using a graph model, the proposed method can be extended to analyzing the human characteristics of forklift truck work. With this technique, some features of the graph model can be used to distinguish the skill level of the forklift truck operator.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72842537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351034
Yan Huang, Li Song, Rong Xie, Zhengyi Luo, Xiangwen Wang
As an open-source and computationally efficient High Efficiency Video Coding (HEVC) encoder, x265 has been gaining increasing popularity in video applications. x265 provides numerous encoding parameters in view of flexibility. However, proper and efficient setting of parameters often becomes a great challenge in practice. In this paper, we deeply investigate the influence of x265 parameters based on the Slow preset and pick out important parameters in terms of efficiency and complexity. Then a Markov Chain Monte Carlo (MCMC) based algorithm is proposed for efficient parameter adaptation at the target encoding time. This paper shows that carefully selected low-complexity encoding configurations can achieve the coding efficiency comparable to that of high-complexity ones. Specifically, average 26.72% encoding time reduction can be achieved while maintaining similar Rate Distortion (RD) performance to x265 presets using the proposed algorithm.
{"title":"An MCMC based Efficient Parameter Selection Model for x265 Encoder","authors":"Yan Huang, Li Song, Rong Xie, Zhengyi Luo, Xiangwen Wang","doi":"10.1109/ISCAS.2018.8351034","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351034","url":null,"abstract":"As an open-source and computationally efficient High Efficiency Video Coding (HEVC) encoder, x265 has been gaining increasing popularity in video applications. x265 provides numerous encoding parameters in view of flexibility. However, proper and efficient setting of parameters often becomes a great challenge in practice. In this paper, we deeply investigate the influence of x265 parameters based on the Slow preset and pick out important parameters in terms of efficiency and complexity. Then a Markov Chain Monte Carlo (MCMC) based algorithm is proposed for efficient parameter adaptation at the target encoding time. This paper shows that carefully selected low-complexity encoding configurations can achieve the coding efficiency comparable to that of high-complexity ones. Specifically, average 26.72% encoding time reduction can be achieved while maintaining similar Rate Distortion (RD) performance to x265 presets using the proposed algorithm.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"17 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81253196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, an automated task partition method for multi-core system is proposed. To explore the full parallelism of an application written in sequential languages such as C/C++, we first present a coarse-grain intermediate representation called Function-ANd-Statement (FANS) which takes function call structure as well as statement structure into account. Based on the FANS intermediate representation, we propose a node fusion technique called Stratify And Grain-Controlled Fusion (SAGCF) to partition the whole application into many subtasks with the goal of maximizing parallelism in space and time dimensions as well as minimizing communication. All of these proposed techniques are implemented in an open source Automatic Task Partition Framework (ATPF). Finally, the feasibility of the proposed method is demonstrated by several cases.
{"title":"An Automatic Task Partition Method for Multi-core System","authors":"Ming-e Jing, Yujie Huang, Yibo Fan, X. Xue, Xiaoyang Zeng, Zhiyi Yu","doi":"10.1109/ISCAS.2018.8351528","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351528","url":null,"abstract":"In this paper, an automated task partition method for multi-core system is proposed. To explore the full parallelism of an application written in sequential languages such as C/C++, we first present a coarse-grain intermediate representation called Function-ANd-Statement (FANS) which takes function call structure as well as statement structure into account. Based on the FANS intermediate representation, we propose a node fusion technique called Stratify And Grain-Controlled Fusion (SAGCF) to partition the whole application into many subtasks with the goal of maximizing parallelism in space and time dimensions as well as minimizing communication. All of these proposed techniques are implemented in an open source Automatic Task Partition Framework (ATPF). Finally, the feasibility of the proposed method is demonstrated by several cases.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"1 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75977343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351731
P. Beerel, Massoud Pedram
The rise of machine learning (ML) has introduced many opportunities for computer-aided-design, VLSI design, and their intersection. Related to computer-aided design, we review several classical CAD algorithms which can benefit from ML, outline the key challenges, and discuss promising approaches. In particular, because some of the existing ML accelerators have used asynchronous design, we review the state-of-the-art in asynchronous CAD support, and identify opportunities for ML within these flows.
{"title":"Opportunities for Machine Learning in Electronic Design Automation","authors":"P. Beerel, Massoud Pedram","doi":"10.1109/ISCAS.2018.8351731","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351731","url":null,"abstract":"The rise of machine learning (ML) has introduced many opportunities for computer-aided-design, VLSI design, and their intersection. Related to computer-aided design, we review several classical CAD algorithms which can benefit from ML, outline the key challenges, and discuss promising approaches. In particular, because some of the existing ML accelerators have used asynchronous design, we review the state-of-the-art in asynchronous CAD support, and identify opportunities for ML within these flows.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"28 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87638725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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