Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351751
W. Arter, A. Osojnik, C. Cartis, Godwin Madho, Chris Jones, S. Tobias
The problem of parameter fitting for nonlinear oscillator models to noisy time series is addressed using a combination of Ensemble Kalman Filter and optimisation techniques. Encouraging preliminary results for acceptable sampling rates and noise levels are presented. Application to the understanding and control of tokamak nuclear reactor operation is discussed.
{"title":"Data assimilation approach to analysing systems of ordinary differential equations","authors":"W. Arter, A. Osojnik, C. Cartis, Godwin Madho, Chris Jones, S. Tobias","doi":"10.1109/ISCAS.2018.8351751","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351751","url":null,"abstract":"The problem of parameter fitting for nonlinear oscillator models to noisy time series is addressed using a combination of Ensemble Kalman Filter and optimisation techniques. Encouraging preliminary results for acceptable sampling rates and noise levels are presented. Application to the understanding and control of tokamak nuclear reactor operation is discussed.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"110 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87712240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8350902
Wei Zhou, W. Goh, J. Cheong, Yuan Gao
This paper presents a new RC relaxation oscillator for biomedical sensor interface circuit. A novel switch-capacitor based RC charging/discharging circuit is proposed to effectively improve the oscillator phase noise and power performance. The inverter-based comparator with replica biasing is employed and optimized to enhance the phase noise performance and to lower output dependence on the supply voltage variation. The oscillator's temperature insensitivity is also improved by resistor temperature compensation. The prototype RC relaxation oscillator circuit is designed in a commercial 65nm CMOS process. The post-layout simulation results showed 3.12 MHz output frequency, −112dBc/Hz phase noise at 100 kHz offset, and 16.6 μW power consumption under 1 V supply voltage. The frequency variation is ±0.294%/V for supply within 1 V to 1.6 V, and 11.31 ppm/°C for temperature across −40°C to 100°C. The overall circuit performance is compared favorably to the state-of-art designs, with an outstanding Figure of Merit (FOM) of 160.03 dBc/Hz at 100 kHz.
{"title":"A 16.6 μW 3.12 MHz RC Relaxation Oscillator with 160.3 dBc/Hz FOM","authors":"Wei Zhou, W. Goh, J. Cheong, Yuan Gao","doi":"10.1109/ISCAS.2018.8350902","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8350902","url":null,"abstract":"This paper presents a new RC relaxation oscillator for biomedical sensor interface circuit. A novel switch-capacitor based RC charging/discharging circuit is proposed to effectively improve the oscillator phase noise and power performance. The inverter-based comparator with replica biasing is employed and optimized to enhance the phase noise performance and to lower output dependence on the supply voltage variation. The oscillator's temperature insensitivity is also improved by resistor temperature compensation. The prototype RC relaxation oscillator circuit is designed in a commercial 65nm CMOS process. The post-layout simulation results showed 3.12 MHz output frequency, −112dBc/Hz phase noise at 100 kHz offset, and 16.6 μW power consumption under 1 V supply voltage. The frequency variation is ±0.294%/V for supply within 1 V to 1.6 V, and 11.31 ppm/°C for temperature across −40°C to 100°C. The overall circuit performance is compared favorably to the state-of-art designs, with an outstanding Figure of Merit (FOM) of 160.03 dBc/Hz at 100 kHz.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"13 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87822153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8350906
A. Ciprut, E. Friedman
Crossbar arrays based on non-volatile resistive devices are planned for future memory systems due to the scalability and performance as compared to conventional charge based memory systems. To enhance the feasibility of these resistive memory systems, the energy consumption needs to be reduced. The write operation of a resistive memory based on a one-selector-one-resistor crossbar array consumes significant energy. The energy consumed by a crossbar array is dependent on the device and interconnect characteristics as well as the bias scheme. While the device and circuit parameters are the same for a specific application, the bias scheme of an array can be tuned to improve the energy efficiency. In this paper, an intelligent write scheme is proposed to provide a hybrid bias scheme. The proposed system adaptively sets the bias schemes to enhance energy efficiency. The most energy efficient bias scheme depends upon several parameters such as the size of the array, nonlinearity factor, and number of selected cells. For a specific array size and device characteristics, a power delivery system is described that sets the bias voltages based on the number of selected cells. Energy improvements of more than 2× are demonstrated with this hybrid bias scheme.
{"title":"Hybrid Write Bias Scheme for Non-Volatile Resistive Crossbar Arrays","authors":"A. Ciprut, E. Friedman","doi":"10.1109/ISCAS.2018.8350906","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8350906","url":null,"abstract":"Crossbar arrays based on non-volatile resistive devices are planned for future memory systems due to the scalability and performance as compared to conventional charge based memory systems. To enhance the feasibility of these resistive memory systems, the energy consumption needs to be reduced. The write operation of a resistive memory based on a one-selector-one-resistor crossbar array consumes significant energy. The energy consumed by a crossbar array is dependent on the device and interconnect characteristics as well as the bias scheme. While the device and circuit parameters are the same for a specific application, the bias scheme of an array can be tuned to improve the energy efficiency. In this paper, an intelligent write scheme is proposed to provide a hybrid bias scheme. The proposed system adaptively sets the bias schemes to enhance energy efficiency. The most energy efficient bias scheme depends upon several parameters such as the size of the array, nonlinearity factor, and number of selected cells. For a specific array size and device characteristics, a power delivery system is described that sets the bias voltages based on the number of selected cells. Energy improvements of more than 2× are demonstrated with this hybrid bias scheme.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2020 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87832497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351645
Mohammed E. Elbtity, A. Radwan
Area and power consumption are the main challenges in Network on Chip (NoC). Indeed, First Input First Output (FIFO) memory is the key element in NoC. Increasing the FIFO depth, produces an increas in the performance of NoC but at the cost of area and power consumption. This paper proposes a new hybrid CMOS-Memristor based FIFO architecture that consumes low power and has a small size compared to the conventional CMOS-based FIFOs. The predicted area is approximately equal to the half of that wasted in conventional FIFOs. The implementation of FIFO controller module is implemented using HDL. Moreover, the functionality test and the simulation results of the proposed architecture are presented. Simulation is done using ISF Xilinix and Cadence tools.
{"title":"Small Area and Low Power Hybrid CMOS-Memristor Based FIFO for NoC","authors":"Mohammed E. Elbtity, A. Radwan","doi":"10.1109/ISCAS.2018.8351645","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351645","url":null,"abstract":"Area and power consumption are the main challenges in Network on Chip (NoC). Indeed, First Input First Output (FIFO) memory is the key element in NoC. Increasing the FIFO depth, produces an increas in the performance of NoC but at the cost of area and power consumption. This paper proposes a new hybrid CMOS-Memristor based FIFO architecture that consumes low power and has a small size compared to the conventional CMOS-based FIFOs. The predicted area is approximately equal to the half of that wasted in conventional FIFOs. The implementation of FIFO controller module is implemented using HDL. Moreover, the functionality test and the simulation results of the proposed architecture are presented. Simulation is done using ISF Xilinix and Cadence tools.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"19 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87915889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351806
T. Ge, Zhou Jia, J. Chang
Flexible Hybrid Electronics (FHE), heterogeneous electronics embodying both conventional silicon electronics and printed electronics, is an emerging technology with huge market potential as it is advantageous compared to conventional silicon electronics and the emerging Printed Electronics — FHE features better mechanical flexibility/conformability and lower cost compared to conventional silicon electronics, and higher performance compared to Printed Electronics. In this paper, a comprehensive literature view on FHE is provided, including the state-of-the-art FHE development, FHE supply chains, and design challenges.
{"title":"Flexible Hybrid Electronics: Review and Challenges","authors":"T. Ge, Zhou Jia, J. Chang","doi":"10.1109/ISCAS.2018.8351806","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351806","url":null,"abstract":"Flexible Hybrid Electronics (FHE), heterogeneous electronics embodying both conventional silicon electronics and printed electronics, is an emerging technology with huge market potential as it is advantageous compared to conventional silicon electronics and the emerging Printed Electronics — FHE features better mechanical flexibility/conformability and lower cost compared to conventional silicon electronics, and higher performance compared to Printed Electronics. In this paper, a comprehensive literature view on FHE is provided, including the state-of-the-art FHE development, FHE supply chains, and design challenges.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"41 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87968081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 12-bit 2.5GHz digital-to-time converter (DTC) for high resolution and high linearity applications is presented in this paper. The DTC is segmented into a 4-bit coarse stage and an 8-bit fine stage. The proposed fine stage utilizes parasitic-insensitive charge-based (PICB) phase interpolator (PI) with significant improvement in linearity. The PICB PI outputs 50% duty cycle differential clock and its performance is insensitive to parasitic effect. The DTC is designed in 40nm CMOS technology and consumes 7.1mW with a 1.1-V supply voltage. Simulation results show that the peak integral nonlinearity and differential nonlinearity are 0.37ps and 0.085ps, respectively.
{"title":"A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator","authors":"Haoyun Jiang, Zexue Liu, Xiucheng Hao, Zherui Zhang, Zhengkun Shen, Heyi Li, Junhua Liu, H. Liao","doi":"10.1109/ISCAS.2018.8351655","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351655","url":null,"abstract":"A 12-bit 2.5GHz digital-to-time converter (DTC) for high resolution and high linearity applications is presented in this paper. The DTC is segmented into a 4-bit coarse stage and an 8-bit fine stage. The proposed fine stage utilizes parasitic-insensitive charge-based (PICB) phase interpolator (PI) with significant improvement in linearity. The PICB PI outputs 50% duty cycle differential clock and its performance is insensitive to parasitic effect. The DTC is designed in 40nm CMOS technology and consumes 7.1mW with a 1.1-V supply voltage. Simulation results show that the peak integral nonlinearity and differential nonlinearity are 0.37ps and 0.085ps, respectively.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"21 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88121283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351015
M. Lodi, A. Shilnikov, M. Storace
This paper discusses practical approaches for designing reduced synthetic circuits of central pattern generators (CPGs) for quadruped locomotion using our newly developed bifurcation toolkit. Specifically, two CPGs containing only four elements (cells) are proposed that can reliably generate natural gaits of typical quadrupeds more effectively than large dedicated complex networks do. In addition, we analyze an enhanced locomotion system that incorporates a neuromechanical model for each leg and includes mechanisms of sensory feedback. We demonstrate how the proposed CPGs produce the desired gaits, which remain robust with respect to external perturbations.
{"title":"Design of Minimal Synthetic Circuits with Sensory Feedback for Quadruped Locomotion","authors":"M. Lodi, A. Shilnikov, M. Storace","doi":"10.1109/ISCAS.2018.8351015","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351015","url":null,"abstract":"This paper discusses practical approaches for designing reduced synthetic circuits of central pattern generators (CPGs) for quadruped locomotion using our newly developed bifurcation toolkit. Specifically, two CPGs containing only four elements (cells) are proposed that can reliably generate natural gaits of typical quadrupeds more effectively than large dedicated complex networks do. In addition, we analyze an enhanced locomotion system that incorporates a neuromechanical model for each leg and includes mechanisms of sensory feedback. We demonstrate how the proposed CPGs produce the desired gaits, which remain robust with respect to external perturbations.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"2014 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88248584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8351397
Tiankai Su, Atif Yasin, Cunxi Yu, M. Ciesielski
The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2m) using GF(2) models of its logic gates. We define a forward variable order “FO >” and the rules of forward reduction that enable verification, bug detection, and automatic bug correction in the circuit. By analyzing the remainder generated by forward reduction, the method can determine whether the circuit is buggy, and finds the location and the type of the bug. The experiments performed on Mastrovito and Montgomery multipliers show that our debugging method is independent of the location of the bug(s) and the debugging time is comparable to the time needed to verify the bug-free circuit.
{"title":"Computer Algebraic Approach to Verification and Debugging of Galois Field Multipliers","authors":"Tiankai Su, Atif Yasin, Cunxi Yu, M. Ciesielski","doi":"10.1109/ISCAS.2018.8351397","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351397","url":null,"abstract":"The paper presents a novel method to verify and debug gate-level arithmetic circuits implemented in Galois Field arithmetic. The method is based on forward reduction of the specification polynomials of the circuit in GF(2m) using GF(2) models of its logic gates. We define a forward variable order “FO >” and the rules of forward reduction that enable verification, bug detection, and automatic bug correction in the circuit. By analyzing the remainder generated by forward reduction, the method can determine whether the circuit is buggy, and finds the location and the type of the bug. The experiments performed on Mastrovito and Montgomery multipliers show that our debugging method is independent of the location of the bug(s) and the debugging time is comparable to the time needed to verify the bug-free circuit.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"17 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88381356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-05-27DOI: 10.1109/ISCAS.2018.8350980
Guijie Zhu, Songping Mai, Xian Tang, Chun Zhang, Zhihua Wang, Hong Chen
This paper presents a high-frequency pulse stimulation (HFPS) output stage of neuro-stimulator with extended average output current range and high power efficiency. The output stage features two parallel buck-boost converters without any filter capacitor at the output node. Compared with HFPS output stage with only one converter, the proposed circuit doubles the maximum average current by staggering the output of two converters. Compared with traditional voltage mode stimulation (VMS), HFPS improves the power efficiency by discharging the inductor current through the tissue load directly, rather than through a filter capacitor with constant voltage. Besides, the control circuit for the proposed HFPS is much simpler than that of traditional VMS converter, which reduces the current consumption significantly and thus improves the efficiency. Test results confirm that with staggered output of two parallel converters, the maximum average current is doubled. The maximum energy efficiency of the proposed HFPS is 76.4%.
{"title":"An Energy-Efficient High-Frequency Neuro-Stimulator with Parallel Pulse Generators, Staggered Output and Extended Average Current Range","authors":"Guijie Zhu, Songping Mai, Xian Tang, Chun Zhang, Zhihua Wang, Hong Chen","doi":"10.1109/ISCAS.2018.8350980","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8350980","url":null,"abstract":"This paper presents a high-frequency pulse stimulation (HFPS) output stage of neuro-stimulator with extended average output current range and high power efficiency. The output stage features two parallel buck-boost converters without any filter capacitor at the output node. Compared with HFPS output stage with only one converter, the proposed circuit doubles the maximum average current by staggering the output of two converters. Compared with traditional voltage mode stimulation (VMS), HFPS improves the power efficiency by discharging the inductor current through the tissue load directly, rather than through a filter capacitor with constant voltage. Besides, the control circuit for the proposed HFPS is much simpler than that of traditional VMS converter, which reduces the current consumption significantly and thus improves the efficiency. Test results confirm that with staggered output of two parallel converters, the maximum average current is doubled. The maximum energy efficiency of the proposed HFPS is 76.4%.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"144 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86203465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clock tree synthesis (CTS) is performed in a very late stage of design. Power estimation, therefore, can only be done without clock network in most design stages, which is not desirable given that clock network is usually the biggest power consumer. One may adopt an estimate of clock power, but its dynamic nature arising from clock gating brings a challenge in the estimation of clock power in a pre-CTS design. In this paper, we (1) estimate the clock tree components (clock gating cells (CGCs) and buffers as well as their wireloads) by using artificial neural networks (ANNs) and (2) use them while gating or ungating of each CGC is identified from a netlist cycle-by-cycle to estimate transient clock power consumption. Experiments with a few test circuits indicate that (1) the estimation of clock tree components causes the error of 13% on average, and (2) the estimated clock power waveform is very close to the actual waveform with average error of only 2%.
{"title":"Transient Clock Power Estimation of Pre-CTS Netlist","authors":"Yonghwi Kwon, Jinwook Jung, Inhak Han, Youngsoo Shin","doi":"10.1109/ISCAS.2018.8351430","DOIUrl":"https://doi.org/10.1109/ISCAS.2018.8351430","url":null,"abstract":"Clock tree synthesis (CTS) is performed in a very late stage of design. Power estimation, therefore, can only be done without clock network in most design stages, which is not desirable given that clock network is usually the biggest power consumer. One may adopt an estimate of clock power, but its dynamic nature arising from clock gating brings a challenge in the estimation of clock power in a pre-CTS design. In this paper, we (1) estimate the clock tree components (clock gating cells (CGCs) and buffers as well as their wireloads) by using artificial neural networks (ANNs) and (2) use them while gating or ungating of each CGC is identified from a netlist cycle-by-cycle to estimate transient clock power consumption. Experiments with a few test circuits indicate that (1) the estimation of clock tree components causes the error of 13% on average, and (2) the estimated clock power waveform is very close to the actual waveform with average error of only 2%.","PeriodicalId":6569,"journal":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","volume":"55 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2018-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89191570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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