Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6993169
N. Madhuri, S. Doradla, M. Kalavathi
Active Power Filters are developed for compensating the harmonics, reactive power simultaneously. The performance of shunt Active Power Filter depends on the two factors i.e., type of the controller and methods used to obtain the reference current. Generally, the type of controller used in most of the Active Power Filters is traditional PI controller or Fuzzy Logic Controller. Recently, Fault Tolerant Shunt Active Power Filter was proposed using PI controller with redundancy method to guarantee reliability of Active Power Filters. However in this study, we propose a Fault tolerant Shunt Active Power Filter using Fuzzy Logic Controller instead of PI controller to achieve better performance in terms of Total Harmonic Distortion. Simulation results are obtained using MATLAB/SIMULINK for Fuzzy based Fault tolerant Shunt Active Power Filter in presence of open / short circuit fault and shown better results in comparison with Fault Tolerant Shunt Active Filter using PI controller.
{"title":"Fuzzy based Fault Tolerant shunt Active Power Filter","authors":"N. Madhuri, S. Doradla, M. Kalavathi","doi":"10.1109/ICCICCT.2014.6993169","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6993169","url":null,"abstract":"Active Power Filters are developed for compensating the harmonics, reactive power simultaneously. The performance of shunt Active Power Filter depends on the two factors i.e., type of the controller and methods used to obtain the reference current. Generally, the type of controller used in most of the Active Power Filters is traditional PI controller or Fuzzy Logic Controller. Recently, Fault Tolerant Shunt Active Power Filter was proposed using PI controller with redundancy method to guarantee reliability of Active Power Filters. However in this study, we propose a Fault tolerant Shunt Active Power Filter using Fuzzy Logic Controller instead of PI controller to achieve better performance in terms of Total Harmonic Distortion. Simulation results are obtained using MATLAB/SIMULINK for Fuzzy based Fault tolerant Shunt Active Power Filter in presence of open / short circuit fault and shown better results in comparison with Fault Tolerant Shunt Active Filter using PI controller.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"379 1","pages":"1334-1337"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78799358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6993140
Payel Roy, Goutami Dey, S. Dutta, Sayan Chakraborty, N. Dey, R. Ray
With the growth of image processing applications, image segmentation has become an important part of image processing. The simplest method to segment an image is thresholding. Using the thresholding method, segmentation of an image is done by fixing all pixels whose intensity values are more than the threshold to a foreground value. The remaining pixels are set to a background value. Such technique can be used to obtain binary images from grayscale images. The conventional thresholding techniques use a global threshold for all pixels, whereas adaptive thresholding changes the threshold value dynamically over the image. This paper offers a comparative study on adaptive thresholding techniques to choose the accurate method for binarizing an image based on the contrast, texture, resolution etc. of an image.
{"title":"Adaptive thresholding: A comparative study","authors":"Payel Roy, Goutami Dey, S. Dutta, Sayan Chakraborty, N. Dey, R. Ray","doi":"10.1109/ICCICCT.2014.6993140","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6993140","url":null,"abstract":"With the growth of image processing applications, image segmentation has become an important part of image processing. The simplest method to segment an image is thresholding. Using the thresholding method, segmentation of an image is done by fixing all pixels whose intensity values are more than the threshold to a foreground value. The remaining pixels are set to a background value. Such technique can be used to obtain binary images from grayscale images. The conventional thresholding techniques use a global threshold for all pixels, whereas adaptive thresholding changes the threshold value dynamically over the image. This paper offers a comparative study on adaptive thresholding techniques to choose the accurate method for binarizing an image based on the contrast, texture, resolution etc. of an image.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"1 1","pages":"1182-1186"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89680457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6992944
Rahul Raveendranath, V. Rajamani, Anoop Babu, S. K. Datta
Smartphones are rising in popularity as well as becoming more sophisticated over recent years. This popularity coupled with the fact that smartphones contain a lot of private user data is causing a proportional rise in different malwares for the platform. In this paper we analyze and classify state-of-the-art malware techniques and their countermeasures. The paper also reports a novel method for malware development and novel attack techniques such as mobile botnets, usage pattern based attacks and repackaging attacks. The possible countermeasures are also proposed. Then a detailed analysis of one of the proposed novel malware methods is explained. Finally the paper concludes by summarizing the paper.
{"title":"Android malware attacks and countermeasures: Current and future directions","authors":"Rahul Raveendranath, V. Rajamani, Anoop Babu, S. K. Datta","doi":"10.1109/ICCICCT.2014.6992944","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992944","url":null,"abstract":"Smartphones are rising in popularity as well as becoming more sophisticated over recent years. This popularity coupled with the fact that smartphones contain a lot of private user data is causing a proportional rise in different malwares for the platform. In this paper we analyze and classify state-of-the-art malware techniques and their countermeasures. The paper also reports a novel method for malware development and novel attack techniques such as mobile botnets, usage pattern based attacks and repackaging attacks. The possible countermeasures are also proposed. Then a detailed analysis of one of the proposed novel malware methods is explained. Finally the paper concludes by summarizing the paper.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"23 1","pages":"137-143"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86342373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6993097
M. Praseetha, S. Deepa
Character segmentation is a significant phase in an Optical Character Recognition (OCR) system. In this stage of OCR, the image of sequence of characters is decomposed into sub-images of individual symbols. The recognition of characters depends on this phase so that any mistake in the segmentation leads to a complete failure of the OCR system. One of the main reasons for incorrect segmentation of characters is the presence of broken characters in the input document. Here an approach based on Active Contour Model is proposed to solve this problem.
{"title":"Segmentation in Malayalam OCR — Handling broken characters using active contour model","authors":"M. Praseetha, S. Deepa","doi":"10.1109/ICCICCT.2014.6993097","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6993097","url":null,"abstract":"Character segmentation is a significant phase in an Optical Character Recognition (OCR) system. In this stage of OCR, the image of sequence of characters is decomposed into sub-images of individual symbols. The recognition of characters depends on this phase so that any mistake in the segmentation leads to a complete failure of the OCR system. One of the main reasons for incorrect segmentation of characters is the presence of broken characters in the input document. Here an approach based on Active Contour Model is proposed to solve this problem.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"71 1","pages":"958-962"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86405958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6993049
D. Rewadkar, Suchita Y. Ghatage
Cloud computing is a revolutionary new approach to how computing services are produced and consumed. It is an abstraction of the concept of pooling resources and presenting them as virtual resources. Using cloud computing resources, data, computations, and services can be shared over scalable network of nodes; these nodes may represent the datacenters, end user computers and web services. On the same note cloud storage refers to storing the data on a remote storage located at other organization's infrastructure. The data storage is maintained and managed by the organization; the user will pay for the storage space which is used. Outsourcing data ultimately relinquishes the control of data from user and the fate of data is in control of the cloud server. As the data is stored on cloud server, the storage correctness of data is put on risk. The cloud server is managed by cloud service provider which is a different administrative entity, so ensuring the data integrity is of prime importance. This article studies the problems of ensuring data storage correctness and proposes an efficient and secure method to address these issues. A third party auditor is introduced securely, who will on behalf of users request will periodically verify the data integrity of the data stored on cloud server. There will not be any online burden on user and security of data will be maintained as the data will not be shared directly with the third party auditor. A homomorphic encryption scheme is used to encrypt the data which will be shared with the TPA. The results can be further extended to enable the third party auditor to do multiple auditing.
{"title":"Cloud storage system enabling secure privacy preserving third party audit","authors":"D. Rewadkar, Suchita Y. Ghatage","doi":"10.1109/ICCICCT.2014.6993049","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6993049","url":null,"abstract":"Cloud computing is a revolutionary new approach to how computing services are produced and consumed. It is an abstraction of the concept of pooling resources and presenting them as virtual resources. Using cloud computing resources, data, computations, and services can be shared over scalable network of nodes; these nodes may represent the datacenters, end user computers and web services. On the same note cloud storage refers to storing the data on a remote storage located at other organization's infrastructure. The data storage is maintained and managed by the organization; the user will pay for the storage space which is used. Outsourcing data ultimately relinquishes the control of data from user and the fate of data is in control of the cloud server. As the data is stored on cloud server, the storage correctness of data is put on risk. The cloud server is managed by cloud service provider which is a different administrative entity, so ensuring the data integrity is of prime importance. This article studies the problems of ensuring data storage correctness and proposes an efficient and secure method to address these issues. A third party auditor is introduced securely, who will on behalf of users request will periodically verify the data integrity of the data stored on cloud server. There will not be any online burden on user and security of data will be maintained as the data will not be shared directly with the third party auditor. A homomorphic encryption scheme is used to encrypt the data which will be shared with the TPA. The results can be further extended to enable the third party auditor to do multiple auditing.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"52 1","pages":"695-699"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79127852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6993006
T. George, Sumi P. Potty, Sneha Jose
Reliable detection and recognition of facial expression from still images in the unconstrained real world situations has many potential applications. Smile detection can be used in many applications include modeling systems for psychological studies on human emotional responses, expression recognition technologies, extending image search capabilities etc. This paper proposes an experimental study of smile detection in embedded environment using Raspberry Pi board, by extracting mouth and eye pair from images using Haar-cascade classifier and train these images using KNN matching algorithm. The relatively simple K- Nearest Neighbor is used because of its lazy learning efficiency. OpenCV- 2.3.1(Open Source Computer Vision) library is used as the imaging library. The experiments explored that the proposed approach has an accuracy of 66.6%.
{"title":"Smile detection from still images using KNN algorithm","authors":"T. George, Sumi P. Potty, Sneha Jose","doi":"10.1109/ICCICCT.2014.6993006","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6993006","url":null,"abstract":"Reliable detection and recognition of facial expression from still images in the unconstrained real world situations has many potential applications. Smile detection can be used in many applications include modeling systems for psychological studies on human emotional responses, expression recognition technologies, extending image search capabilities etc. This paper proposes an experimental study of smile detection in embedded environment using Raspberry Pi board, by extracting mouth and eye pair from images using Haar-cascade classifier and train these images using KNN matching algorithm. The relatively simple K- Nearest Neighbor is used because of its lazy learning efficiency. OpenCV- 2.3.1(Open Source Computer Vision) library is used as the imaging library. The experiments explored that the proposed approach has an accuracy of 66.6%.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"1 1","pages":"461-465"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76459096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6992973
Teena Susan Elias, P. Dhanusha
The paper describes the design of one-dimensional discrete cosine transform (DCT) which is widely used in image and video compression systems. The objective of this paper is to design an area efficient fully parallel distributed arithmetic (DA) architecture for one-dimensional DCT to be implemented on field programmable gate array (FPGA). DCT requires large amount of mathematical computations including multiplications and accumulations. The multipliers consume increased power and area; hence multipliers are completely discarded in the proposed design. Distributed arithmetic is a method of modification at bit stream for sum of product or vector dot product to hide the multiplications. DA is very much suitable for FPGA designs as it reduces the size of a multiply and accumulate hardware. The speed is increased in the proposed design with the fully parallel approach. In this work, existing DA architecture for 1D-DCT and the proposed area efficient fully parallel DA architecture for 1D-DCT are realized. The simulation is performed using Modelsim6.2b and synthesized with Xilinx IS E Simulator. The 1D-DCT can be extended to 2D-DCT by using row column decomposition technique.
本文介绍了在图像和视频压缩系统中广泛应用的一维离散余弦变换(DCT)的设计。本文的目的是设计一种在现场可编程门阵列(FPGA)上实现一维DCT的区域高效全并行分布式算法(DA)体系结构。DCT需要大量的数学计算，包括乘法和累加。乘数器消耗更多的功率和面积;因此，在提出的设计中，乘数完全被丢弃。分布式算法是一种在比特流上对乘积和或向量点积进行修改以隐藏乘法的方法。数据处理非常适合FPGA设计，因为它减少了乘法和累加硬件的尺寸。采用全并行方法，提高了设计的速度。在此工作中，实现了现有的3d - dct数据处理体系结构和提出的3d - dct区域高效全并行数据处理体系结构。采用Modelsim6.2b进行仿真，并用Xilinx is E Simulator进行合成。利用行列分解技术可以将一维dct扩展到二维dct。
{"title":"Area efficient fully parallel distributed arithmetic architecture for one-dimensional discrete cosine transform","authors":"Teena Susan Elias, P. Dhanusha","doi":"10.1109/ICCICCT.2014.6992973","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992973","url":null,"abstract":"The paper describes the design of one-dimensional discrete cosine transform (DCT) which is widely used in image and video compression systems. The objective of this paper is to design an area efficient fully parallel distributed arithmetic (DA) architecture for one-dimensional DCT to be implemented on field programmable gate array (FPGA). DCT requires large amount of mathematical computations including multiplications and accumulations. The multipliers consume increased power and area; hence multipliers are completely discarded in the proposed design. Distributed arithmetic is a method of modification at bit stream for sum of product or vector dot product to hide the multiplications. DA is very much suitable for FPGA designs as it reduces the size of a multiply and accumulate hardware. The speed is increased in the proposed design with the fully parallel approach. In this work, existing DA architecture for 1D-DCT and the proposed area efficient fully parallel DA architecture for 1D-DCT are realized. The simulation is performed using Modelsim6.2b and synthesized with Xilinx IS E Simulator. The 1D-DCT can be extended to 2D-DCT by using row column decomposition technique.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"29 1","pages":"294-299"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90665341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6992935
G. V. A. Kumar, T. Subbareddy, Bommepalli Madhava Reddy, N. Raju, V. Elamaran
This study work is basically aimed at designing and testing of hardware module to perform inversion operation of a matrix in a small time. Here, an approach is made for calculating 3×3 matrix inverse. There are many mathematical methods available for performing matrix inversion and out of them a suitable method, like Adjoint Matrix Method is selected by analysing the computational requirements. The mathematical method of calculating the inverse of matrix is then suitably converted into VHDL code. The code is then tested for simulation using a set of test matrices. After simulation is verified by checking the results of test inputs the code is tested for synthesizability. After the synthesizability is verified then it is finally tested for hardware verification by dumping into FPGA. Altera's DE1 board which consists a Cyclone-II series FPGA EP2C20F484C7 FPGA is used for this study. The test inputs can be fed in either by using on board GPIO or UI or S RAM. The outputs are taken the same way either by GPIO or UI or written to S RAM and are then to be verified by comparing with actual results.
{"title":"An approach to design a matrix inversion hardware module using FPGA","authors":"G. V. A. Kumar, T. Subbareddy, Bommepalli Madhava Reddy, N. Raju, V. Elamaran","doi":"10.1109/ICCICCT.2014.6992935","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992935","url":null,"abstract":"This study work is basically aimed at designing and testing of hardware module to perform inversion operation of a matrix in a small time. Here, an approach is made for calculating 3×3 matrix inverse. There are many mathematical methods available for performing matrix inversion and out of them a suitable method, like Adjoint Matrix Method is selected by analysing the computational requirements. The mathematical method of calculating the inverse of matrix is then suitably converted into VHDL code. The code is then tested for simulation using a set of test matrices. After simulation is verified by checking the results of test inputs the code is tested for synthesizability. After the synthesizability is verified then it is finally tested for hardware verification by dumping into FPGA. Altera's DE1 board which consists a Cyclone-II series FPGA EP2C20F484C7 FPGA is used for this study. The test inputs can be fed in either by using on board GPIO or UI or S RAM. The outputs are taken the same way either by GPIO or UI or written to S RAM and are then to be verified by comparing with actual results.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"91 1","pages":"87-90"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85874536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6992948
A. Parashar
Transmission Control Protocol is one of the key protocol of Transport Layer in TCP/IP Protocols suite. While IP transmits data between individual computers on the Internet, TCP transfers data between actual applications running on the system. TCP provides connection oriented and reliable data stream. TCP achieves this reliability by assigning a sequence number to each segment it transmits and requiring a acknowledgment (ACK) from the receiving end. If the ACK is not received within the time-out interval, the data is retransmitted. This research paper describes improved Transmission Control Protocol model which transfers data efficiently among its peer.
{"title":"Improved transmission control protocol model","authors":"A. Parashar","doi":"10.1109/ICCICCT.2014.6992948","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992948","url":null,"abstract":"Transmission Control Protocol is one of the key protocol of Transport Layer in TCP/IP Protocols suite. While IP transmits data between individual computers on the Internet, TCP transfers data between actual applications running on the system. TCP provides connection oriented and reliable data stream. TCP achieves this reliability by assigning a sequence number to each segment it transmits and requiring a acknowledgment (ACK) from the receiving end. If the ACK is not received within the time-out interval, the data is retransmitted. This research paper describes improved Transmission Control Protocol model which transfers data efficiently among its peer.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"28 1","pages":"161-164"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81350850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-07-10DOI: 10.1109/ICCICCT.2014.6992985
R. Saranya, C. Pradeep
Reconfigurable computing for DSP remains an active area of research as the need for integration with more traditional DSP technologies become apparent. Traditionally, most of the work in the field of reconfigurable computing was focused on fine-grained FPGA devices. Over the years, the focus was shifted from bit level granularity to a more coarse grained composition. In this paper, we present the synthesis of high-throughput and area efficient data path for reconfigurable Finite Impulse Response (FIR) filter. FIR filters have been and continue to be important building blocks in many DSP systems. It computes the output by multiplying a set of input samples with a set of coefficients followed by addition. Here, the multiplication and addition processess are based on the concept of Divide and Conquer approach. Separate multiplier and adder blocks are designed to model the FIR filter. The design was modeled using Verilog HDL and simulated and synthesized using Xilinx IS E 14.2. The design was also synthesized in Leonardo Spectrum. A comparison was made by implementing the design on different FPGA devices. The result shows that the proposed system has better device utilization in Virtex-5 FPGA.
随着与更传统的DSP技术集成的需求日益明显，DSP的可重构计算仍然是一个活跃的研究领域。传统上，可重构计算领域的大部分工作都集中在细粒度FPGA器件上。多年来，焦点从位级粒度转移到更粗粒度的组合。本文提出了一种用于可重构有限脉冲响应(FIR)滤波器的高通量和面积高效数据路径的合成方法。FIR滤波器已经并将继续是许多DSP系统的重要组成部分。它通过将一组输入样本与一组系数相乘，然后进行加法来计算输出。在这里，乘法和加法的过程是基于分治法的概念。单独的乘法器和加法器模块被设计用来模拟FIR滤波器。设计采用Verilog HDL进行建模，采用Xilinx IS E 14.2进行仿真合成。该设计也在Leonardo Spectrum中合成。通过在不同FPGA器件上的实现，对设计进行了比较。结果表明，该系统在Virtex-5 FPGA上具有较好的器件利用率。
{"title":"FPGA synthesis of area efficient data path for reconfigurable FIR filter","authors":"R. Saranya, C. Pradeep","doi":"10.1109/ICCICCT.2014.6992985","DOIUrl":"https://doi.org/10.1109/ICCICCT.2014.6992985","url":null,"abstract":"Reconfigurable computing for DSP remains an active area of research as the need for integration with more traditional DSP technologies become apparent. Traditionally, most of the work in the field of reconfigurable computing was focused on fine-grained FPGA devices. Over the years, the focus was shifted from bit level granularity to a more coarse grained composition. In this paper, we present the synthesis of high-throughput and area efficient data path for reconfigurable Finite Impulse Response (FIR) filter. FIR filters have been and continue to be important building blocks in many DSP systems. It computes the output by multiplying a set of input samples with a set of coefficients followed by addition. Here, the multiplication and addition processess are based on the concept of Divide and Conquer approach. Separate multiplier and adder blocks are designed to model the FIR filter. The design was modeled using Verilog HDL and simulated and synthesized using Xilinx IS E 14.2. The design was also synthesized in Leonardo Spectrum. A comparison was made by implementing the design on different FPGA devices. The result shows that the proposed system has better device utilization in Virtex-5 FPGA.","PeriodicalId":6615,"journal":{"name":"2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)","volume":"11 1","pages":"349-354"},"PeriodicalIF":0.0,"publicationDate":"2014-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81668400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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