Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477332
B. Dinechin
Presents a collection of slides covering the following topics: manycore processor roadmap; field-programmable gate arrays (FPGA); digital signal processors (DSP); graphics processing units (GPU); Intel many integrated core (MIC); Bostan processor architecture; and supecomputing on a chip.
{"title":"Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor","authors":"B. Dinechin","doi":"10.1109/HOTCHIPS.2015.7477332","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477332","url":null,"abstract":"Presents a collection of slides covering the following topics: manycore processor roadmap; field-programmable gate arrays (FPGA); digital signal processors (DSP); graphics processing units (GPU); Intel many integrated core (MIC); Bostan processor architecture; and supecomputing on a chip.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"145 1","pages":"1-27"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75503486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477322
Venkat Mattela
This article consists of a collection of slides from the author's conference presentation. 1. WyzBee is a single stop shop for an IOT application development. Provides significant reduction in time to market. Reduces cost of development and deployment. THING boards supported for realizing applications for all IoT market segments (connectivity, sensors, audio and video). Seamless interface to Third-party cloud services. Easy application development framework. 2. WyzBee provides secured connectivity with multi-wireless protocols. Support for Wi-Fi, Bluetooth 4.1 Dual Mode, ZigBee. Advanced On-Chip PUF security for Device Authentication and hardware / software binding. 3. WyzBee synthesizes the final product for you! Includes all hardware and software.
{"title":"IoT device development challenges and solutions","authors":"Venkat Mattela","doi":"10.1109/HOTCHIPS.2015.7477322","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477322","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. 1. WyzBee is a single stop shop for an IOT application development. Provides significant reduction in time to market. Reduces cost of development and deployment. THING boards supported for realizing applications for all IoT market segments (connectivity, sensors, audio and video). Seamless interface to Third-party cloud services. Easy application development framework. 2. WyzBee provides secured connectivity with multi-wireless protocols. Support for Wi-Fi, Bluetooth 4.1 Dual Mode, ZigBee. Advanced On-Chip PUF security for Device Authentication and hardware / software binding. 3. WyzBee synthesizes the final product for you! Includes all hardware and software.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"8 1","pages":"1-19"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78574678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477325
D. Rossi, Francesco Conti, A. Marongiu, A. Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, P. Flatresse, L. Benini
{"title":"PULP: A parallel ultra low power platform for next generation IoT applications","authors":"D. Rossi, Francesco Conti, A. Marongiu, A. Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, P. Flatresse, L. Benini","doi":"10.1109/HOTCHIPS.2015.7477325","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477325","url":null,"abstract":"","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"1 1","pages":"1-39"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76143777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477456
M. Gschwind
This article consists of a collection of slides from the author's conference presentation. POWER8 delivers advanced virtualization for CPU and I/O. POWER8 takes the next step in exploiting system accelerators. Collaborative Innovation based on Open Standards.
{"title":"I/O virtualization and system acceleration in POWER8","authors":"M. Gschwind","doi":"10.1109/HOTCHIPS.2015.7477456","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477456","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. POWER8 delivers advanced virtualization for CPU and I/O. POWER8 takes the next step in exploiting system accelerators. Collaborative Innovation based on Open Standards.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"1 1","pages":"1-26"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89814348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477459
Kalin Ovtcharov, Olatunji Ruwase, Joo-Young Kim, J. Fowers, K. Strauss, Eric S. Chung
This article consists of a collection of slides from the authors' conference presentation. Are FPGAs a Promising Target in the Datacenter for Deep Learning? Yes.
本文由作者在会议上演讲的幻灯片集合组成。fpga是深度学习数据中心的一个有前途的目标吗?是的。
{"title":"Toward accelerating deep learning at scale using specialized hardware in the datacenter","authors":"Kalin Ovtcharov, Olatunji Ruwase, Joo-Young Kim, J. Fowers, K. Strauss, Eric S. Chung","doi":"10.1109/HOTCHIPS.2015.7477459","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477459","url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. Are FPGAs a Promising Target in the Datacenter for Deep Learning? Yes.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"7 1","pages":"1-38"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87430946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477478
E. Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, V. Srinivasan, S. Lipa, E. Rotenberg, W. R. Davis, P. Franzon
This article consists of a single slide from the authors' conference presentation. Single-ISA Heterogeneous Multi-core: General purpose cores with different microarchitectures, tuned for different energy/performance points. Performance and energy of a program can be optimized by migrating among the core types as program characteristics change. Prior research has shown as much as a 50% improvement in energy when migrating every 1,000 cycles versus every 10,000 cycles. Such fine-grained thread migration requires very low migration overhead. We propose hardware support for fast thread migration. To migrate a thread, committed register values and the program counter must be moved from the source core to the destination core.
{"title":"Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor","authors":"E. Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, V. Srinivasan, S. Lipa, E. Rotenberg, W. R. Davis, P. Franzon","doi":"10.1109/HOTCHIPS.2015.7477478","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477478","url":null,"abstract":"This article consists of a single slide from the authors' conference presentation. Single-ISA Heterogeneous Multi-core: General purpose cores with different microarchitectures, tuned for different energy/performance points. Performance and energy of a program can be optimized by migrating among the core types as program characteristics change. Prior research has shown as much as a 50% improvement in energy when migrating every 1,000 cycles versus every 10,000 cycles. Such fine-grained thread migration requires very low migration overhead. We propose hardware support for fast thread migration. To migrate a thread, committed register values and the program counter must be moved from the source core to the destination core.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"11 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83457786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477473
J. Lockwood
This article consists of a collection of slides from the author's conference presentation. The presentation concludes that Gateware Defined Networking dramatically reduces latency and power and improves throughput in the data center.
{"title":"Comparison of Key/Value Store (KVS) in software and programmable hardware","authors":"J. Lockwood","doi":"10.1109/HOTCHIPS.2015.7477473","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477473","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. The presentation concludes that Gateware Defined Networking dramatically reduces latency and power and improves throughput in the data center.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"166 1","pages":"1-8"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80465918","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477474
D. Roberts, Amin Farmahini Farahani, Kevin Cheng, N. Hu, D. Mayhew, Mike Ignatowski
This article consists of a slide from the authors' conference presentation. NMI is an abstracted, unified memory interface to support future scale-out memory capacity, processing-in-memory, I/O devices, emerging non-volatile memories, cache-coherent shared virtual memory.
{"title":"NMI: A new memory interface to enable innovation","authors":"D. Roberts, Amin Farmahini Farahani, Kevin Cheng, N. Hu, D. Mayhew, Mike Ignatowski","doi":"10.1109/HOTCHIPS.2015.7477474","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477474","url":null,"abstract":"This article consists of a slide from the authors' conference presentation. NMI is an abstracted, unified memory interface to support future scale-out memory capacity, processing-in-memory, I/O devices, emerging non-volatile memories, cache-coherent shared virtual memory.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"56 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90153394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477455
Basant Vinaik, Rahoul Puri
This article consists of a collection of slides from the authors' conference presentation. The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle's products remains at the sole discretion of Oracle.
{"title":"Oracle's Sonoma processor: Advanced low-cost SPARC processor for enterprise workloads","authors":"Basant Vinaik, Rahoul Puri","doi":"10.1109/HOTCHIPS.2015.7477455","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477455","url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. The following is intended to outline our general product direction. It is intended for information purposes only, and may not be incorporated into any contract. It is not a commitment to deliver any material, code, or functionality, and should not be relied upon in making purchasing decisions. The development, release, and timing of any features or functionality described for Oracle's products remains at the sole discretion of Oracle.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"9 1","pages":"1-23"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81392583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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