Smart sensing technologies and their inherent data-processing techniques have drawn considerable research and industrial attention in recent years. Recent developments in nanometer CMOS technologies have shown great potential to deal with the increasing demand of processing power that arises in these sensing technologies, from IoT applications to complicated medical devices. Moreover, circuit implementation, which could be based on a full analog or digital approach or, in most cases, on a mixed-signal approach, possesses a fundamental role in exploiting the full capabilities of sensing technologies. In addition, all circuit design methodologies include the optimization of several performance metrics, such as low power, low cost, small area, and high throughput, which impose critical challenges in the field of sensor design. This Special Issue aims to highlight advances in the development, modeling, simulation, and implementation of integrated circuits for sensing technologies, from the component level to complete sensing systems.
{"title":"Special Issue “Smart IC Design and Sensing Technologies”","authors":"G. Floros, A. Tziouvaras","doi":"10.3390/chips1030011","DOIUrl":"https://doi.org/10.3390/chips1030011","url":null,"abstract":"Smart sensing technologies and their inherent data-processing techniques have drawn considerable research and industrial attention in recent years. Recent developments in nanometer CMOS technologies have shown great potential to deal with the increasing demand of processing power that arises in these sensing technologies, from IoT applications to complicated medical devices. Moreover, circuit implementation, which could be based on a full analog or digital approach or, in most cases, on a mixed-signal approach, possesses a fundamental role in exploiting the full capabilities of sensing technologies. In addition, all circuit design methodologies include the optimization of several performance metrics, such as low power, low cost, small area, and high throughput, which impose critical challenges in the field of sensor design. This Special Issue aims to highlight advances in the development, modeling, simulation, and implementation of integrated circuits for sensing technologies, from the component level to complete sensing systems.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"56 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74119546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the outbreak of the COVID-19 pandemic, the persistent chip shortage, war in Ukraine, and U.S.–China tensions, the semiconductor industry is at a critical stage. Only if it is capable of major changes, will it be able to sustain itself and continue to provide solutions for ongoing exponential technology growth. However, the war has undermined, perhaps definitively, a global order that urged the integration of markets above geopolitical divergences. Now that the trend seems to be reversed, the extent to which the costs of this commercial and technological decoupling can be absorbed and legitimized will have to be understood.
{"title":"The Integrated Circuit Industry at a Crossroads: Threats and Opportunities","authors":"S. Pennisi","doi":"10.3390/chips1030010","DOIUrl":"https://doi.org/10.3390/chips1030010","url":null,"abstract":"With the outbreak of the COVID-19 pandemic, the persistent chip shortage, war in Ukraine, and U.S.–China tensions, the semiconductor industry is at a critical stage. Only if it is capable of major changes, will it be able to sustain itself and continue to provide solutions for ongoing exponential technology growth. However, the war has undermined, perhaps definitively, a global order that urged the integration of markets above geopolitical divergences. Now that the trend seems to be reversed, the extent to which the costs of this commercial and technological decoupling can be absorbed and legitimized will have to be understood.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"98 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-10-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73867437","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pascal Stadler, H. Papurcu, T. Welling, Simón Tejero Tejero Alfageme, N. Pohl
In this article, a literature study has been conducted including 398 radar circuit elements from 311 recent publications (mostly between 2010 and 2022) that have been reported mainly in the F-, D- and G-Band (80–200 GHz). This study is intended to give a state-of-the-art comparison on the performance of the different technologies—RFCMOS, SiGe/BiCMOS and III–V semiconductor composites—regarding the most crucial circuit parameters of Voltage-Controlled Oscillators (VCO), Power Amplifiers (PA), Phase Shifters (PS), Low-Noise Amplifiers (LNA) and Mixers. The most common topologies of each circuit element as well as the differences between the technolgies will futher be laid out while reasoning their benefits. Since not all devices were derived solely from single device publications, necessary steps to yield as fairly a comparison as possible were taken. Results include the area and power efficiency in RFCMOS, superior noise and power performance in III–V semiconductors and a continuous compromise between efficiency and performance in SiGe. The most rarely published devices, being Mixers and PSs, in the given frequency range have also been identified to give incentive for further developments.
{"title":"An Overview of State-of-the-Art D-Band Radar System Components","authors":"Pascal Stadler, H. Papurcu, T. Welling, Simón Tejero Tejero Alfageme, N. Pohl","doi":"10.3390/chips1030009","DOIUrl":"https://doi.org/10.3390/chips1030009","url":null,"abstract":"In this article, a literature study has been conducted including 398 radar circuit elements from 311 recent publications (mostly between 2010 and 2022) that have been reported mainly in the F-, D- and G-Band (80–200 GHz). This study is intended to give a state-of-the-art comparison on the performance of the different technologies—RFCMOS, SiGe/BiCMOS and III–V semiconductor composites—regarding the most crucial circuit parameters of Voltage-Controlled Oscillators (VCO), Power Amplifiers (PA), Phase Shifters (PS), Low-Noise Amplifiers (LNA) and Mixers. The most common topologies of each circuit element as well as the differences between the technolgies will futher be laid out while reasoning their benefits. Since not all devices were derived solely from single device publications, necessary steps to yield as fairly a comparison as possible were taken. Results include the area and power efficiency in RFCMOS, superior noise and power performance in III–V semiconductors and a continuous compromise between efficiency and performance in SiGe. The most rarely published devices, being Mixers and PSs, in the given frequency range have also been identified to give incentive for further developments.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"48 4 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-09-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89197776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.
{"title":"Integrated Sensor Electronic Front-Ends with Self-X Capabilities","authors":"S. Alraho, Q. Zaman, H. Abd, A. König","doi":"10.3390/chips1020008","DOIUrl":"https://doi.org/10.3390/chips1020008","url":null,"abstract":"The ongoing vivid advance in integration technologies is giving leverage both to computing systems as well as to sensors and sensor systems. Both conventional computing systems as well as innovative computing systems, e.g., following bio-inspiration from nervous systems or neural networks, require efficient interfacing to an increasing diversity of sensors under the constraints of metrology. The realization of sufficiently accurate, robust, and flexible analog front-ends (AFE) is decisive for the overall application system and quality and requires substantial design expertise both for cells in System-on-Chip (SoC) or chips in System-in-Package (SiP) realizations. Adding robustness and flexibility to sensory systems, e.g., for Industry 4.0., by self-X or self-* features, e.g., self-monitoring, -trimming, or -healing (AFEX) approaches the capabilities met in living beings and is pursued in our research. This paper summarizes on two chips, denoted as Universal-Sensor-Interface-with-self-X-properties (USIX) based on amplitude representation and reports on recently identified challenges and corresponding advanced solutions, e.g., on circuit assessment as well as observer robustness for classic amplitude-based AFE, and transition activities to spike domain representation spiking-analog-front-ends with self-X properties (SAFEX) based on adaptive spiking electronics as the next evolutionary step in AFE development. Key cells for AFEX and SAFEX have been designed in XFAB xh035 CMOS technology and have been subject to extrinsic optimization and/or adaptation. The submitted chip features 62,921 transistors, a total area of 10.89 mm2 (74% analog, 26% digital), and 66 bytes of the configuration memory. The prepared demonstrator will allow intrinsic optimization and/or adaptation for the developed technology agnostic concepts and chip instances. In future work, confirmed cells will be moved to complete versatile and robust AFEs, which can serve both for conventional as well as innovative computing systems, e.g., spiking neurocomputers, as well as to leading-edge technologies to serve in SOCs.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"17 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-08-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79029673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, with the aim of extending the use of the CP in all those applications where a time-variant signal must be amplified with its DC component above the positive power supply rail, the signal amplification feature of a conventional Dickson charge pump (CP) has been investigated, introducing a small-signal model for each particular condition in which a CP can work. In this paper this idea is further investigated, especially under the slow switching limit (SSL) condition, and experimental validation has been carried out using a 65 nm CMOS technology for four different voltage gain values. Starting from an equivalent model of the CP, the main small- and large-signal parameters are analytically derived and discussed in depth. As a proof of concept, experimental measurements on four CPs with different numbers of stages confirm the validity of this unconventional application and the effectiveness of the CP when used as an amplifier.
{"title":"Signal Amplification by Means of a Dickson Charge Pump: Analysis and Experimental Validation","authors":"A. Ballo, A. D. Grasso, G. Palumbo","doi":"10.3390/chips1020007","DOIUrl":"https://doi.org/10.3390/chips1020007","url":null,"abstract":"Recently, with the aim of extending the use of the CP in all those applications where a time-variant signal must be amplified with its DC component above the positive power supply rail, the signal amplification feature of a conventional Dickson charge pump (CP) has been investigated, introducing a small-signal model for each particular condition in which a CP can work. In this paper this idea is further investigated, especially under the slow switching limit (SSL) condition, and experimental validation has been carried out using a 65 nm CMOS technology for four different voltage gain values. Starting from an equivalent model of the CP, the main small- and large-signal parameters are analytically derived and discussed in depth. As a proof of concept, experimental measurements on four CPs with different numbers of stages confirm the validity of this unconventional application and the effectiveness of the CP when used as an amplifier.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"51 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79156243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kemal Çağlar Coşkun, Muhammad Hassan, R. Drechsler
Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in comparison to SPICE-level simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. Functional equivalence of single Laplace Transfer Function (LTF) system-level models to respective SPICE-level models was successfully demonstrated recently. However, this is clearly not sufficient, as the complex systems comprise multiple LTF modules. In this article, we go beyond single LTF models, i.e., we develop a novel graph-based methodology to formally check equivalence between complex system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits, such as High-Pass Filters (HPF). To achieve this, first, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the two representations from separate modeling levels. This canonical representation consists of the input and output nodes and a single edge between them with an LTF as its weight. Second, we create an SFG representation with linear graph modeling for SPICE-level models, whereas for system-level models we extract an SFG from the behavioral description. We then transform the SFG representations into the canonical representation by utilizing three graph manipulation techniques, namely node removal, parallel edge unification, and reflexive edge elimination. This allows us to establish functional equivalence between complex system-level models and SPICE-level models. We demonstrate the applicability of the proposed methodology by successfully applying it to complex circuits.
{"title":"Equivalence Checking of System-Level and SPICE-Level Models of Linear Circuits","authors":"Kemal Çağlar Coşkun, Muhammad Hassan, R. Drechsler","doi":"10.3390/chips1010006","DOIUrl":"https://doi.org/10.3390/chips1010006","url":null,"abstract":"Due to the increasing complexity of analog circuits and their integration into System-on-Chips (SoC), the analog design and verification industry would greatly benefit from an expansion of system-level methodologies using SystemC AMS. These can provide a speed increase of over 100,000× in comparison to SPICE-level simulations and allow interoperability with digital tools at the system-level. However, a key barrier to the expansion of system-level tools for analog circuits is the lack of confidence in system-level models implemented in SystemC AMS. Functional equivalence of single Laplace Transfer Function (LTF) system-level models to respective SPICE-level models was successfully demonstrated recently. However, this is clearly not sufficient, as the complex systems comprise multiple LTF modules. In this article, we go beyond single LTF models, i.e., we develop a novel graph-based methodology to formally check equivalence between complex system-level and SPICE-level representations of Single-Input Single-Output (SISO) linear analog circuits, such as High-Pass Filters (HPF). To achieve this, first, we introduce a canonical representation in the form of a Signal-Flow Graph (SFG), which is used to functionally map the two representations from separate modeling levels. This canonical representation consists of the input and output nodes and a single edge between them with an LTF as its weight. Second, we create an SFG representation with linear graph modeling for SPICE-level models, whereas for system-level models we extract an SFG from the behavioral description. We then transform the SFG representations into the canonical representation by utilizing three graph manipulation techniques, namely node removal, parallel edge unification, and reflexive edge elimination. This allows us to establish functional equivalence between complex system-level models and SPICE-level models. We demonstrate the applicability of the proposed methodology by successfully applying it to complex circuits.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"18 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86531185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As Editor-in-Chief, it is my honor and pleasure to introduce Chips [...]
作为主编，我非常荣幸地向大家介绍Chips[…]
{"title":"Chips: A New Open Access Journal in the Domain of ICs","authors":"Gaetano Palumbo","doi":"10.3390/chips1010005","DOIUrl":"https://doi.org/10.3390/chips1010005","url":null,"abstract":"As Editor-in-Chief, it is my honor and pleasure to introduce Chips [...]","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"47 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-05-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80051813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Vasiliki Gavriilidou, A. Voulkidou, T. Noulis, N. Codreanu, C. Ionescu
In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.
{"title":"System on Chip Noise Integrity Simulation","authors":"Vasiliki Gavriilidou, A. Voulkidou, T. Noulis, N. Codreanu, C. Ionescu","doi":"10.3390/chips1010003","DOIUrl":"https://doi.org/10.3390/chips1010003","url":null,"abstract":"In mixed-signal integrated circuits, interference between digital noisy and sensitive analog/RF circuits is a challenging performance issue. The high cost of chip fabrication requires accurate simulation of the circuits’ performance versus signal and noise integrity. In this paper, a substrate crosstalk noise analysis flow is described and the characteristics of the substrate noise coupling mechanism are analyzed. The proposed noise integrity aware simulation flow properly estimates the substrate coupling effect and predicts the analog/RF victim circuit performance degradation due to noise coupling mechanisms. The methodology is implemented seamlessly in the current standard virtuoso-based design suite and is used in parallel with any commercial design tool, compatible with the standard analog/RF simulation process. The efficiency of the proposed methodology is validated by a full substrate crosstalk aware system on chip vehicle, designed in an RFCMOS 65 nm process. Silicon substrate, interconnect parasitics and package parasitics are efficiently modeled so as to enable the substrate noise simulation. A substrate crosstalk system on chip vehicle is designed in a 65 nm RFCMOS. The crosstalk noise victim is a 5 GHz CMOS LNA and the noise aggressor is a 90 kGates digital logic. It is demonstrated that by applying the proposed methodology, substrate crosstalk performance degradation can be efficiently captured. The LNA carrier degradation and the spectrum distortion re efficiently simulated by identifying all of the noise spurs propagating through the common silicon substrate from the digital logic to the custom low noise amplifier noise victim. The respective inter-modulation spurs are also captured.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"8 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81202840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The minimalistic hardware of most Internet of things (IoT) devices and sensors, especially those based on microcontrollers (MCU), imposes severe limitations on the memory capacity and interfacing capabilities of the device. Nevertheless, many applications prescribe not only textual but also graphical display features as output interface. Due to the aforementioned limitations, the storage of graphical data is however highly problematic and existing solutions have even resorted to requiring external storage (e.g., a microSD card) for that purpose. In this paper, we present, evaluate and discuss two solutions that enable loading fullscreen, optimal 18-bit colour image data directly from the MCU, that is, without having to rely on additional hardware. Importantly, these solutions retain a very low footprint to suit the microcontroller architecture; the AVR architecture has been selected given its popularity. The obtained results show the feasibility and practicability of the proposal: in the worst case, 21 Kbytes of memory are required, in other words approximately 33% of the flash memory of a 32-Kbyte MCU remain available.
{"title":"Memory Optimisation on AVR Microcontrollers for IoT Devices’ Minimalistic Displays","authors":"A. Bossard","doi":"10.3390/chips1010002","DOIUrl":"https://doi.org/10.3390/chips1010002","url":null,"abstract":"The minimalistic hardware of most Internet of things (IoT) devices and sensors, especially those based on microcontrollers (MCU), imposes severe limitations on the memory capacity and interfacing capabilities of the device. Nevertheless, many applications prescribe not only textual but also graphical display features as output interface. Due to the aforementioned limitations, the storage of graphical data is however highly problematic and existing solutions have even resorted to requiring external storage (e.g., a microSD card) for that purpose. In this paper, we present, evaluate and discuss two solutions that enable loading fullscreen, optimal 18-bit colour image data directly from the MCU, that is, without having to rely on additional hardware. Importantly, these solutions retain a very low footprint to suit the microcontroller architecture; the AVR architecture has been selected given its popularity. The obtained results show the feasibility and practicability of the proposal: in the worst case, 21 Kbytes of memory are required, in other words approximately 33% of the flash memory of a 32-Kbyte MCU remain available.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"36 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-04-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81850600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-01-27DOI: 10.36227/techrxiv.18724562
Danilo Pau, Prem Kumar Ambrose, F. M. Aymone
This paper presents the state-of-the-art review of the different approaches for Neural Architecture Search targeting resource constrained devices such as microcontrollers. As well as the implementations of On-Device learning techniques for those devices.
{"title":"A quantitative review of automated neural search and on-device learning for tiny devices","authors":"Danilo Pau, Prem Kumar Ambrose, F. M. Aymone","doi":"10.36227/techrxiv.18724562","DOIUrl":"https://doi.org/10.36227/techrxiv.18724562","url":null,"abstract":"This paper presents the state-of-the-art review of the different approaches for Neural Architecture Search targeting resource constrained\u0000 devices such as microcontrollers. As well as the implementations of On-Device learning techniques for those devices.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"52 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2022-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83953698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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