Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477328
This article consists of a collection of slides from the author's conference presentation. Take Home Messages: Deep Learning is enabling a new wave of applications; Deep Learning and Convolutional Nets are widely deployed; We need hardware (and software) for embedded applications; But we are still far from building truly intelligent machines.
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Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477460
Vinay Gangadhar, Raghuraman Balasubramanian, M. Drumond, Ziliang Guo, J. Menon, Cherin Joseph, Robin Prakash, Sharath Prasad, Pradip Vallathol, K. Sankaralingam
This article consists of a collection of slides from the authors' conference presentation. MIAOW is a credible GPGPU implementation. Compatible with AMD Southern Islands ISA. Runs OpenCL programs and prototyped on FPGA. Similar design to industry state-of-art. Similar performance to industry state-of-art. Flexible and Extendable. MIOAW's hardware design is Open Source. Contributes to changing hardware landscape.
{"title":"MIAOW: An open source GPGPU","authors":"Vinay Gangadhar, Raghuraman Balasubramanian, M. Drumond, Ziliang Guo, J. Menon, Cherin Joseph, Robin Prakash, Sharath Prasad, Pradip Vallathol, K. Sankaralingam","doi":"10.1109/HOTCHIPS.2015.7477460","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477460","url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. MIAOW is a credible GPGPU implementation. Compatible with AMD Southern Islands ISA. Runs OpenCL programs and prototyped on FPGA. Similar design to industry state-of-art. Similar performance to industry state-of-art. Flexible and Extendable. MIOAW's hardware design is Open Source. Contributes to changing hardware landscape.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"9 1","pages":"1-43"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73041761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477471
K. Yamazaki, Yoshihiro Nakajima, T. Hatano, A. Miyazaki
This article consists of one slide from the authors' conference presentation. Some of the topics discussed include: What is SDN and why?; What is Lagopus vSwitch?; Packet processing on multi-core CPUs; Issues of CPU centralized processing; Designing concept and architecture; FPGA flow classification & dispatch empowered by SDNet and flow director; Performance vs. Power Dissipation; and Demonstration.
{"title":"Lagopus FPGA -- A reprogrammable data plane for high-performance software SDN switches","authors":"K. Yamazaki, Yoshihiro Nakajima, T. Hatano, A. Miyazaki","doi":"10.1109/HOTCHIPS.2015.7477471","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477471","url":null,"abstract":"This article consists of one slide from the authors' conference presentation. Some of the topics discussed include: What is SDN and why?; What is Lagopus vSwitch?; Packet processing on multi-core CPUs; Issues of CPU centralized processing; Designing concept and architecture; FPGA flow classification & dispatch empowered by SDNet and flow director; Performance vs. Power Dissipation; and Demonstration.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"23 1 1","pages":"1-1"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82921922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477468
D. Nagaraj, C. Gianos
This article consists of a collection of slides from the authors' conference presentation. Conclusions: Broadwell-DE brings Xeon class performance and capabilities to dense solutions with higher power efficiency; Focused engineering to co-optimize the platform and SoC to achieve density and power targets; Rich feature set across Virtualization, Security RAS and Power Management; New optimization choices for Hyperscale cloud environments, Networking and for dense, low power storage solutions; Delivers up to 3.4X the performance and up to 1.7X perf/watt over the 22nm Atom C2000 SoC family.
本文由作者在会议上演讲的幻灯片集合组成。结论:Broadwell-DE为高密度解决方案带来了至强级的性能和能力，并具有更高的功率效率;聚焦工程，共同优化平台和SoC，以实现密度和功耗目标;丰富的功能集跨越虚拟化，安全RAS和电源管理;针对超大规模云环境、网络和密集、低功耗存储解决方案的新优化选择;与22nm Atom C2000 SoC系列相比，可提供高达3.4倍的性能和高达1.7倍的perf/watt。
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Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477330
Z. Nikolic, R. Venkatasubramanian, Jason A. T. Jones, Peter Labaziewicz
This article consists of a collection of slides from the author's conference presentation. Agenda items include: highlight challenges of implementing Advanced Driver Assistance Systems (ADAS) in embedded systems; Discuss ADAS system options and compromises; High level overview of TDAx SOC; Mapping ADAS use cases to devices from TDAx SOC families.
{"title":"A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA","authors":"Z. Nikolic, R. Venkatasubramanian, Jason A. T. Jones, Peter Labaziewicz","doi":"10.1109/HOTCHIPS.2015.7477330","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477330","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Agenda items include: highlight challenges of implementing Advanced Driver Assistance Systems (ADAS) in embedded systems; Discuss ADAS system options and compromises; High level overview of TDAx SOC; Mapping ADAS use cases to devices from TDAx SOC families.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"40 1","pages":"1-32"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80538982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477320
C. Nitta
This article consists of a collection of slides from the author's conference presentation. He introduces the tutorial agenda: Maker Trends: The Path of Least Resistance Peter Dokter, SparkFun; IoT Device Development Challenges and Solutions Venkat Mattela and Sailaja Dharani, Redpine Signals; lmplementing Software Defined Radio on the Parallella Andreas Olofsson, Adapteva; Current Trends for Hardware & Software Developers Vrajesh Bhavsar, ARM.
本文由作者在会议上的演讲幻灯片组成。他介绍了教程议程:Maker Trends: the Path of Least Resistance;物联网设备开发挑战和解决方案Venkat Mattela和Sailaja Dharani, Redpine Signals;软件定义无线电在并行网络上的实现硬件和软件开发者的当前趋势Vrajesh Bhavsar
{"title":"Makers from Hobbyists to professionals","authors":"C. Nitta","doi":"10.1109/HOTCHIPS.2015.7477320","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477320","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. He introduces the tutorial agenda: Maker Trends: The Path of Least Resistance Peter Dokter, SparkFun; IoT Device Development Challenges and Solutions Venkat Mattela and Sailaja Dharani, Redpine Signals; lmplementing Software Defined Radio on the Parallella Andreas Olofsson, Adapteva; Current Trends for Hardware & Software Developers Vrajesh Bhavsar, ARM.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"44 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88409215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477462
Ian Bratt
This article consists of a collection of slides from the author's conference presentation. Mali-T880 Conclusion: Tile-based deferred rasterization with hierarchical tiling; Pipelined rendering, overlapping vertex processing and tiling from one frame, with fragment processing from the previous frame; Scalable from 1->16 shader cores, serving several markets; On-chip network enables ease of scalability; Integrated MMU and fixed-function Tiler; A pixel/cycle shader core serves as the fundamental building block, supporting simultaneous vertex and fragment shading; Designed from the ground up for power management; Multiple BW saving techniques, including Transaction Elimination, ARM Frame Buffer Compression, and Adaptive Scalable Texture Compression.
{"title":"The ARM® Mali-T880 Mobile GPU","authors":"Ian Bratt","doi":"10.1109/HOTCHIPS.2015.7477462","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477462","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Mali-T880 Conclusion: Tile-based deferred rasterization with hierarchical tiling; Pipelined rendering, overlapping vertex processing and tiling from one frame, with fragment processing from the previous frame; Scalable from 1->16 shader cores, serving several markets; On-chip network enables ease of scalability; Integrated MMU and fixed-function Tiler; A pixel/cycle shader core serves as the fundamental building block, supporting simultaneous vertex and fragment shading; Designed from the ground up for power management; Multiple BW saving techniques, including Transaction Elimination, ARM Frame Buffer Compression, and Adaptive Scalable Texture Compression.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"60 1","pages":"1-27"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85995874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.1109/HOTCHIPS.2015.7477457
V. Boppana, Sagheer Ahmad, I. Ganusov, Vinod Kathail, V. Rajagopalan, Ralph Wittig
This article consists of a collection of slides from the authors' conference presentation. Zynq UltraScale+ MPSoC: 2nd Generation SoC from Xilinx - Applications processing, Real-time, Graphics, Video, Serial connectivity - Power management, Safety, Security - SDSoC: Full system optimizing compiler; More than Moore: Architectural innovation - 3x CPU performance and 4.5x memory bandwidth (SoC) -UltraScale+ fabric: 60% higher performance, 2.5x performance/watt (FPGA) - 3rd generation of silicon interposer technology (3D IC); Taped out in Jun 2015 on TSMC 16FF+ - Significant power and performance benefits with 3D FinFet transistors - Diverse SW and systems running on multiple platforms today.
{"title":"UltraScale+ MPSoC and FPGA families","authors":"V. Boppana, Sagheer Ahmad, I. Ganusov, Vinod Kathail, V. Rajagopalan, Ralph Wittig","doi":"10.1109/HOTCHIPS.2015.7477457","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2015.7477457","url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation. Zynq UltraScale+ MPSoC: 2nd Generation SoC from Xilinx - Applications processing, Real-time, Graphics, Video, Serial connectivity - Power management, Safety, Security - SDSoC: Full system optimizing compiler; More than Moore: Architectural innovation - 3x CPU performance and 4.5x memory bandwidth (SoC) -UltraScale+ fabric: 60% higher performance, 2.5x performance/watt (FPGA) - 3rd generation of silicon interposer technology (3D IC); Taped out in Jun 2015 on TSMC 16FF+ - Significant power and performance benefits with 3D FinFet transistors - Diverse SW and systems running on multiple platforms today.","PeriodicalId":6666,"journal":{"name":"2015 IEEE Hot Chips 27 Symposium (HCS)","volume":"145 1","pages":"1-37"},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81487264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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