Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786699
E. Siri, M. Golsorkhtabaramiri, Amir Safaei
One of the main challenges in modern anti-collision algorithms in RFID systems is to estimate the number of collided tags in each slot of identification process. This paper presents a novel solution in Vogt tag estimation algorithm which is used in assigned tree slotted aloha (ATSA) method based on Chaos optimization algorithm. This method has been examined with logistic chaotic map and outcomes are compared with classical method. Simulation is accomplished with 12-bit ID which covers the full serial number bit length and the tags number are considered up to 4096 tags. Some criterions such as the number of collision slots, idle slots, and total slots are compared and simulation results show an improvement in system throughput.
{"title":"A New Method in RFID Anti-Collision Protocol using Chaos Optimization Algorithm","authors":"E. Siri, M. Golsorkhtabaramiri, Amir Safaei","doi":"10.1109/IranianCEE.2019.8786699","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786699","url":null,"abstract":"One of the main challenges in modern anti-collision algorithms in RFID systems is to estimate the number of collided tags in each slot of identification process. This paper presents a novel solution in Vogt tag estimation algorithm which is used in assigned tree slotted aloha (ATSA) method based on Chaos optimization algorithm. This method has been examined with logistic chaotic map and outcomes are compared with classical method. Simulation is accomplished with 12-bit ID which covers the full serial number bit length and the tags number are considered up to 4096 tags. Some criterions such as the number of collision slots, idle slots, and total slots are compared and simulation results show an improvement in system throughput.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"03 1","pages":"2062-2066"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90364368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786463
M. Pezhman, A. Heidari
In this paper, two compact multi-aperture substrate integrated waveguide (SIW) couplers are proposed for Ku-band applications. These couplers are designed using ray-tracing method (RTM). RTM is a simple method that can be used for initial design of SIW multi-aperture couplers (MACs). In order to reduce the size of the MAC, two rows of vias are inserted at two sides of SIWs, along the coupling apertures. Then, two structures are proposed and analyzed using RTM. The length of the coupling aperture is reduced by 15% and 26% for the first and second designs, respectively. The proposed structures are simulated and optimized using HFSS software. The results show that the couplers have good return loss, high isolation between output ports, and a broadband frequency bandwidth.
{"title":"Design of compact SIW-based multi-aperture coupler for Ku-band applications","authors":"M. Pezhman, A. Heidari","doi":"10.1109/IranianCEE.2019.8786463","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786463","url":null,"abstract":"In this paper, two compact multi-aperture substrate integrated waveguide (SIW) couplers are proposed for Ku-band applications. These couplers are designed using ray-tracing method (RTM). RTM is a simple method that can be used for initial design of SIW multi-aperture couplers (MACs). In order to reduce the size of the MAC, two rows of vias are inserted at two sides of SIWs, along the coupling apertures. Then, two structures are proposed and analyzed using RTM. The length of the coupling aperture is reduced by 15% and 26% for the first and second designs, respectively. The proposed structures are simulated and optimized using HFSS software. The results show that the couplers have good return loss, high isolation between output ports, and a broadband frequency bandwidth.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"6 1","pages":"1338-1341"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88475679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786501
M. I. Hosseini, M. Harandi, Seyed ahmad Khalilpour seyedi, Hamid reza Dokht taghirad
Increasing the speed and precision of operation in cable robots is crucial due to the flexibility of cables. On the other hand, due to the frequent dynamical uncertainties present in cable robots, providing a robust control method is necessary. The performance of the fast terminal sliding mode (FTSM) controller has been investigated in various systems, which ensures that the state of the system is rapidly converged to the equilibrium point at a finite time. In this paper, the FTSM controller has been developed in such a way to be able to track the optimal robot path in the presence of dynamic uncertainties at different operating speeds. The main innovation of this paper is to provide an adaptive robust control method for controlling cable robots and analyzing the stability of the closed-loop control system based on the Lyapunov stability theory. In order to demonstrate the effectiveness of the proposed controller, simulation results, as well as experimental implementation on ARAS-CAM, a four cable suspended robot with three degrees of freedom, has been investigated and it is shown that the proposed controller can provide suitable tracking performance in practice.
{"title":"Adaptive Fast Terminal Sliding Mode Control of A Suspended Cable-Driven Robot","authors":"M. I. Hosseini, M. Harandi, Seyed ahmad Khalilpour seyedi, Hamid reza Dokht taghirad","doi":"10.1109/IranianCEE.2019.8786501","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786501","url":null,"abstract":"Increasing the speed and precision of operation in cable robots is crucial due to the flexibility of cables. On the other hand, due to the frequent dynamical uncertainties present in cable robots, providing a robust control method is necessary. The performance of the fast terminal sliding mode (FTSM) controller has been investigated in various systems, which ensures that the state of the system is rapidly converged to the equilibrium point at a finite time. In this paper, the FTSM controller has been developed in such a way to be able to track the optimal robot path in the presence of dynamic uncertainties at different operating speeds. The main innovation of this paper is to provide an adaptive robust control method for controlling cable robots and analyzing the stability of the closed-loop control system based on the Lyapunov stability theory. In order to demonstrate the effectiveness of the proposed controller, simulation results, as well as experimental implementation on ARAS-CAM, a four cable suspended robot with three degrees of freedom, has been investigated and it is shown that the proposed controller can provide suitable tracking performance in practice.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"30 1","pages":"985-990"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76586295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786441
Mohammad Khademi, I. Izadi, M. Kamali, Farid Sheiholeslam
In this paper, controller design for networked control systems with input delay and output limitations is studied. An auxiliary signal is defined to separate the input delay from system input. Also, barrier Lyapunov functions are utilized to deal with output limitations. The nonlinear functions in the model, which assumed unknown, are another limitation. These unknown nonlinear functions are estimated using fuzzy logic systems. Based on these techniques a controller is designed. Stability analysis proves that all the signals in the closed-loop system are semi-globally uniformly ultimately bounded. Simulation results are provided to support the theory.
{"title":"An Adaptive Fuzzy Backstepping Controller for Delay Compensation in Networked Control Systems","authors":"Mohammad Khademi, I. Izadi, M. Kamali, Farid Sheiholeslam","doi":"10.1109/IranianCEE.2019.8786441","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786441","url":null,"abstract":"In this paper, controller design for networked control systems with input delay and output limitations is studied. An auxiliary signal is defined to separate the input delay from system input. Also, barrier Lyapunov functions are utilized to deal with output limitations. The nonlinear functions in the model, which assumed unknown, are another limitation. These unknown nonlinear functions are estimated using fuzzy logic systems. Based on these techniques a controller is designed. Stability analysis proves that all the signals in the closed-loop system are semi-globally uniformly ultimately bounded. Simulation results are provided to support the theory.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"13 1","pages":"1157-1162"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76689341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786578
Marjan Gholamrezaii, Seyed Mohammad Taghi Almodarresi
Activity recognition represents the task of classifying data derived from different sensor types into one of predefined activity classes. Convolutional neural networks (CNN) as one of the best deep learning methods has recently attracted much attention to the problem of activity recognition, Most convolutional neural networks used for recognition task are built using convolution and pooling layers followed by a few number of fully connected layers. In this paper, we propose a new architecture based on 2D convolutional neural network that consists solely of convolutional layers and find that with removing the pooling layers and instead adding strides to convolution layers, the computation time will decrease notably while the model performance will not change or in some cases will even improve. Also its performance will be compared with some other handcrafted feature based methods. The third point that will be discussed in this paper is the impact of applying fast fourier transform to inputs before training learning algorithm. It will be shown that this preprocessing will enhance the model performance. Experiments on benchmark dataset demonstrate the high performance of proposed 2D CNN model with no pooling layers, achieving an overall accuracy of 95.69% on the test set.
{"title":"Human Activity Recognition Using 2D Convolutional Neural Networks","authors":"Marjan Gholamrezaii, Seyed Mohammad Taghi Almodarresi","doi":"10.1109/IranianCEE.2019.8786578","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786578","url":null,"abstract":"Activity recognition represents the task of classifying data derived from different sensor types into one of predefined activity classes. Convolutional neural networks (CNN) as one of the best deep learning methods has recently attracted much attention to the problem of activity recognition, Most convolutional neural networks used for recognition task are built using convolution and pooling layers followed by a few number of fully connected layers. In this paper, we propose a new architecture based on 2D convolutional neural network that consists solely of convolutional layers and find that with removing the pooling layers and instead adding strides to convolution layers, the computation time will decrease notably while the model performance will not change or in some cases will even improve. Also its performance will be compared with some other handcrafted feature based methods. The third point that will be discussed in this paper is the impact of applying fast fourier transform to inputs before training learning algorithm. It will be shown that this preprocessing will enhance the model performance. Experiments on benchmark dataset demonstrate the high performance of proposed 2D CNN model with no pooling layers, achieving an overall accuracy of 95.69% on the test set.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"27 1","pages":"1682-1686"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78037796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786469
S. Heidari, J. R. Mohassel, R. Nemati, N. Karimian, N. Masoumi
In this paper a 2-way (3-section) structure for a Wilkinson Power Divider is proposed to increase frequency range. This study, allows designers to obtain a desirable operational frequency, using either a direct or a combination of cascaded power combiner sections with a new defect structure. By designing and utilizing the Defected Ground Structure (DGS), named as butterfly comb, the ground plane is patterned to improve the bandwidth. In this research, the proposed DGS pattern results in improvements, by etching the metal layer without increasing the size or employing any extra components. The power divider has been simulated using ADS, and fabricated on 32 mils FR4 substrate. After employing the designed DGS, the measurement results illustrates 133% fractional bandwidth or 37% improvement compared with conventional 3-section Wilkinson power divider. This improvement is achieved with a return loss reference of −15 dB for 0.5-2.5 GHz.
{"title":"DGS for a Wilkinson Power Divider Using a Symmetric Butterfly Comb","authors":"S. Heidari, J. R. Mohassel, R. Nemati, N. Karimian, N. Masoumi","doi":"10.1109/IranianCEE.2019.8786469","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786469","url":null,"abstract":"In this paper a 2-way (3-section) structure for a Wilkinson Power Divider is proposed to increase frequency range. This study, allows designers to obtain a desirable operational frequency, using either a direct or a combination of cascaded power combiner sections with a new defect structure. By designing and utilizing the Defected Ground Structure (DGS), named as butterfly comb, the ground plane is patterned to improve the bandwidth. In this research, the proposed DGS pattern results in improvements, by etching the metal layer without increasing the size or employing any extra components. The power divider has been simulated using ADS, and fabricated on 32 mils FR4 substrate. After employing the designed DGS, the measurement results illustrates 133% fractional bandwidth or 37% improvement compared with conventional 3-section Wilkinson power divider. This improvement is achieved with a return loss reference of −15 dB for 0.5-2.5 GHz.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"98 1","pages":"264-268"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78101906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786757
Armin Choopani, Shahaboddin Ghajari, A. Safarian
A novel frequency synthesizer architecture for reducing spur level is presented. By using a feedforward path a new zero in the transfer function is generated which enables us to increase the capacitor tied to the control voltage line and thus reducing spur level. A fast settling technique is also used to compensate the effect of spur reduction technique on settling time. Different blocks of frequency synthesizer are implemented in MATLAB/Simulink. Simulations show 13 dB improvement in reference spur level compared to conventional architecture for a 2.4 GHz frequency synthesizer.
{"title":"Novel Frequency Synthesizer for Spur Level Reduction","authors":"Armin Choopani, Shahaboddin Ghajari, A. Safarian","doi":"10.1109/IranianCEE.2019.8786757","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786757","url":null,"abstract":"A novel frequency synthesizer architecture for reducing spur level is presented. By using a feedforward path a new zero in the transfer function is generated which enables us to increase the capacitor tied to the control voltage line and thus reducing spur level. A fast settling technique is also used to compensate the effect of spur reduction technique on settling time. Different blocks of frequency synthesizer are implemented in MATLAB/Simulink. Simulations show 13 dB improvement in reference spur level compared to conventional architecture for a 2.4 GHz frequency synthesizer.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"9 1","pages":"76-81"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75182419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786400
Amir Tasdighi, M. Menhaj
The use of wind power, as a major source of renewable energy, has been growing worldwide in recent decades. A large number of wind turbine (WT) generators has been deployed on wind farms located at both land and sea areas to meet the ever increasing demand for alternative energy resources. In order to improve the efficiency and the reliability of WTs, advanced fault detection, diagnosis and accommodation plans are of great importance. This paper proposes a model predictive controller using Laguerre functions with the aim of designing a fault tolerant control scheme which ensures the reliable performance of wind turbine in case of fault occurrence in the WT's pitch and generator actuators. In addition, a model-based strategy relying on recursive least squares (RLS) algorithm is proposed for fault identification. We provide an analytical stability analysis of the controller through the Lyapunov function candidate. The accuracy and the efficiency of the proposed method is evaluated and compared with conventional controllers in two different scenarios, namely, in the presence of actuator faults and in a fault-free system.
{"title":"Fault Tolerant Model Predictive Control of Wind Turbine Against Actuator Faults Using Laguerre Functions","authors":"Amir Tasdighi, M. Menhaj","doi":"10.1109/IranianCEE.2019.8786400","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786400","url":null,"abstract":"The use of wind power, as a major source of renewable energy, has been growing worldwide in recent decades. A large number of wind turbine (WT) generators has been deployed on wind farms located at both land and sea areas to meet the ever increasing demand for alternative energy resources. In order to improve the efficiency and the reliability of WTs, advanced fault detection, diagnosis and accommodation plans are of great importance. This paper proposes a model predictive controller using Laguerre functions with the aim of designing a fault tolerant control scheme which ensures the reliable performance of wind turbine in case of fault occurrence in the WT's pitch and generator actuators. In addition, a model-based strategy relying on recursive least squares (RLS) algorithm is proposed for fault identification. We provide an analytical stability analysis of the controller through the Lyapunov function candidate. The accuracy and the efficiency of the proposed method is evaluated and compared with conventional controllers in two different scenarios, namely, in the presence of actuator faults and in a fault-free system.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"340 1","pages":"898-903"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75354306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786608
Abdolvahab Khalili Sadaghiani, M. Ghanbari
Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a fast 2D-DCT architecture for hardware efficient embedded systems and power limited applications such as Internet of Things (IoT). The proposed design both from a structure point of view and operation reduction point of view has two headed approaches toward the problem of image and video compression. It includes a modified high speed architecture using an extra operational reducing technique. Reduction of operations occurs in two stages while computing 8-point DCT transform of the blocks. Defining the appropriate threshold for comparing DCT domain of two rows of an 8*8 block. Approximating DCT operations column-wise is the additional approach of the paper. The architecture is implemented on Xilinx Vivado 2018.2 with VHDL language on Artix-7 FPGA. 207 MHz clock frequency has achieved.
{"title":"An Optimized Hardware Design for high speed 2D-DCT processor based on modified Loeffler architecture","authors":"Abdolvahab Khalili Sadaghiani, M. Ghanbari","doi":"10.1109/IranianCEE.2019.8786608","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786608","url":null,"abstract":"Discrete Cosine Transform (DCT) has an important role in image compression. This paper presents a fast 2D-DCT architecture for hardware efficient embedded systems and power limited applications such as Internet of Things (IoT). The proposed design both from a structure point of view and operation reduction point of view has two headed approaches toward the problem of image and video compression. It includes a modified high speed architecture using an extra operational reducing technique. Reduction of operations occurs in two stages while computing 8-point DCT transform of the blocks. Defining the appropriate threshold for comparing DCT domain of two rows of an 8*8 block. Approximating DCT operations column-wise is the additional approach of the paper. The architecture is implemented on Xilinx Vivado 2018.2 with VHDL language on Artix-7 FPGA. 207 MHz clock frequency has achieved.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"15 1","pages":"1476-1480"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74972956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-04-01DOI: 10.1109/IranianCEE.2019.8786551
M. Sanaeepur
The effect of substrate surface roughness on the resistivity of graphene nanoribbons (GNRs) and consequently the resistance of multy-layer GNR (MLGNR) interconnects with perfect edges is semiclassically calculated. Results show that besides line edge roughness, the surface roughness of underlying dielectric material can severely increase the resistance of MLGNR interconnects, hence, it must be considered in design considerations.
{"title":"On the Resistivity of Multi-Layer Graphene Nanoribbon Interconnects","authors":"M. Sanaeepur","doi":"10.1109/IranianCEE.2019.8786551","DOIUrl":"https://doi.org/10.1109/IranianCEE.2019.8786551","url":null,"abstract":"The effect of substrate surface roughness on the resistivity of graphene nanoribbons (GNRs) and consequently the resistance of multy-layer GNR (MLGNR) interconnects with perfect edges is semiclassically calculated. Results show that besides line edge roughness, the surface roughness of underlying dielectric material can severely increase the resistance of MLGNR interconnects, hence, it must be considered in design considerations.","PeriodicalId":6683,"journal":{"name":"2019 27th Iranian Conference on Electrical Engineering (ICEE)","volume":"81 1","pages":"50-53"},"PeriodicalIF":0.0,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72855874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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