Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612792
Y. Lim, Rui Yang
The application of the frequency-response-masking technique for the synthesis of computationally efficient sharp filters has been discussed widely in the literature. However, all of the previously reported frequency-response-masking methods are efficient for synthesizing filters operating in the single rate environment only. In this paper, we extend the frequency response-masking technique into the design of multirate filters. Our method is eminently suitable for the synthesis of anti-aliasing and anti-imagining filters for interpolation and decimation operations.
{"title":"The synthesis of linear-phase multirate frequency-response-masking filters","authors":"Y. Lim, Rui Yang","doi":"10.1109/ISCAS.1997.612792","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612792","url":null,"abstract":"The application of the frequency-response-masking technique for the synthesis of computationally efficient sharp filters has been discussed widely in the literature. However, all of the previously reported frequency-response-masking methods are efficient for synthesizing filters operating in the single rate environment only. In this paper, we extend the frequency response-masking technique into the design of multirate filters. Our method is eminently suitable for the synthesis of anti-aliasing and anti-imagining filters for interpolation and decimation operations.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80243048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621540
E. Tiiliharju, S. Zarabadi, M. Ismail, K. Halonen
A "Super-MOS" maximum output swing CMOS/BiCMOS cascode circuit for use as a basic building block of low-voltage small geometry integrated circuits (on the order of 1 micron and smaller) is described. The described circuit provides a high output impedance and maximum output voltage swing capability. Its applications to a current mirroring circuit and to a VHF OTA are discussed.
{"title":"A novel very-high-output-impedance high-swing cascode stage and its applications","authors":"E. Tiiliharju, S. Zarabadi, M. Ismail, K. Halonen","doi":"10.1109/ISCAS.1997.621540","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621540","url":null,"abstract":"A \"Super-MOS\" maximum output swing CMOS/BiCMOS cascode circuit for use as a basic building block of low-voltage small geometry integrated circuits (on the order of 1 micron and smaller) is described. The described circuit provides a high output impedance and maximum output voltage swing capability. Its applications to a current mirroring circuit and to a VHF OTA are discussed.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80264359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621912
S. Qiu
This paper presents a cell model of chaotic attractor that describes practical chaotic behaviors and explains the chaos-producing mechanisms of nonlinear systems. It has been shown that: (1) there are one or more real attractors, the "hybrid attractors", in a chaotic attractor, and (2) a quasi-periodic motion (QM) and an isolate direct motion (DM) occur alternately and convert each other in a chaotic system, and the quasi-periodicity of QM and the wandering nature of DM are the main causes of chaos-evolving. Two criteria for the existence of chaotic attractor are given as well.
{"title":"A cell model of chaotic attractor","authors":"S. Qiu","doi":"10.1109/ISCAS.1997.621912","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621912","url":null,"abstract":"This paper presents a cell model of chaotic attractor that describes practical chaotic behaviors and explains the chaos-producing mechanisms of nonlinear systems. It has been shown that: (1) there are one or more real attractors, the \"hybrid attractors\", in a chaotic attractor, and (2) a quasi-periodic motion (QM) and an isolate direct motion (DM) occur alternately and convert each other in a chaotic system, and the quasi-periodicity of QM and the wandering nature of DM are the main causes of chaos-evolving. Two criteria for the existence of chaotic attractor are given as well.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80547895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.622018
G. Fujita, T. Onoye, I. Shirakawa
A VLSI architecture of a motion estimator is described for the H.263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional Processing Element array is devised to be tuned to the H.263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1.34 mm/sup 2/ by using 0.35 /spl mu/m CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures.
{"title":"A new motion estimation core dedicated to H.263 video coding","authors":"G. Fujita, T. Onoye, I. Shirakawa","doi":"10.1109/ISCAS.1997.622018","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.622018","url":null,"abstract":"A VLSI architecture of a motion estimator is described for the H.263 low bitrate video coding. Adopting an efficient hierarchical search algorithm, a new motion estimator yields high quality vectors with small area occupancy and at a low operation frequency. A one-dimensional Processing Element array is devised to be tuned to the H.263 encoding, which treats both the advanced prediction mode and the PB-frame mode. The proposed motion estimation core is integrated in 1.34 mm/sup 2/ by using 0.35 /spl mu/m CMOS 3LM technology, which operates at 15 MHz, and hence enables the realtime motion estimation of QCIF pictures.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80552311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.622079
S. Tsekeridou, I. Pitas, C. Le Buhan
The problem of errors occurring in MPEG-2 coded video sequences, caused by signal loss during transmission, is examined in this paper and an attempt is made to reconstruct the lost parts at each frame. The proposed error concealment scheme exploits reconstructed temporal information from previously decoded frames in order to conceal bitstream errors in all types of frames: I, P, or B, as long as temporal information is available. Since no such information is available for the first frame (I-frame) of an MPEG-2 coded sequence, another concealment technique is added to the proposed scheme, which uses spatial information from neighbouring macroblocks (MBs). The simulation results compared with other methods prove to be better judging from both PSNR values and the perceived visual quality of the reconstructed sequence. Its quality ameliorates with time.
{"title":"An error concealment scheme for MPEG-2 coded video sequences","authors":"S. Tsekeridou, I. Pitas, C. Le Buhan","doi":"10.1109/ISCAS.1997.622079","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.622079","url":null,"abstract":"The problem of errors occurring in MPEG-2 coded video sequences, caused by signal loss during transmission, is examined in this paper and an attempt is made to reconstruct the lost parts at each frame. The proposed error concealment scheme exploits reconstructed temporal information from previously decoded frames in order to conceal bitstream errors in all types of frames: I, P, or B, as long as temporal information is available. Since no such information is available for the first frame (I-frame) of an MPEG-2 coded sequence, another concealment technique is added to the proposed scheme, which uses spatial information from neighbouring macroblocks (MBs). The simulation results compared with other methods prove to be better judging from both PSNR values and the perceived visual quality of the reconstructed sequence. Its quality ameliorates with time.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80432584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621530
S. Choe, G. Rigby, G. Hellestrand
A new logic family which uses less power compared to conventional logic is described. Power reduction is achieved by recycling the charge from the evaluate cycle for the precharge cycle. The logic of each stage is pipelined anti the cascade chain operates on a four phase clock. Power metrics for both gate and overall power (sum of gate and clock power) are presented. Simulations demonstrate a reduction of 40% to 50% in the gate power consumption compared to conventional logic.
{"title":"Dynamic half rail differential logic for low power","authors":"S. Choe, G. Rigby, G. Hellestrand","doi":"10.1109/ISCAS.1997.621530","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621530","url":null,"abstract":"A new logic family which uses less power compared to conventional logic is described. Power reduction is achieved by recycling the charge from the evaluate cycle for the precharge cycle. The logic of each stage is pipelined anti the cascade chain operates on a four phase clock. Power metrics for both gate and overall power (sum of gate and clock power) are presented. Simulations demonstrate a reduction of 40% to 50% in the gate power consumption compared to conventional logic.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82973602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608994
W. Porod, C. Lent, G. Tóth, H. Luo, Á. Csurgay, Y.-F. Huang, R.-W. Liu
We discuss a novel nano-electronic computing paradigm in which cells composed of interacting quantum dots are employed in a locally-interconnected architecture. We develop a network-theoretic description in terms of appropriate local state variables in each cell.
{"title":"Quantum-dot cellular nonlinear networks: computing with locally-connected quantum dot arrays","authors":"W. Porod, C. Lent, G. Tóth, H. Luo, Á. Csurgay, Y.-F. Huang, R.-W. Liu","doi":"10.1109/ISCAS.1997.608994","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608994","url":null,"abstract":"We discuss a novel nano-electronic computing paradigm in which cells composed of interacting quantum dots are employed in a locally-interconnected architecture. We develop a network-theoretic description in terms of appropriate local state variables in each cell.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75832501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608820
B. Mirzai, D. Lím, G. Moschytz
In this paper we investigate the dynamic behavior of the simplest anti-symmetric CNN. Stable equilibria of the system for constant boundary values are investigated. We provide a comparison with the simplest symmetric CNN in terms of dynamics and stable equilibria.
{"title":"On the dynamics and stable equilibria of anti-symmetric CNNs","authors":"B. Mirzai, D. Lím, G. Moschytz","doi":"10.1109/ISCAS.1997.608820","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608820","url":null,"abstract":"In this paper we investigate the dynamic behavior of the simplest anti-symmetric CNN. Stable equilibria of the system for constant boundary values are investigated. We provide a comparison with the simplest symmetric CNN in terms of dynamics and stable equilibria.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77737399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621599
Yun-Nan Chang, J. Satyanarayana, K. K. Parhi
Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (/spl les/4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.
{"title":"Low-power digit-serial multipliers","authors":"Yun-Nan Chang, J. Satyanarayana, K. K. Parhi","doi":"10.1109/ISCAS.1997.621599","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621599","url":null,"abstract":"Digit-serial implementation styles are best suited for implementation of digital signal processing systems which require moderate sampling rates. Digit-serial multipliers obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, an alternative approach for the design of digit-serial multipliers is presented based on a novel cell replacement transformation. This transformation permits bit-level pipelining of the digit-serial multipliers thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for smaller digit-sizes (/spl les/4), the type-II multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is /spl sim//spl radic/2W, where W represents the word length. The proposed digit-serial multipliers consume on an average 1.75 times lower power than the traditional digit-serial architectures for the non-pipelined case, and about 15 times lower power for the bit-level pipelined case.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81194043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608684
Shuo-Yuan Hsiao, Chung-Yu Wu
A new CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed new combiner circuit, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 /spl mu/m N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV/sub p.p/ at both inputs. The measured -3 dB bandwidth is 2.2 MHz and the power dissipation is 2.8 mW. The input bandwidth of the multiplier can be designed to reach the GHz range. Simple structure, low-voltage low-power capability, and high performance make the proposed multiplier quite feasible in many applications.
{"title":"A 1.2 V CMOS four-quadrant analog multiplier","authors":"Shuo-Yuan Hsiao, Chung-Yu Wu","doi":"10.1109/ISCAS.1997.608684","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608684","url":null,"abstract":"A new CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed new combiner circuit, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 /spl mu/m N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV/sub p.p/ at both inputs. The measured -3 dB bandwidth is 2.2 MHz and the power dissipation is 2.8 mW. The input bandwidth of the multiplier can be designed to reach the GHz range. Simple structure, low-voltage low-power capability, and high performance make the proposed multiplier quite feasible in many applications.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81200168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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