Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608878
Chuen-Yau Chen, Chun-Yueh Huang, Bin-Da Liu
A current-mode circuit based on square-root and squarer/divider circuits to realize the centre of gravity defuzzify strategy is described in this paper. The current-mode approach allows it to operate at 3.3 V without degrading its dynamic range. This proposed circuit had been fabricated in 0.8 /spl mu/m single-polysilicon-double-metal technology, and the experimental results showed that it can operate with high speed and low power dissipation.
{"title":"A current-mode defuzzifier circuit to realize the centroid strategy","authors":"Chuen-Yau Chen, Chun-Yueh Huang, Bin-Da Liu","doi":"10.1109/ISCAS.1997.608878","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608878","url":null,"abstract":"A current-mode circuit based on square-root and squarer/divider circuits to realize the centre of gravity defuzzify strategy is described in this paper. The current-mode approach allows it to operate at 3.3 V without degrading its dynamic range. This proposed circuit had been fabricated in 0.8 /spl mu/m single-polysilicon-double-metal technology, and the experimental results showed that it can operate with high speed and low power dissipation.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"13 1","pages":"609-612 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86194566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621594
S.M. Kang, H. Duan, J. Lockwood, J. D. Will
This paper discusses the principle of a versatile, 3-dimensional queue (3DQ) and its prototype implementation-illinois input Queue (iiQueue) module for input-buffered ATM switches. 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per virtual connection Quality-of-Service (QoS) and avoids Head-Of-Line (HOL) blocking. Implemented with field programmable gate array (FPGA) devices for the core 3DQ logic on a 6-layer printed circuit board (PCB), iiQueue prototype module can process ATM cells at 622 Mb/s (OC-12). With multichip module (MCM) and fast GaAs logic implementation, iiQueue module is expected to process cells at 2.5 Gb/s (OC-48).
{"title":"iiQueue, a QoS-oriented queue module for input-buffered ATM switches","authors":"S.M. Kang, H. Duan, J. Lockwood, J. D. Will","doi":"10.1109/ISCAS.1997.621594","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621594","url":null,"abstract":"This paper discusses the principle of a versatile, 3-dimensional queue (3DQ) and its prototype implementation-illinois input Queue (iiQueue) module for input-buffered ATM switches. 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per virtual connection Quality-of-Service (QoS) and avoids Head-Of-Line (HOL) blocking. Implemented with field programmable gate array (FPGA) devices for the core 3DQ logic on a 6-layer printed circuit board (PCB), iiQueue prototype module can process ATM cells at 622 Mb/s (OC-12). With multichip module (MCM) and fast GaAs logic implementation, iiQueue module is expected to process cells at 2.5 Gb/s (OC-48).","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"80 1","pages":"2144-2147 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83953707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608780
M. El-Gamal, V. Leung, G. Roberts
General transfer characteristics of log-domain integrators necessary to realize different log-domain filter topologies, based on LC ladder synthesis, are described. As an example, a transistor-level all-NPN differential log-domain integrator is proposed and used to implement a fully tunable balanced 600 MHz biquad. The integrator is then used to implement 4/sup th/ and 6/sup th/-order balanced bandpass filters. The sensitivity of log-domain integrators to DC biasing offsets is discussed. These offsets are minimized using a BiCMOS common mode feedback circuit. Simulation results are presented with an emphasis on distortion analysis.
{"title":"Balanced log-domain filters for VHF applications","authors":"M. El-Gamal, V. Leung, G. Roberts","doi":"10.1109/ISCAS.1997.608780","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608780","url":null,"abstract":"General transfer characteristics of log-domain integrators necessary to realize different log-domain filter topologies, based on LC ladder synthesis, are described. As an example, a transistor-level all-NPN differential log-domain integrator is proposed and used to implement a fully tunable balanced 600 MHz biquad. The integrator is then used to implement 4/sup th/ and 6/sup th/-order balanced bandpass filters. The sensitivity of log-domain integrators to DC biasing offsets is discussed. These offsets are minimized using a BiCMOS common mode feedback circuit. Simulation results are presented with an emphasis on distortion analysis.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"58 1","pages":"493-496 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83955281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612898
Andreea Spineanu, R. Kielbasa
In this paper the design and performance of an electromechanical sigma-delta modulator for acceleration measuring systems is presented. It has been designed by a top-down system approach and is based on a piezoelectric measuring cell integrated in the first stage of a second order continuous-time sigma-delta modulator. It aims at a working range of /spl plusmn/1 g and 8-bit resolution. The spotted application is in vibration measurement.
{"title":"An electromechanical sigma-delta modulator for acceleration measuring systems","authors":"Andreea Spineanu, R. Kielbasa","doi":"10.1109/ISCAS.1997.612898","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612898","url":null,"abstract":"In this paper the design and performance of an electromechanical sigma-delta modulator for acceleration measuring systems is presented. It has been designed by a top-down system approach and is based on a piezoelectric measuring cell integrated in the first stage of a second order continuous-time sigma-delta modulator. It aims at a working range of /spl plusmn/1 g and 8-bit resolution. The spotted application is in vibration measurement.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"44 7 1","pages":"2765-2768 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82713495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621559
An-Nan Suen, Jhing-Fa Wang, Horng-Jei Chang
In this paper, the fixed-point accuracy analysis and VLSI architecture of FS1O16 CELP decoder are presented. The code excited linear predictive (CELP) coder is the most effective technique among various linear predictive coding methods for speech compression. Hence to design a low cost and low power CELP decoder chip for the portable systems and wireless digital communication environment becomes increasingly important. The decoder VLSI architecture can achieve (1) excellent accuracy results due to the accuracy studies for the finite word length, (2) power saving and high speed operations resulting from the combined advantages of pipeline, current processing for LSE's interpolating and cosine operation, (3) table size reducing by applying the memoryless realization for stochastic codebook and partial sums technique, and (4) specification satisfying the FS1016 CELP coder.
{"title":"On the fixed-point error analysis and VLSI architecture for FS1016 CELP decoder","authors":"An-Nan Suen, Jhing-Fa Wang, Horng-Jei Chang","doi":"10.1109/ISCAS.1997.621559","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621559","url":null,"abstract":"In this paper, the fixed-point accuracy analysis and VLSI architecture of FS1O16 CELP decoder are presented. The code excited linear predictive (CELP) coder is the most effective technique among various linear predictive coding methods for speech compression. Hence to design a low cost and low power CELP decoder chip for the portable systems and wireless digital communication environment becomes increasingly important. The decoder VLSI architecture can achieve (1) excellent accuracy results due to the accuracy studies for the finite word length, (2) power saving and high speed operations resulting from the combined advantages of pipeline, current processing for LSE's interpolating and cosine operation, (3) table size reducing by applying the memoryless realization for stochastic codebook and partial sums technique, and (4) specification satisfying the FS1016 CELP coder.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"27 1","pages":"2052-2055 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86606452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612903
Yu-sheng Lin, Shanshan Yang, Su-Jen Fang, C. Shung
Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority control selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA), and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8/spl times/8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130 k gates in a chip area of 137.88 mm/sup 2/ using 0.6 /spl mu/m CMOS technology.
{"title":"VLSI design of a priority arbitrator for shared buffer ATM switches","authors":"Yu-sheng Lin, Shanshan Yang, Su-Jen Fang, C. Shung","doi":"10.1109/ISCAS.1997.612903","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612903","url":null,"abstract":"Priority arbitration is an essential part of the ATM switches in order to support the integration of telecommunication services with difference characteristics. Service priority control selects the connection to output a cell among all connections destined to the same output port. Discard priority control selects the connection to discard a cell when the shared buffer is full. In this paper we present a VLSI design of a priority arbitrator for shared buffer ATM switches. This priority arbitrator is targeted to support our new service priority control scheme, reactive bandwidth arbitration (RBA), and new discard priority control scheme, local pushout discarding (LPD). The priority arbitrator is designed for an 8/spl times/8 shared buffer ATM switch with four priority classes per port and a link rate of 622 Mbps. The chip has 130 k gates in a chip area of 137.88 mm/sup 2/ using 0.6 /spl mu/m CMOS technology.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"84 1","pages":"2785-2788 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86736869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621453
M. Styblinski, P. Gajer, J. Lei
A method of handling uncertain statistical information and its (approximate) propagation through an IC is proposed, utilizing the concepts of fuzzy numbers and fuzzy arithmetic, combined with the propagation of moments method of statistical analysis, leading to a new method of propagation of fuzzy variance. A symbolic implementation of this method is proposed, allowing one to efficiently represent the relevant membership functions.
{"title":"A symbolic fuzzy number approach to the propagation of uncertain statistical information in IC design","authors":"M. Styblinski, P. Gajer, J. Lei","doi":"10.1109/ISCAS.1997.621453","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621453","url":null,"abstract":"A method of handling uncertain statistical information and its (approximate) propagation through an IC is proposed, utilizing the concepts of fuzzy numbers and fuzzy arithmetic, combined with the propagation of moments method of statistical analysis, leading to a new method of propagation of fuzzy variance. A symbolic implementation of this method is proposed, allowing one to efficiently represent the relevant membership functions.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"109 1","pages":"1664-1667 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88984826","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612908
F. Mombers, D. Nicoulaz, M. Gumm, S. Dogimont, D. Mlynek, F. Bellifemine, P. Garino, A. Torielli
This paper describes the core of a video signal processor dedicated to perform MPEG-2 motion estimation and prediction selection. A mixed Hardware/Software approach based on a small RISC controller was adopted which gives flexibility and robustness in the choice of the algorithms. Hardware optimizations were investigated to implement genetic motion estimation algorithm which appears to be the best candidate for this kind of architecture. The candidate motion vectors generated by the controller allow nearly full search quality with a drastic decrease of the required calculation power and the hardware complexity.
{"title":"A video signal processor core for motion estimation in MPEG2 encoding","authors":"F. Mombers, D. Nicoulaz, M. Gumm, S. Dogimont, D. Mlynek, F. Bellifemine, P. Garino, A. Torielli","doi":"10.1109/ISCAS.1997.612908","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612908","url":null,"abstract":"This paper describes the core of a video signal processor dedicated to perform MPEG-2 motion estimation and prediction selection. A mixed Hardware/Software approach based on a small RISC controller was adopted which gives flexibility and robustness in the choice of the algorithms. Hardware optimizations were investigated to implement genetic motion estimation algorithm which appears to be the best candidate for this kind of architecture. The candidate motion vectors generated by the controller allow nearly full search quality with a drastic decrease of the required calculation power and the hardware complexity.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"20 1","pages":"2805-2808 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89187227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608647
Shu-Chuan Huang, Chin Chang
This paper presents a BiCMOS rail-to-rail operational amplifier for low-voltage applications. CMOS differential pairs are used for the input stage to achieve high input impedances. The BJT translinear principle is then employed in the design of a constant-g/sub m/ circuit to control the tail currents of the complementary differential pairs properly. Mismatching between K/sub n/ and K/sub p/ is compensated by a a K/sub n/-K/sub p/ matching circuit employing the MOS translinear principle. The resulting variation of the total g/sub m/ is within 13% according to the simulation. The output stage is also rail-to-rail with a class AB control. When configured as a unity-gain buffer with a 10 kHz sinusoidal wave applied, the total harmonic distortion simulated from SPICE is less than 0.06% with the input amplitude less than 1.4 V and 0.114% at 1.5 V. This op amp will be fabricated in a CMP/AMS 0.8 /spl mu/m DPDM BiCMOS process, and the experimental results will be reported later.
{"title":"Design of a BiCMOS constant-g/sub m/ rail-to-rail operational amplifier for low-voltage applications","authors":"Shu-Chuan Huang, Chin Chang","doi":"10.1109/ISCAS.1997.608647","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608647","url":null,"abstract":"This paper presents a BiCMOS rail-to-rail operational amplifier for low-voltage applications. CMOS differential pairs are used for the input stage to achieve high input impedances. The BJT translinear principle is then employed in the design of a constant-g/sub m/ circuit to control the tail currents of the complementary differential pairs properly. Mismatching between K/sub n/ and K/sub p/ is compensated by a a K/sub n/-K/sub p/ matching circuit employing the MOS translinear principle. The resulting variation of the total g/sub m/ is within 13% according to the simulation. The output stage is also rail-to-rail with a class AB control. When configured as a unity-gain buffer with a 10 kHz sinusoidal wave applied, the total harmonic distortion simulated from SPICE is less than 0.06% with the input amplitude less than 1.4 V and 0.114% at 1.5 V. This op amp will be fabricated in a CMP/AMS 0.8 /spl mu/m DPDM BiCMOS process, and the experimental results will be reported later.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"23 1","pages":"161-164 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90051587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621454
P.R.S. Mendonca, L. Calôba
This paper introduces a new class of D-dimensional density probability functions to be used in Simulated Annealing algorithms and derives an appropriate cooling schedule that is proved to be inversely proportional to a previously chosen power n of time. This generates a new algorithm, the nFast Simulated Annealing (nFSA), from which the Fast Simulated Annealing (FSA) is a particular case. As will be shown, this new algorithm achieves results with an accuracy that increases with n, at the expense of an initial convergence speed that decreases with n. This drawback is solved by the use of an adaptive algorithm, the Adaptive nFast Simulated Annealing (AnFSA), where the parameter n starts at small value, producing a fast initial convergence, and is raised as the algorithm runs, finding global minima points quickly and with great accuracy.
{"title":"New simulated annealing algorithms","authors":"P.R.S. Mendonca, L. Calôba","doi":"10.1109/ISCAS.1997.621454","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621454","url":null,"abstract":"This paper introduces a new class of D-dimensional density probability functions to be used in Simulated Annealing algorithms and derives an appropriate cooling schedule that is proved to be inversely proportional to a previously chosen power n of time. This generates a new algorithm, the nFast Simulated Annealing (nFSA), from which the Fast Simulated Annealing (FSA) is a particular case. As will be shown, this new algorithm achieves results with an accuracy that increases with n, at the expense of an initial convergence speed that decreases with n. This drawback is solved by the use of an adaptive algorithm, the Adaptive nFast Simulated Annealing (AnFSA), where the parameter n starts at small value, producing a fast initial convergence, and is raised as the algorithm runs, finding global minima points quickly and with great accuracy.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"36 6 1","pages":"1668-1671 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89141292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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