Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608652
L.H.Y. Leung, A. Buchwald
This paper describes a CMOS 10-MHz Variable Gain Amplifier (VGA) with 60-dB dynamic-range. The gain is continuously tunable over a 6-dB range, with a minimum gain of unity and a maximum gain of two. Continuous gain tuning is accomplished by a novel method of interpolating between 10 taps of a feedback resistor, respectively connected to a fully-differential multi-input-stage operational amplifier. Measured results with a 10-MHz input show THD below -60-dB with a 4-V/sub pp/ differential output signal. Third-order inter-modulation distortion, for two equal amplitude tones at 9.5-MHz and 10.5-MHz, remains below -59.17-dBc over all gain settings. The circuit has been fabricated in a 0.8-/spl mu/m CMOS process (Hewlett Packard CMOS26G), occupies an area of 0.6/spl times/1-mm/sup 2/ and dissipates 80-mW.
{"title":"10-MHz 60-dB dynamic-range 6-dB variable gain amplifier","authors":"L.H.Y. Leung, A. Buchwald","doi":"10.1109/ISCAS.1997.608652","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608652","url":null,"abstract":"This paper describes a CMOS 10-MHz Variable Gain Amplifier (VGA) with 60-dB dynamic-range. The gain is continuously tunable over a 6-dB range, with a minimum gain of unity and a maximum gain of two. Continuous gain tuning is accomplished by a novel method of interpolating between 10 taps of a feedback resistor, respectively connected to a fully-differential multi-input-stage operational amplifier. Measured results with a 10-MHz input show THD below -60-dB with a 4-V/sub pp/ differential output signal. Third-order inter-modulation distortion, for two equal amplitude tones at 9.5-MHz and 10.5-MHz, remains below -59.17-dBc over all gain settings. The circuit has been fabricated in a 0.8-/spl mu/m CMOS process (Hewlett Packard CMOS26G), occupies an area of 0.6/spl times/1-mm/sup 2/ and dissipates 80-mW.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"23 1","pages":"173-176 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80570512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612879
T. Nagai, S. Tsutsui, M. Ikehara
In this research, we propose a new design method for the generalized linear-phase lapped orthogonal transforms (GenLOT). The GenLOT is based on the DCT and has fast implementation algorithm. Generally, the lattice structure is used for its design and implementation. Consequently, nonlinear optimization is required for its design process. In our proposed method, filter coefficients are optimized directly and this method requires one only to solve linear equations iteratively. Moreover, this algorithm converges within a few iterations.
{"title":"Iterative procedure for designing the GenLOT","authors":"T. Nagai, S. Tsutsui, M. Ikehara","doi":"10.1109/ISCAS.1997.612879","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612879","url":null,"abstract":"In this research, we propose a new design method for the generalized linear-phase lapped orthogonal transforms (GenLOT). The GenLOT is based on the DCT and has fast implementation algorithm. Generally, the lattice structure is used for its design and implementation. Consequently, nonlinear optimization is required for its design process. In our proposed method, filter coefficients are optimized directly and this method requires one only to solve linear equations iteratively. Moreover, this algorithm converges within a few iterations.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"36 1","pages":"2689-2692 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80571005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608767
R. Rivoir, F. Maloberti
A new comparator architecture for high-resolution, rail-to-rail comparison at high-speed and low power dissipation is presented. The internal structure of the comparator permits one to overcome the technological constraints arising from a purely digital process. In particular, no precision capacitors are needed in this design. The newly developed circuit consists of three different gain stages before a dynamic latch. The first stage achieves a rail-to-rail operation owing to two distinct amplifiers working in parallel. The two outputs are separately offset compensated and then connected to a differential difference amplifier (DDA). A third high-swing stage, preceding a current-limited dynamic latch, is used to ensure a fast regeneration time. Particular care has been taken to limit not only the static, but also the dynamic power dissipation of the digital part. Circuit simulations on 0.5 /spl mu/m, 3.3 V single-supply CMOS digital technology show that this architecture can easily achieve a 10 MS/s speed, at the expense of only 165 /spl mu/A typical static current consumption.
{"title":"A 1 mV resolution 10 MS/s rail-to-rail comparator in 0.5 /spl mu/m low-voltage CMOS digital process","authors":"R. Rivoir, F. Maloberti","doi":"10.1109/ISCAS.1997.608767","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608767","url":null,"abstract":"A new comparator architecture for high-resolution, rail-to-rail comparison at high-speed and low power dissipation is presented. The internal structure of the comparator permits one to overcome the technological constraints arising from a purely digital process. In particular, no precision capacitors are needed in this design. The newly developed circuit consists of three different gain stages before a dynamic latch. The first stage achieves a rail-to-rail operation owing to two distinct amplifiers working in parallel. The two outputs are separately offset compensated and then connected to a differential difference amplifier (DDA). A third high-swing stage, preceding a current-limited dynamic latch, is used to ensure a fast regeneration time. Particular care has been taken to limit not only the static, but also the dynamic power dissipation of the digital part. Circuit simulations on 0.5 /spl mu/m, 3.3 V single-supply CMOS digital technology show that this architecture can easily achieve a 10 MS/s speed, at the expense of only 165 /spl mu/A typical static current consumption.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"16 1","pages":"461-464 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83673380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608664
F. Chang, K. Pun
Wavelet Method has been found to be very effective in treating singularities due to its properties of localization both in time/spatial and frequency domains. Singularities exist in the simulation of semiconductor devices. We now introduce the Discrete B-spline wavelet method for semiconductor devices simulation. Starting from the governing equations of semiconductor devices, the wavelet basis is used to solve these nonlinear ordinary differential equations. We find it much better than conventional finite difference methods in both computational time and accuracy. As an example, the steady state response of an abrupt P-N junction diode demonstrates this effectiveness.
{"title":"Discrete B-spline wavelet method for semiconductor device simulation","authors":"F. Chang, K. Pun","doi":"10.1109/ISCAS.1997.608664","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608664","url":null,"abstract":"Wavelet Method has been found to be very effective in treating singularities due to its properties of localization both in time/spatial and frequency domains. Singularities exist in the simulation of semiconductor devices. We now introduce the Discrete B-spline wavelet method for semiconductor devices simulation. Starting from the governing equations of semiconductor devices, the wavelet basis is used to solve these nonlinear ordinary differential equations. We find it much better than conventional finite difference methods in both computational time and accuracy. As an example, the steady state response of an abrupt P-N junction diode demonstrates this effectiveness.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"8 1","pages":"193-196 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81036081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612790
M. Moniri
This paper introduces an adaptive discrete time operator called the /spl beta/-operator for the design of high sampling rate recursive digital filters. It is shown that this operator is superior to the z-operator and,can also provide better numerical advantages compared with the /spl delta/-operator. In fact the /spl delta/-operator is only a special case of the /spl beta/-operator. Simulation examples are given comparing between different operators.
{"title":"/spl beta/-operator: an adaptive discrete-time operator model for high sampling rate recursive digital filters","authors":"M. Moniri","doi":"10.1109/ISCAS.1997.612790","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612790","url":null,"abstract":"This paper introduces an adaptive discrete time operator called the /spl beta/-operator for the design of high sampling rate recursive digital filters. It is shown that this operator is superior to the z-operator and,can also provide better numerical advantages compared with the /spl delta/-operator. In fact the /spl delta/-operator is only a special case of the /spl beta/-operator. Simulation examples are given comparing between different operators.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"46 1","pages":"2333-2336 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88612669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621430
Yao-Wen Chang, D. F. Wong, Cheng-Chi Wong
Switch modules are the most important component of the routing resources in FPGAs/FPICs. We consider in this paper an FPGA/FPIC switch-module analyse's problem: The inputs consist of a switch-module description and the number of nets required to be routed through the switch module; the question is to determine if there exists a feasible routing for the routing requirements on the switch module. This problem is applicable to the routability evaluation of FPGA/FPIC switch modules, the switch-module design for FPGAs/FPICs, and FPGA/FPIC routing. We present a graph-theoretic sufficient condition for the analyse's problem. The implications of the condition are: (1) there exist several classes of efficient approximation algorithms for the analysis problem; (2) there exist several classes of switch-module architectures on which the analysis problem can be solved efficiently.
{"title":"A graph-theoretic sufficient condition for FPGA/FPIC switch-module routability","authors":"Yao-Wen Chang, D. F. Wong, Cheng-Chi Wong","doi":"10.1109/ISCAS.1997.621430","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621430","url":null,"abstract":"Switch modules are the most important component of the routing resources in FPGAs/FPICs. We consider in this paper an FPGA/FPIC switch-module analyse's problem: The inputs consist of a switch-module description and the number of nets required to be routed through the switch module; the question is to determine if there exists a feasible routing for the routing requirements on the switch module. This problem is applicable to the routability evaluation of FPGA/FPIC switch modules, the switch-module design for FPGAs/FPICs, and FPGA/FPIC routing. We present a graph-theoretic sufficient condition for the analyse's problem. The implications of the condition are: (1) there exist several classes of efficient approximation algorithms for the analysis problem; (2) there exist several classes of switch-module architectures on which the analysis problem can be solved efficiently.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"34 1","pages":"1572-1575 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88784444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612800
H. C. Reddy, I-Hung Khoo, G. Moschytz, A. Stubberud
This paper provides the theory and an efficient tabular algorithm to test for various symmetries in the magnitude response of two-dimensional (2-D) complex-coefficient delta operator formulated discrete-time systems. In general, centro symmetry is not preserved in the complex case. The conditions under which this is preserved is discussed in the paper. It is to be noted that as the sampling period (/spl Delta/) goes to zero, the symmetry conditions merge with that of 2-D continuous-time case.
{"title":"Theory and test procedure for symmetries in the frequency response of complex two-dimensional delta operator formulated discrete-time systems","authors":"H. C. Reddy, I-Hung Khoo, G. Moschytz, A. Stubberud","doi":"10.1109/ISCAS.1997.612800","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612800","url":null,"abstract":"This paper provides the theory and an efficient tabular algorithm to test for various symmetries in the magnitude response of two-dimensional (2-D) complex-coefficient delta operator formulated discrete-time systems. In general, centro symmetry is not preserved in the complex case. The conditions under which this is preserved is discussed in the paper. It is to be noted that as the sampling period (/spl Delta/) goes to zero, the symmetry conditions merge with that of 2-D continuous-time case.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"30 1","pages":"2373-2376 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87283232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621481
Z. Li, P. Mok, W. Ki, Johnny K. O. Sin
A simple design method has been developed to investigate the dimming control of electronic ballast circuits for fluorescent lamps. This method is based on the steady-state calculation of the ballast at resonant frequency, f/sub 0/, and the inherent characteristics of the fluorescent lamp, i.e. the relationship between the lamp resistance and the lamp power. The inherent lamp characteristics encompass the fact that the voltage across the lamp varies with the lamp power. Including this inherent characteristic into a new lamp Spice simulation model can provide an accurate simulation result of the relations between the ballast operation frequency and the lamp power.
{"title":"A simple method to design resonant circuits of electronic ballast for fluorescent lamps","authors":"Z. Li, P. Mok, W. Ki, Johnny K. O. Sin","doi":"10.1109/ISCAS.1997.621481","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621481","url":null,"abstract":"A simple design method has been developed to investigate the dimming control of electronic ballast circuits for fluorescent lamps. This method is based on the steady-state calculation of the ballast at resonant frequency, f/sub 0/, and the inherent characteristics of the fluorescent lamp, i.e. the relationship between the lamp resistance and the lamp power. The inherent lamp characteristics encompass the fact that the voltage across the lamp varies with the lamp power. Including this inherent characteristic into a new lamp Spice simulation model can provide an accurate simulation result of the relations between the ballast operation frequency and the lamp power.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"60 1","pages":"1744-1747 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84699264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621510
Ching-Sung Wang, Shih-Yi Yuan, Ke-Horng Chen, S. Kuo
In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (V/sub int/) and have low input signal swing. As long as V/sub int/>|V/sub t/| (assuming V/sub tn/=-V/sub tp/), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf; the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr=Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.
{"title":"A new BiCMOS increased full swing converter for low-internal-voltage ULSI systems","authors":"Ching-Sung Wang, Shih-Yi Yuan, Ke-Horng Chen, S. Kuo","doi":"10.1109/ISCAS.1997.621510","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621510","url":null,"abstract":"In this paper a new BiCMOS increased full swing inverter (IFSI) and a new BiCMOS increased full swing buffer (IFSB) for low voltage/low power ULSI (Ultra Large Scale Integration) systems are proposed. These circuits can operate at low internal voltage (V/sub int/) and have low input signal swing. As long as V/sub int/>|V/sub t/| (assuming V/sub tn/=-V/sub tp/), the circuits can work properly. The proposed BiCMOS IFSC circuits are suitable for high-speed operations. When the capacitor load is larger than 0.6 pf; the propagation delay and the delay power product at different internal voltages are better than previous circuits under the same circuit design parameters. We also establish the relationship between the Kr=Kn/Kp ratio and the circuit area. This can avoid the trial and error step in the circuit sizing operation to reduce the power consumption.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"10 21 1","pages":"1856-1859 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80649033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621872
J. Verbeeck, R. Pintelon, P. Guillaume
This paper deals with the problem of the determination of synchronous machine parameters starting from two-port information. Network synthesis techniques are used to show that no unique solution can be found for models containing more than one damper winding. Only a limited number of parameters can be determined in a unique way from two-port information.
{"title":"Determination of synchronous machine parameters using network synthesis techniques","authors":"J. Verbeeck, R. Pintelon, P. Guillaume","doi":"10.1109/ISCAS.1997.621872","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621872","url":null,"abstract":"This paper deals with the problem of the determination of synchronous machine parameters starting from two-port information. Network synthesis techniques are used to show that no unique solution can be found for models containing more than one damper winding. Only a limited number of parameters can be determined in a unique way from two-port information.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"18 1","pages":"949-952 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89246509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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