Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.608810
A. Moini, A. Bouzerdoum, K. Esbraghian
In this paper we present a current-mode VLSI implementation of shunting inhibition. Our approach uses translinear circuit design techniques using MOS transistors operating in the subthreshold region. Compared to previous implementations our design achieves a larger dynamic range and also clearly demonstrates the dependence of the spatio-temporal response of the network on the input light mean-intensity. A 64-cell one-dimensional array of the SI circuit has been implemented and fabricated in a 2/spl mu/ CMOS process. Hspice simulation results as well as test results obtained from the chip are presented and discussed.
在本文中，我们提出了一个电流模式的VLSI实现分流抑制。我们的方法使用在亚阈值区域工作的MOS晶体管的跨线性电路设计技术。与以前的实现相比，我们的设计实现了更大的动态范围，也清楚地表明了网络的时空响应对输入光平均强度的依赖。在2/spl μ m / CMOS工艺下，实现并制作了64单元SI电路的一维阵列。给出并讨论了该芯片的Hspice仿真结果和测试结果。
{"title":"A current mode implementation of shunting inhibition","authors":"A. Moini, A. Bouzerdoum, K. Esbraghian","doi":"10.1109/ISCAS.1997.608810","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.608810","url":null,"abstract":"In this paper we present a current-mode VLSI implementation of shunting inhibition. Our approach uses translinear circuit design techniques using MOS transistors operating in the subthreshold region. Compared to previous implementations our design achieves a larger dynamic range and also clearly demonstrates the dependence of the spatio-temporal response of the network on the input light mean-intensity. A 64-cell one-dimensional array of the SI circuit has been implemented and fabricated in a 2/spl mu/ CMOS process. Hspice simulation results as well as test results obtained from the chip are presented and discussed.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"55 1","pages":"557-560 vol.1"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78676154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621854
Billy K. H. Wong, H. Chung
A new computer-aided analysis technique for switching power regulators is proposed. The methodology is based on piecewise quadratic formulation of reactive element state variables with progressive analysis of switches' operation. The prominent features of this method include: 1) its simplicity in not requiring any complicated mathematical calculation, such as solving Laplace-transformed equations and differential formulas, 2) its generality in determining valid topological configuration without prior understanding of the circuit operation, 3) its directness in calculating switching instants, 4) its consideration of parasitic elements. An example of a practical switch mode buck regulator with overcurrent protection and maximum duty-cycle control is illustrated. The simulated results are favorably compared with the waveforms obtained by other available literature.
{"title":"Fast computer-aided analysis technique for switching power regulators based on direct determination of switches' state","authors":"Billy K. H. Wong, H. Chung","doi":"10.1109/ISCAS.1997.621854","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621854","url":null,"abstract":"A new computer-aided analysis technique for switching power regulators is proposed. The methodology is based on piecewise quadratic formulation of reactive element state variables with progressive analysis of switches' operation. The prominent features of this method include: 1) its simplicity in not requiring any complicated mathematical calculation, such as solving Laplace-transformed equations and differential formulas, 2) its generality in determining valid topological configuration without prior understanding of the circuit operation, 3) its directness in calculating switching instants, 4) its consideration of parasitic elements. An example of a practical switch mode buck regulator with overcurrent protection and maximum duty-cycle control is illustrated. The simulated results are favorably compared with the waveforms obtained by other available literature.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"104 1","pages":"881-884 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75964606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621924
T. Stojanovski, L. Kocarev, U. Parlitz, R. Harris
The concept of time-discontinuous coupling of two identical chaotic systems called sporadic coupling is explained. The sufficient conditions for the occurrence of synchronization between sporadically coupled chaotic systems are given. Amplitude quantization of the driving signal in addition to the sporadic coupling allows digital exchange of digital information signals between the sporadically coupled chaotic systems.
{"title":"Digital chaotic encoding of digital information","authors":"T. Stojanovski, L. Kocarev, U. Parlitz, R. Harris","doi":"10.1109/ISCAS.1997.621924","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621924","url":null,"abstract":"The concept of time-discontinuous coupling of two identical chaotic systems called sporadic coupling is explained. The sufficient conditions for the occurrence of synchronization between sporadically coupled chaotic systems are given. Amplitude quantization of the driving signal in addition to the sporadic coupling allows digital exchange of digital information signals between the sporadically coupled chaotic systems.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"68 1","pages":"1057-1060 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87837688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.622138
Ealgoo Kim, Daeyun Shim, Seong-Ik Jang, Gyudong Kim, Wonchan Kim
A very hardware and computation efficient method for frame motion characterization is developed. Instead of dealing a 2-dimensional m/spl times/n picture elements, this algorithm generates two 1-dimensional vectors, by mathematically operating the luminance values of vertical and horizontal lines as the characteristic valves of x and y direction, respectively. The efficiency of this algorithm is demonstrated by decomposition of frame changes into various factors: the motion of objects, panning and zooming. Applications in automatic motion tracking system and image stabilizer are discussed.
{"title":"A global motion characterization method using one-dimensional characteristic curves for image processing applications","authors":"Ealgoo Kim, Daeyun Shim, Seong-Ik Jang, Gyudong Kim, Wonchan Kim","doi":"10.1109/ISCAS.1997.622138","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.622138","url":null,"abstract":"A very hardware and computation efficient method for frame motion characterization is developed. Instead of dealing a 2-dimensional m/spl times/n picture elements, this algorithm generates two 1-dimensional vectors, by mathematically operating the luminance values of vertical and horizontal lines as the characteristic valves of x and y direction, respectively. The efficiency of this algorithm is demonstrated by decomposition of frame changes into various factors: the motion of objects, panning and zooming. Applications in automatic motion tracking system and image stabilizer are discussed.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"12 1","pages":"1393-1396 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87057438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621490
S. Guha, R. Puvvada, D. Suri, I. Suzuki
A powerful new method, randomized preprocessing for motion planning, has emerged recently with great success in robotics, specially when the configuration space is high-dimensional. Our contributions in this paper are two. We describe and implement: (a) a cell-division based heuristic for the node generation phase of randomized preprocessing based on iterative and controlled splitting of the configuration space, and (b) a new approach to randomized preprocessing, termed ray shooting in which we randomly generate rays, instead of isolated configurations, in the configuration space. Our experiments indicate that for certain robots either approach significantly improves performance over naive randomized preprocessing.
{"title":"New approaches in randomized preprocessing for motion planning","authors":"S. Guha, R. Puvvada, D. Suri, I. Suzuki","doi":"10.1109/ISCAS.1997.621490","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621490","url":null,"abstract":"A powerful new method, randomized preprocessing for motion planning, has emerged recently with great success in robotics, specially when the configuration space is high-dimensional. Our contributions in this paper are two. We describe and implement: (a) a cell-division based heuristic for the node generation phase of randomized preprocessing based on iterative and controlled splitting of the configuration space, and (b) a new approach to randomized preprocessing, termed ray shooting in which we randomly generate rays, instead of isolated configurations, in the configuration space. Our experiments indicate that for certain robots either approach significantly improves performance over naive randomized preprocessing.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"5 1","pages":"1780-1783 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87525266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.622086
Yong Kwan Kim, R. Kim, Sang Uk Lee
In this paper, a temporally adaptive layered video coding technique employing the 3-D subband coding (SBC) is proposed. By using the R-D performance measure, the input video is divided adaptively into temporal layers, according to the temporal activity. Then, while the base layer is encoded by H.261, the enhancement layer is encoded by the 3-D SBC technique. From the simulation results, the proposed technique shows about 1 dB PSNR gain over the conventional layered coding techniques, including the twin-H.261, even under heavy ATM network loading.
{"title":"A temporally adaptive layered video coding technique employing the 3-D SBC for ATM networks","authors":"Yong Kwan Kim, R. Kim, Sang Uk Lee","doi":"10.1109/ISCAS.1997.622086","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.622086","url":null,"abstract":"In this paper, a temporally adaptive layered video coding technique employing the 3-D subband coding (SBC) is proposed. By using the R-D performance measure, the input video is divided adaptively into temporal layers, according to the temporal activity. Then, while the base layer is encoded by H.261, the enhancement layer is encoded by the 3-D SBC technique. From the simulation results, the proposed technique shows about 1 dB PSNR gain over the conventional layered coding techniques, including the twin-H.261, even under heavy ATM network loading.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"56 1","pages":"1301-1304 vol.2"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88010765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621500
Bum-Sik Kim, L. Kim
All digital DLL is designed for synchronization of high frequency VLSI system with low power consumption and small area. Two new design method features are presented. First, the operation is described by Verilog HDL and verified. Second, using the circuit level simulations and optimizations, low power consumption and high speed is achieved. The simulation results show that the power consumption is 3.2 mW at 100 MHz, 2.0 V supply voltage without driver buffers; the area is 0.1 mm/sup 2/ and the proposed DLL has no jitter.
{"title":"A low power 100 MHz all digital delay-locked loop","authors":"Bum-Sik Kim, L. Kim","doi":"10.1109/ISCAS.1997.621500","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621500","url":null,"abstract":"All digital DLL is designed for synchronization of high frequency VLSI system with low power consumption and small area. Two new design method features are presented. First, the operation is described by Verilog HDL and verified. Second, using the circuit level simulations and optimizations, low power consumption and high speed is achieved. The simulation results show that the power consumption is 3.2 mW at 100 MHz, 2.0 V supply voltage without driver buffers; the area is 0.1 mm/sup 2/ and the proposed DLL has no jitter.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"45 1","pages":"1820-1823 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88103762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621458
Taekyoon Ahn, Kiyoung Choi
We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup.
{"title":"VHDL simulation acceleration using specialized functions","authors":"Taekyoon Ahn, Kiyoung Choi","doi":"10.1109/ISCAS.1997.621458","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621458","url":null,"abstract":"We present a new approach to speeding up VHDL simulation. In this approach, the simulation code is generated with routines for unused VHDL features stripped off. The VHDL simulator optimized in this way runs faster when the design is described mostly with simple constructs and expressions. We prepare multiple functions for each task in the simulation process. Each function is pre-optimized for each possible case. When a design is compiled and the simulation code is generated, we select functions that best fit with the design. With this approach and with several other optimization techniques, we obtained about twofold speedup.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"4 1","pages":"1684-1687 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88202493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.621434
Shin-ya Furasawa, V.G. Mashnyaga, K. Tamaru
This paper presents a new approach for time constrained synthesis of pipelined data-paths. The method improves on previous work in the synthesis by being able to integrate clock optimization and resource sharing with functional pipelining and library mapping. Experiments on several benchmarks show that such formulation ensures efficient exploration of delay-area trade offs and results in circuit structure with a near optimal area under given throughput constraint.
{"title":"A combined hardware selection, resource sharing and clock optimization for pipelined data-path synthesis","authors":"Shin-ya Furasawa, V.G. Mashnyaga, K. Tamaru","doi":"10.1109/ISCAS.1997.621434","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.621434","url":null,"abstract":"This paper presents a new approach for time constrained synthesis of pipelined data-paths. The method improves on previous work in the synthesis by being able to integrate clock optimization and resource sharing with functional pipelining and library mapping. Experiments on several benchmarks show that such formulation ensures efficient exploration of delay-area trade offs and results in circuit structure with a near optimal area under given throughput constraint.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"36 1","pages":"1588-1591 vol.3"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88386465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-06-09DOI: 10.1109/ISCAS.1997.612900
W. Pan, B. Lin
Conventional fiber optic interferometers are playing an important role as sensors for their high sensitivity, fast response and simple construction. However, they face the challenges of temperature stability and sensitive lead in/out disturbance. In this paper, we proposed a novel two-core fiber interferometric (TCFI) strain sensor, which utilizes the strain induced phase difference between the two cores for strain measurement and a polarization effect to obtain high S/N ratio and stability; also, we give experimental results. The experimental results are generally in accordance with the theory. Interferometric sensors of such kinds may have wide applications in the future.
{"title":"Two-core fiber interferometric strain sensor","authors":"W. Pan, B. Lin","doi":"10.1109/ISCAS.1997.612900","DOIUrl":"https://doi.org/10.1109/ISCAS.1997.612900","url":null,"abstract":"Conventional fiber optic interferometers are playing an important role as sensors for their high sensitivity, fast response and simple construction. However, they face the challenges of temperature stability and sensitive lead in/out disturbance. In this paper, we proposed a novel two-core fiber interferometric (TCFI) strain sensor, which utilizes the strain induced phase difference between the two cores for strain measurement and a polarization effect to obtain high S/N ratio and stability; also, we give experimental results. The experimental results are generally in accordance with the theory. Interferometric sensors of such kinds may have wide applications in the future.","PeriodicalId":68559,"journal":{"name":"电路与系统学报","volume":"73 1","pages":"2773-2776 vol.4"},"PeriodicalIF":0.0,"publicationDate":"1997-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86148447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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