Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487103
Brennan Kelly, Julia Zhang, Luke Chen
Advancements in semiconductor technology present new challenges in electric machine construction, operation and control. Silicon carbide (SiC)-based power electronics are becoming the new standard for high-power consumer and commercial devices, and are implemented in technologies such as power inverters, converters and rectifiers. This paper focuses on the effects of inverter drives for traction motors in electric vehicles with high dV/dt rates on bar-wound machine windings, including the expected impacts on insulation materials under prolonged periods of high voltage stress. A simulation model was constructed using finite element analysis, the results of which were validated with experimental results using a commercially available SiC inverter and traction motor. The results presented in the analysis pertain mostly to a single phase of a three-phase IPMSM in order to reduce simulation and testing complexity and runtime, so that the accuracy of the simulation in relation to the physical model can be demonstrated before proceeding to three-phase analysis. Some three-phase testing and analysis is also included. Correlation has been established between the preliminary simulation results and experimental data. It is proven that as DC bus voltages increase with the capabilities of SiC devices, the voltage stresses inside the stator windings approach levels which could cause partial discharge and premature insulation degradation in existing stator designs.
{"title":"Bar-Wound Machine Voltage Stress: a Method for 2D FE Modeling and Testing","authors":"Brennan Kelly, Julia Zhang, Luke Chen","doi":"10.1109/APEC42165.2021.9487103","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487103","url":null,"abstract":"Advancements in semiconductor technology present new challenges in electric machine construction, operation and control. Silicon carbide (SiC)-based power electronics are becoming the new standard for high-power consumer and commercial devices, and are implemented in technologies such as power inverters, converters and rectifiers. This paper focuses on the effects of inverter drives for traction motors in electric vehicles with high dV/dt rates on bar-wound machine windings, including the expected impacts on insulation materials under prolonged periods of high voltage stress. A simulation model was constructed using finite element analysis, the results of which were validated with experimental results using a commercially available SiC inverter and traction motor. The results presented in the analysis pertain mostly to a single phase of a three-phase IPMSM in order to reduce simulation and testing complexity and runtime, so that the accuracy of the simulation in relation to the physical model can be demonstrated before proceeding to three-phase analysis. Some three-phase testing and analysis is also included. Correlation has been established between the preliminary simulation results and experimental data. It is proven that as DC bus voltages increase with the capabilities of SiC devices, the voltage stresses inside the stator windings approach levels which could cause partial discharge and premature insulation degradation in existing stator designs.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89077199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487194
Dominik Koch, Julian Weimer, Mathias C. J. Weiser, Jan Hueckelheim, I. Kallfass
In this work experimental and simulative proof of a concept for paralleling low voltage and high current Gallium Nitride (GaN) transistors each with a distinct gate booster is presented. For both high-side (HS) and low-side (LS), two 100V 5mΩ normally-off GaN-HEMTs are operated with a driver, which offers separate paths for turn-on and turn-off. In combination with the Kelvin source a minimal gate-loop inductance and stable switching operation is achieved. The HS and LS signals are provided by an isolated half-bridge driver with ultra-low jitter and identical PCB path lengths to ensure equal propagation delay. The half-bridge with paralleled GaN-HEMTs, which is approved by full-wave S-parameter extraction in combination with a comprehensive thermal simulation and a transient simulation based on a physical GaN model, is operated in a 300kHz48V-to-24V buck converter operation up to 54A output current with an overall efficiency of above 95%. The output power of the converter is mainly limited by the thermal performance of the packaging and the PCB and the single gate-contact of the transistors, which is reducing the degrees of freedoms in the layout and introducing significant common source and parasitic inductances.
{"title":"Gate Driver Concept for Parallel Operation of Low-Voltage High-Current GaN Power Transistors for Mild-Hybrid Applications","authors":"Dominik Koch, Julian Weimer, Mathias C. J. Weiser, Jan Hueckelheim, I. Kallfass","doi":"10.1109/APEC42165.2021.9487194","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487194","url":null,"abstract":"In this work experimental and simulative proof of a concept for paralleling low voltage and high current Gallium Nitride (GaN) transistors each with a distinct gate booster is presented. For both high-side (HS) and low-side (LS), two 100V 5mΩ normally-off GaN-HEMTs are operated with a driver, which offers separate paths for turn-on and turn-off. In combination with the Kelvin source a minimal gate-loop inductance and stable switching operation is achieved. The HS and LS signals are provided by an isolated half-bridge driver with ultra-low jitter and identical PCB path lengths to ensure equal propagation delay. The half-bridge with paralleled GaN-HEMTs, which is approved by full-wave S-parameter extraction in combination with a comprehensive thermal simulation and a transient simulation based on a physical GaN model, is operated in a 300kHz48V-to-24V buck converter operation up to 54A output current with an overall efficiency of above 95%. The output power of the converter is mainly limited by the thermal performance of the packaging and the PCB and the single gate-contact of the transistors, which is reducing the degrees of freedoms in the layout and introducing significant common source and parasitic inductances.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85940642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487072
Xingxuan Huang, Shiqi Ji, Cheng Nie, Dingrui Li, Min Lin, L. Tolbert, Fred Wang, William Giewont
This paper provides an analysis of the desat protection for high voltage (>3.3 kV) SiC MOSFETs from the perspective of noise immunity. The high positive dv/dt with long voltage rise time generated by high voltage SiC MOSFETs is identified as a major threat to noise immunity of the desat protection circuitry. The impact of numerous influencing factors is analyzed, such as parasitic inductance, damping resistance, and clamping impedance. In some cases, small parasitic capacitances (<0.01 pF) between the drain terminal with high dv/dt and protection circuitry dominate the noise immunity of the desat protection circuitry with high-impedance voltage divider. The noise immunity margin is derived quantitatively to guide the noise immunity improvement. Different noise immunity enhancement methods are developed and validated with experimental results, including adding a shielding layer, reducing clamping impedance, and decreasing voltage divider impedance.
本文从抗扰度的角度分析了高压(>3.3 kV) SiC mosfet的防沙保护。高电压SiC mosfet产生的高正dv/dt和长电压上升时间是对土壤保护电路抗噪性的主要威胁。分析了寄生电感、阻尼电阻、箝位阻抗等多种影响因素的影响。在某些情况下，高dv/dt的漏极与保护电路之间的小寄生电容(<0.01 pF)决定了高阻抗分压器保护电路的抗噪能力。定量导出了噪声抗扰度，指导了噪声抗扰度的提高。提出了增加屏蔽层、减小箝位阻抗、减小分压器阻抗等增强抗扰度的方法，并通过实验验证了方法的有效性。
{"title":"Noise Immunity of Desat Protection Circuitry for High Voltage SiC MOSFETs with High dv/dt","authors":"Xingxuan Huang, Shiqi Ji, Cheng Nie, Dingrui Li, Min Lin, L. Tolbert, Fred Wang, William Giewont","doi":"10.1109/APEC42165.2021.9487072","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487072","url":null,"abstract":"This paper provides an analysis of the desat protection for high voltage (>3.3 kV) SiC MOSFETs from the perspective of noise immunity. The high positive dv/dt with long voltage rise time generated by high voltage SiC MOSFETs is identified as a major threat to noise immunity of the desat protection circuitry. The impact of numerous influencing factors is analyzed, such as parasitic inductance, damping resistance, and clamping impedance. In some cases, small parasitic capacitances (<0.01 pF) between the drain terminal with high dv/dt and protection circuitry dominate the noise immunity of the desat protection circuitry with high-impedance voltage divider. The noise immunity margin is derived quantitatively to guide the noise immunity improvement. Different noise immunity enhancement methods are developed and validated with experimental results, including adding a shielding layer, reducing clamping impedance, and decreasing voltage divider impedance.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85956653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487339
Vinay Rathore, K. Rajashekara, Anindya Ray, L. A. G. Rodriguez, Jacob A. Mueller
This paper presents a new high gain, multilevel, bidirectional DC-DC converter for interfacing battery energy storage systems (BESS) with the distribution grid. The proposed topology employs a current-fed structure on the low-voltage (LV) BESS side to obtain high voltage gain during battery-to-grid mode of operation without requiring a large turns ratio isolation transformer. The high-voltage (HV) side of the converter is a voltage-doubler network comprising two half-bridge circuits with an intermediary bidirectional switch that re-configures the two bridges in series connection to enhance the boost ratio. A seamless commutation of the transformer leakage inductor current is ensured by the phase-shift modulation of HV side devices. The modulating duty cycle of the intermediary bidirectional devices generates a multilevel voltage of twice the switching frequency at the grid-side dc link, which significantly reduces the filter size. The presented modulation strategy ensures zero current switching (ZCS) of the LV devices and zero voltage switching (ZVS) of the HV devices to achieve a high power conversion efficiency. Design and operation of the proposed converter is explained with modal analysis, and further verified by detailed simulation results.
{"title":"A Current-fed High Gain Multilevel DC-DC Converter for BESS Grid Integration Applications","authors":"Vinay Rathore, K. Rajashekara, Anindya Ray, L. A. G. Rodriguez, Jacob A. Mueller","doi":"10.1109/APEC42165.2021.9487339","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487339","url":null,"abstract":"This paper presents a new high gain, multilevel, bidirectional DC-DC converter for interfacing battery energy storage systems (BESS) with the distribution grid. The proposed topology employs a current-fed structure on the low-voltage (LV) BESS side to obtain high voltage gain during battery-to-grid mode of operation without requiring a large turns ratio isolation transformer. The high-voltage (HV) side of the converter is a voltage-doubler network comprising two half-bridge circuits with an intermediary bidirectional switch that re-configures the two bridges in series connection to enhance the boost ratio. A seamless commutation of the transformer leakage inductor current is ensured by the phase-shift modulation of HV side devices. The modulating duty cycle of the intermediary bidirectional devices generates a multilevel voltage of twice the switching frequency at the grid-side dc link, which significantly reduces the filter size. The presented modulation strategy ensures zero current switching (ZCS) of the LV devices and zero voltage switching (ZVS) of the HV devices to achieve a high power conversion efficiency. Design and operation of the proposed converter is explained with modal analysis, and further verified by detailed simulation results.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86444761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487400
Haibin Song, Daofei Xu, A. Zhang
LLC convertor is widely used because of ZVS operation of primary switches and ZCS operation of secondary switches. These features make it suitable for high fs design to cater for the miniaturization trend of switching mode power supply (SMPS). ZVS operation of the primary switches is critical for high fs design to achieve high efficiency. Traditional analysis of the ZVS condition for LLC converter is not accurate enough for high fs design. This paper gives a detail analysis on the operation modes during the dead time interval. An accurate ZVS condition is derived based on the analysis. The verification of the theoretical analysis has been carried out with simulation and a half-bridge(HB) LLC prototype.
{"title":"Re-analysis on ZVS Condition for LLC Converter","authors":"Haibin Song, Daofei Xu, A. Zhang","doi":"10.1109/APEC42165.2021.9487400","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487400","url":null,"abstract":"LLC convertor is widely used because of ZVS operation of primary switches and ZCS operation of secondary switches. These features make it suitable for high fs design to cater for the miniaturization trend of switching mode power supply (SMPS). ZVS operation of the primary switches is critical for high fs design to achieve high efficiency. Traditional analysis of the ZVS condition for LLC converter is not accurate enough for high fs design. This paper gives a detail analysis on the operation modes during the dead time interval. An accurate ZVS condition is derived based on the analysis. The verification of the theoretical analysis has been carried out with simulation and a half-bridge(HB) LLC prototype.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81805109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487421
Saurav Dey, T. Bhattacharya
A modular dc-dc converter topology is discussed in this paper which provides an economic solution on existing modular multilevel converter (MMC) based dc-dc converters for forming a hybrid interlink in high voltage dc (HVdc) network. The number of semiconductor devices is optimized by using hybrid MMC to minimize losses and at the same time ensure dc fault clearance capability. The topology is demonstrated for three modes of operation of the dc-dc converter such as bipolar VSC to bipolar LCC, bipolar VSC to monopolar LCC and monopolar VSC to bipolar LCC dc buses with the help of simulation results in Matlab/Simulink.
{"title":"A Hybrid Modular DC-DC Converter Topology for Hybrid Interlink in HVDC","authors":"Saurav Dey, T. Bhattacharya","doi":"10.1109/APEC42165.2021.9487421","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487421","url":null,"abstract":"A modular dc-dc converter topology is discussed in this paper which provides an economic solution on existing modular multilevel converter (MMC) based dc-dc converters for forming a hybrid interlink in high voltage dc (HVdc) network. The number of semiconductor devices is optimized by using hybrid MMC to minimize losses and at the same time ensure dc fault clearance capability. The topology is demonstrated for three modes of operation of the dc-dc converter such as bipolar VSC to bipolar LCC, bipolar VSC to monopolar LCC and monopolar VSC to bipolar LCC dc buses with the help of simulation results in Matlab/Simulink.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84723029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487208
Edgaras Mickus, Trong Tue Vu
Modern power converters are expected to have high efficiency and features like datalogging. This typically results in a design with a digital controller implemented on the secondary side, which means having to drive transistors across the galvanic isolation barrier. The most common approaches are a) Bulky magnetic drive with many turns of triple-isolated wire; b) Compact but costly coreless transformer ICs that also require local powering; This work presents an alternative approach, which optimizes size and cost without compromising performance in traditional applications, intended for driving a complementary pair of MOSFETs like in Half-Bridge LLC converters.
{"title":"Low-cost Compact Approach to Reinforced Isolated Drive for LLC Converters","authors":"Edgaras Mickus, Trong Tue Vu","doi":"10.1109/APEC42165.2021.9487208","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487208","url":null,"abstract":"Modern power converters are expected to have high efficiency and features like datalogging. This typically results in a design with a digital controller implemented on the secondary side, which means having to drive transistors across the galvanic isolation barrier. The most common approaches are a) Bulky magnetic drive with many turns of triple-isolated wire; b) Compact but costly coreless transformer ICs that also require local powering; This work presents an alternative approach, which optimizes size and cost without compromising performance in traditional applications, intended for driving a complementary pair of MOSFETs like in Half-Bridge LLC converters.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90748552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487080
J. Baek, Youssef Elasser, Minjie Chen
This paper presents a merged-two-stage hybrid switched-capacitor point-of-load converter with 3D-embedded coupled inductors, vertical power delivery, and LEGO-PoL architecture. By merging a switched-capacitor circuit with a multiphase buck circuit, the 3D LEGO-PoL converter offers reduced device stress and minimized magnetic size, and enables soft switching, soft charging, voltage balancing, and current sharing. A prototype converter with 3D embedded coupled inductors is designed to deliver power vertically from the motherboard to microprocessors with minimized 2D area. A 675 W, 48 V to 1.5 V/450 A hybrid converter with a peak efficiency of 93.3%, full load efficiency of 87.2%, current density of 0.57 A/mm2, and power density of 688 W/in3 was built and tested to verify the effectiveness of the hybrid converter architecture with 3D embedded coupled inductors and vertical power delivery.
{"title":"3D LEGO-PoL: A 93.3% Efficient 48V-1.5V 450A Merged-Two-Stage Hybrid Switched-Capacitor Converter with 3D Vertical Coupled Inductors","authors":"J. Baek, Youssef Elasser, Minjie Chen","doi":"10.1109/APEC42165.2021.9487080","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487080","url":null,"abstract":"This paper presents a merged-two-stage hybrid switched-capacitor point-of-load converter with 3D-embedded coupled inductors, vertical power delivery, and LEGO-PoL architecture. By merging a switched-capacitor circuit with a multiphase buck circuit, the 3D LEGO-PoL converter offers reduced device stress and minimized magnetic size, and enables soft switching, soft charging, voltage balancing, and current sharing. A prototype converter with 3D embedded coupled inductors is designed to deliver power vertically from the motherboard to microprocessors with minimized 2D area. A 675 W, 48 V to 1.5 V/450 A hybrid converter with a peak efficiency of 93.3%, full load efficiency of 87.2%, current density of 0.57 A/mm2, and power density of 688 W/in3 was built and tested to verify the effectiveness of the hybrid converter architecture with 3D embedded coupled inductors and vertical power delivery.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90983319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487046
Yu-Chen Liu, Chen Chen, Kai-De Chen, Yong-Long Syu, Ching-Chia Chen, Kang Liu, Xingyu Chen, H. Chiu
In this study, an LLC resonant converter equipped with an adjustable leakage inductance integrated transformer is proposed and applied to high-power adapters. To achieve high efficiency and power density, the magnetic circuit was increased by substituting the resonant inductor with an adjustable leakage inductance integrated transformer, and a novel core structure was designed to reduce copper loss. To further reduce the core loss and copper loss of the transformer, the core size was analyzed using a parametric technique. Finally, the total loss and physical footprint of the transformer were compared to select the most effective design point as the final design. The FEA 3D simulation was employed to verify the function of the transformer. An integrated transformer with adjustable leakage inductance replaced the resonant inductor in LLC resonant converters. Finally, a resonant converter was achieved with a switching frequency operating at 1 MHz, input voltage of 380 V, output voltage of 19 V, output power of 190 W, power density of 400 W/in3, and maximum efficiency of 94.3%.
{"title":"Design and Implementation of an Integrated Planar Transformer for High-Frequency LLC Resonant Converters","authors":"Yu-Chen Liu, Chen Chen, Kai-De Chen, Yong-Long Syu, Ching-Chia Chen, Kang Liu, Xingyu Chen, H. Chiu","doi":"10.1109/APEC42165.2021.9487046","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487046","url":null,"abstract":"In this study, an LLC resonant converter equipped with an adjustable leakage inductance integrated transformer is proposed and applied to high-power adapters. To achieve high efficiency and power density, the magnetic circuit was increased by substituting the resonant inductor with an adjustable leakage inductance integrated transformer, and a novel core structure was designed to reduce copper loss. To further reduce the core loss and copper loss of the transformer, the core size was analyzed using a parametric technique. Finally, the total loss and physical footprint of the transformer were compared to select the most effective design point as the final design. The FEA 3D simulation was employed to verify the function of the transformer. An integrated transformer with adjustable leakage inductance replaced the resonant inductor in LLC resonant converters. Finally, a resonant converter was achieved with a switching frequency operating at 1 MHz, input voltage of 380 V, output voltage of 19 V, output power of 190 W, power density of 400 W/in3, and maximum efficiency of 94.3%.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89375912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487253
Zhao Yuan, A. Emon, Zhongjing Wang, Hongwu Peng, B. Narayanasamy, M. Hassan, Yalin Wang, A. Deshpande, F. Luo
This paper presents a prototype of a 450 kVA inverter system by using 3-level T-type neutral-point-clamped converter (3L-TNPC). The prototype features high-power density and high-efficiency design. The design highlights an improved busbar structure, which achieves lower stray inductance than published literature of 3-level converters with limited temperature rise. The improved power-loop design provides sufficient room for accelerating switching speed. Over 67.7% of switching loss reduction is achieved by choosing optimal gate resistance (1 Ω). The paper also focuses on compact integration of signal sensing, conditioning circuits, and controller circuits to improve power density. The design strategy for the sensing system is discussed to optimize the trade-off between compact sensing and noise distortion. As a result, the converter reaches the power density of 26.6 kW/L. The peak efficiency of 99.47% is measured at 266 kVA under 70 kHz switching frequency.
{"title":"A Three-phase 450 kVA SiC-MOSFET Based Inverter With High Efficiency and High Power Density By Using 3L-TNPC","authors":"Zhao Yuan, A. Emon, Zhongjing Wang, Hongwu Peng, B. Narayanasamy, M. Hassan, Yalin Wang, A. Deshpande, F. Luo","doi":"10.1109/APEC42165.2021.9487253","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487253","url":null,"abstract":"This paper presents a prototype of a 450 kVA inverter system by using 3-level T-type neutral-point-clamped converter (3L-TNPC). The prototype features high-power density and high-efficiency design. The design highlights an improved busbar structure, which achieves lower stray inductance than published literature of 3-level converters with limited temperature rise. The improved power-loop design provides sufficient room for accelerating switching speed. Over 67.7% of switching loss reduction is achieved by choosing optimal gate resistance (1 Ω). The paper also focuses on compact integration of signal sensing, conditioning circuits, and controller circuits to improve power density. The design strategy for the sensing system is discussed to optimize the trade-off between compact sensing and noise distortion. As a result, the converter reaches the power density of 26.6 kW/L. The peak efficiency of 99.47% is measured at 266 kVA under 70 kHz switching frequency.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87257370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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