Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487301
Roderick S. Bayliss, Rachel S. Yang, Alex J. Hanson, C. Sullivan, D. Perreault
Radio-Frequency (RF) power inductors are critical to many applications such as communications, RF heating, and plasma generation for semiconductor processing. Their high loss and large size can often be major contributors to the overall system size and loss. Inductors for high frequency and high power (e.g., tens of MHz and hundreds of watts and above) have traditionally been implemented as air-core solenoids to avoid high-frequency core loss. These designs have more turns than magnetic-core inductors and thus high copper loss. We propose a magnetic-core inductor design approach that leverages NiZn ferrites with low loss at RF, distributed gaps and field balancing to achieve improved performance at tens of MHz and at hundreds of watts and above. We demonstrate this approach with a 13.56 MHz, 500 nH, 80 Apk magnetic-core inductor design for a plasma generation matching network that achieves a quality factor of >1800 in simulation and >1100 experimentally. Additionally, we describe the difficulties in experimentally measuring inductor quality factors with very high current and very low loss at high frequency.
{"title":"Design, Implementation, and Evaluation of High-Efficiency High-Power Radio-Frequency Inductors","authors":"Roderick S. Bayliss, Rachel S. Yang, Alex J. Hanson, C. Sullivan, D. Perreault","doi":"10.1109/APEC42165.2021.9487301","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487301","url":null,"abstract":"Radio-Frequency (RF) power inductors are critical to many applications such as communications, RF heating, and plasma generation for semiconductor processing. Their high loss and large size can often be major contributors to the overall system size and loss. Inductors for high frequency and high power (e.g., tens of MHz and hundreds of watts and above) have traditionally been implemented as air-core solenoids to avoid high-frequency core loss. These designs have more turns than magnetic-core inductors and thus high copper loss. We propose a magnetic-core inductor design approach that leverages NiZn ferrites with low loss at RF, distributed gaps and field balancing to achieve improved performance at tens of MHz and at hundreds of watts and above. We demonstrate this approach with a 13.56 MHz, 500 nH, 80 Apk magnetic-core inductor design for a plasma generation matching network that achieves a quality factor of >1800 in simulation and >1100 experimentally. Additionally, we describe the difficulties in experimentally measuring inductor quality factors with very high current and very low loss at high frequency.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"36 1","pages":"881-888"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87191897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487040
Wenkang Huang, D. Clavette, Mudassar Khatib
This paper presents a current-mirror sensing scheme for high-current trench MOSFETs in synchronous buck converters and implements in a three-die PQFN package capable of delivering 70-A current per phase. Current signal accuracy is critical in high-current multiphase converters that power CPUs, GPUs, DDR memories, and FPGAs in high-performance computers and artificial intelligence systems, since the current information is used not only in optimization of computer system performance and adaptive voltage positioning but also for current sharing between multiple phases and converter over-current protection. Inductor DCR and MOSFET RDS(on) current sensing methods have been used in synchronous buck converters for more than a decade, but the current sensing accuracy is limited to +/-10% and +/-5% respectively and becomes even worse when application conditions vary in wider ranges. Higher current reporting accuracy of the MOSFET current mirror sensing is experimentally verified using multiple synchronous buck converter boards, which are built to measure current sensing error of each power stage and to determine distribution of system current reporting tolerance. Smaller than +/-3%, 3-sigma current error is achieved over wide application ranges of ambient temperature and MOSFET gate drive voltage.
{"title":"A More Accurate Power MOSFET Current Mirror Sensing Scheme in Synchronous Buck Converters","authors":"Wenkang Huang, D. Clavette, Mudassar Khatib","doi":"10.1109/APEC42165.2021.9487040","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487040","url":null,"abstract":"This paper presents a current-mirror sensing scheme for high-current trench MOSFETs in synchronous buck converters and implements in a three-die PQFN package capable of delivering 70-A current per phase. Current signal accuracy is critical in high-current multiphase converters that power CPUs, GPUs, DDR memories, and FPGAs in high-performance computers and artificial intelligence systems, since the current information is used not only in optimization of computer system performance and adaptive voltage positioning but also for current sharing between multiple phases and converter over-current protection. Inductor DCR and MOSFET RDS(on) current sensing methods have been used in synchronous buck converters for more than a decade, but the current sensing accuracy is limited to +/-10% and +/-5% respectively and becomes even worse when application conditions vary in wider ranges. Higher current reporting accuracy of the MOSFET current mirror sensing is experimentally verified using multiple synchronous buck converter boards, which are built to measure current sensing error of each power stage and to determine distribution of system current reporting tolerance. Smaller than +/-3%, 3-sigma current error is achieved over wide application ranges of ambient temperature and MOSFET gate drive voltage.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"27 1","pages":"506-512"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87241257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487053
Yu-Chen Liu, Meng-Chi Tsai, Ying-Jiun Chen, Katherine A. Kim, Chen Chen, N. A. Dung
This paper proposes the design and implementation of an inductor with a stepped air-gap for a buck converter with improved feedback control. Typically, a power converter needs to maintain stable operation during any load transient. When designing the compensator for a converter according to the traditional method for continuous conduction mode (CCM), the same compensator is employed from light load to full load, which leads to poor response at some operating points, especially at light load. To achieve a better system response, a stepped air-gap inductor is proposed to increase the inductance at light load, which is analyzed and compared with a traditional inductor. The proposed stepped air-gap inductor reduces the influence of the magnetic flux leakage on the winding. The effect of having two different inductance values on the controller design is discussed, and the conditions for discontinuous conduction mode (DCM) at light load with the stepped air-gap inductor are outlined. A 48-V to 12-V buck converter rated for 60 W is built and tested to verify the proposed stepped air-gap inductor. With the proposed stepped air-gap inductor, experimental results show that undershoot and overshoot were improved 50% and settling time was decreased to 20% and 30% during light-to-full load transients, compared to the traditional inductor. Hence, the proposed stepped air-gap inductor can effectively improve system response.
{"title":"Design and Implementation of a Stepped Air-Gap Inductor for Buck Converters","authors":"Yu-Chen Liu, Meng-Chi Tsai, Ying-Jiun Chen, Katherine A. Kim, Chen Chen, N. A. Dung","doi":"10.1109/APEC42165.2021.9487053","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487053","url":null,"abstract":"This paper proposes the design and implementation of an inductor with a stepped air-gap for a buck converter with improved feedback control. Typically, a power converter needs to maintain stable operation during any load transient. When designing the compensator for a converter according to the traditional method for continuous conduction mode (CCM), the same compensator is employed from light load to full load, which leads to poor response at some operating points, especially at light load. To achieve a better system response, a stepped air-gap inductor is proposed to increase the inductance at light load, which is analyzed and compared with a traditional inductor. The proposed stepped air-gap inductor reduces the influence of the magnetic flux leakage on the winding. The effect of having two different inductance values on the controller design is discussed, and the conditions for discontinuous conduction mode (DCM) at light load with the stepped air-gap inductor are outlined. A 48-V to 12-V buck converter rated for 60 W is built and tested to verify the proposed stepped air-gap inductor. With the proposed stepped air-gap inductor, experimental results show that undershoot and overshoot were improved 50% and settling time was decreased to 20% and 30% during light-to-full load transients, compared to the traditional inductor. Hence, the proposed stepped air-gap inductor can effectively improve system response.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"48 1","pages":"875-880"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90625359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487330
Bahlakoana Mabetha, Yanqiao Li, Benjamin L. Dobbins, J. Stauth
This paper explores the design and implementation of a cm-scale switched capacitor (SC) converter with a kilovolt range output, such as could be used for driving electrostatic, piezoelectric, or dielectric elastomer electromechanical transducers. The design uses a two-stage power conversion approach: a first stage, two-channel series parallel (SP) converter boosts a low-voltage input (e.g. stacked Li-ion cells) by 16x; a second stage symmetric ladder converter boosts the differential series-parallel output by ~10x, providing capabilities to reach voltages in the kV range. The first stage uses a pseudo-soft-charging switching scheme to reduce charge sharing loss and recover energy in parasitic (e.g. bottom-plate) capacitances without the use of an inductor. The implementation optimizes the use of discrete components and represents a scalable design while maintaining a small form factor. The first stage integrated circuit is implemented in 650V SOI CMOS with a die area of 10 mm2; the second stage printed circuit board design uses discrete components with board area < 50 mm2. The converter provides conversion ratio VCR up to 150, peak efficiency ~ 80%, and output power up to 50 mW. Efficient regulation is demonstrated by using a mixture of frequency and digital adjustment of the first stage switching sequence.
本文探讨了一种具有千伏输出范围的厘米级开关电容(SC)变换器的设计和实现，例如可用于驱动静电，压电或介电弹性体机电换能器。该设计采用两级功率转换方法:第一级，双通道串并联(SP)转换器将低压输入(例如堆叠的锂离子电池)提高16倍;第二级对称梯形变换器将差分串并联输出提高约10倍，提供达到kV范围内电压的能力。第一阶段使用伪软充电开关方案，以减少电荷共享损失，并在寄生(如底板)电容中回收能量，而无需使用电感。该实现优化了离散组件的使用，并在保持小尺寸的同时代表了可扩展的设计。第一级集成电路采用650V SOI CMOS实现，芯片面积为10 mm2;第二阶段印刷电路板设计使用电路板面积< 50 mm2的分立元件。转换器提供高达150的转化率VCR，峰值效率~ 80%，输出功率高达50 mW。有效的调节被证明是使用混合频率和数字调整的第一级开关序列。
{"title":"Analysis and Implementation of a cm-Scale Switched Capacitor Converter for Low Power, Kilovolt-Range Applications","authors":"Bahlakoana Mabetha, Yanqiao Li, Benjamin L. Dobbins, J. Stauth","doi":"10.1109/APEC42165.2021.9487330","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487330","url":null,"abstract":"This paper explores the design and implementation of a cm-scale switched capacitor (SC) converter with a kilovolt range output, such as could be used for driving electrostatic, piezoelectric, or dielectric elastomer electromechanical transducers. The design uses a two-stage power conversion approach: a first stage, two-channel series parallel (SP) converter boosts a low-voltage input (e.g. stacked Li-ion cells) by 16x; a second stage symmetric ladder converter boosts the differential series-parallel output by ~10x, providing capabilities to reach voltages in the kV range. The first stage uses a pseudo-soft-charging switching scheme to reduce charge sharing loss and recover energy in parasitic (e.g. bottom-plate) capacitances without the use of an inductor. The implementation optimizes the use of discrete components and represents a scalable design while maintaining a small form factor. The first stage integrated circuit is implemented in 650V SOI CMOS with a die area of 10 mm2; the second stage printed circuit board design uses discrete components with board area < 50 mm2. The converter provides conversion ratio VCR up to 150, peak efficiency ~ 80%, and output power up to 50 mW. Efficient regulation is demonstrated by using a mixture of frequency and digital adjustment of the first stage switching sequence.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"45 1","pages":"208-213"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90638914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487107
Tyler McGrew, V. Sysoeva, Chi-Hao Cheng, Mark Scott
Non-invasive condition monitoring techniques have been developed for various electrical components within different power electronic topologies in order to increase reliability and decrease maintenance costs for these systems. DC-link capacitors are a component of particular attention for these condition monitoring systems due to their outsized effect on cost, size, and failure rate for power electronic converters. A non-invasive, online condition monitoring system is proposed in this paper which estimates the health of the MPPF DC-link capacitor within a 3-phase inverter. Current measurements are collected using a current transducer (CT) on the DC-bus, and a novel condition monitoring method of time-frequency image classification is used to analyze high frequency electromagnetic interference (EMI) content around 15-43 MHz. The proposed system uses a continuous wavelet transform (CWT), convolutional neural network (CNN), and Hidden Markov Model (HMM) to classify DC-link capacitor health into one of five stages with 99.9% accuracy.
{"title":"Condition Monitoring of DC-Link Capacitors Using Hidden Markov Model Supported-Convolutional Neural Network","authors":"Tyler McGrew, V. Sysoeva, Chi-Hao Cheng, Mark Scott","doi":"10.1109/APEC42165.2021.9487107","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487107","url":null,"abstract":"Non-invasive condition monitoring techniques have been developed for various electrical components within different power electronic topologies in order to increase reliability and decrease maintenance costs for these systems. DC-link capacitors are a component of particular attention for these condition monitoring systems due to their outsized effect on cost, size, and failure rate for power electronic converters. A non-invasive, online condition monitoring system is proposed in this paper which estimates the health of the MPPF DC-link capacitor within a 3-phase inverter. Current measurements are collected using a current transducer (CT) on the DC-bus, and a novel condition monitoring method of time-frequency image classification is used to analyze high frequency electromagnetic interference (EMI) content around 15-43 MHz. The proposed system uses a continuous wavelet transform (CWT), convolutional neural network (CNN), and Hidden Markov Model (HMM) to classify DC-link capacitor health into one of five stages with 99.9% accuracy.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"62 1","pages":"2323-2330"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85666671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487060
S. B. Vilsen, D. Stroe
Accurate modelling of the dynamic behaviour of Lithium-ion (Li-ion) batteries is important in a wide range of scenarios from the determination of appropriate battery-pack size, to battery balancing and state estimation in battery management systems. The prevailing methods used in voltage prediction are the equivalent electrical circuit (EEC) models. EEC models account for the change in the voltage by a series of resistor capacitor networks to mimic the internal resistance of a battery. Thus, given a change in current the EEC models create an appropriate change in the voltage. The downside is that the parameters of the model needs to be fully characterised, across the entire range of usage and life of the battery. This is both time consuming and expensive. In this paper, a linear auto-regressive (AR) process is proposed to account for the short-term dynamic behaviour of the battery cell, allowing for accurate prediction of the voltage given other measurable parameters such as current and temperature. After conducting a sensitivity analysis on the size of the sequence needed to train the AR model, it was found that less than a days worth of raw measurements data is enough to offer a better voltage prediction than a traditional EEC model (the root mean square errors of the two considered voltage estimation approaches were 0.00157 and 0.0133 V, respectively).
{"title":"An auto-regressive model for battery voltage prediction","authors":"S. B. Vilsen, D. Stroe","doi":"10.1109/APEC42165.2021.9487060","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487060","url":null,"abstract":"Accurate modelling of the dynamic behaviour of Lithium-ion (Li-ion) batteries is important in a wide range of scenarios from the determination of appropriate battery-pack size, to battery balancing and state estimation in battery management systems. The prevailing methods used in voltage prediction are the equivalent electrical circuit (EEC) models. EEC models account for the change in the voltage by a series of resistor capacitor networks to mimic the internal resistance of a battery. Thus, given a change in current the EEC models create an appropriate change in the voltage. The downside is that the parameters of the model needs to be fully characterised, across the entire range of usage and life of the battery. This is both time consuming and expensive. In this paper, a linear auto-regressive (AR) process is proposed to account for the short-term dynamic behaviour of the battery cell, allowing for accurate prediction of the voltage given other measurable parameters such as current and temperature. After conducting a sensitivity analysis on the size of the sequence needed to train the AR model, it was found that less than a days worth of raw measurements data is enough to offer a better voltage prediction than a traditional EEC model (the root mean square errors of the two considered voltage estimation approaches were 0.00157 and 0.0133 V, respectively).","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"19 1","pages":"2673-2680"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86028092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487432
Shen Wang, Kentaro Kitamura, S. Doki, Takashi Suzuki
A novel decoupling control scheme of a Dual Three Phase (DTP) Permanent Magnet Synchronous Motor (PMSM) drive with two microprocessors applying current observer is proposed in this work. Multiphase drives are considered as a viable solution for safety-critical applications, and substantial works have been conducted for this purpose. However, it should be noted that for a fault-tolerant drive, not only the machine itself should be considered, but also control executed Microcontroller Unit (MCU) Therefore, a novel configuration of an integrated fault tolerant DTP drive with two independent MCUs has become the interest of this paper. Magnetic coupling between winding sets is a big issue causing instability and dynamic deterioration. In order to implement decoupling current vector control on this particular system, an observer that estimates the other subsystem output current is proposed and utilized. Effectiveness of the proposed drive has been verified by experimental results.
{"title":"A Novel Decoupling Control of Dual Three Phase Drive with Two Independent Microprocessors Utilizing Current Observer","authors":"Shen Wang, Kentaro Kitamura, S. Doki, Takashi Suzuki","doi":"10.1109/APEC42165.2021.9487432","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487432","url":null,"abstract":"A novel decoupling control scheme of a Dual Three Phase (DTP) Permanent Magnet Synchronous Motor (PMSM) drive with two microprocessors applying current observer is proposed in this work. Multiphase drives are considered as a viable solution for safety-critical applications, and substantial works have been conducted for this purpose. However, it should be noted that for a fault-tolerant drive, not only the machine itself should be considered, but also control executed Microcontroller Unit (MCU) Therefore, a novel configuration of an integrated fault tolerant DTP drive with two independent MCUs has become the interest of this paper. Magnetic coupling between winding sets is a big issue causing instability and dynamic deterioration. In order to implement decoupling current vector control on this particular system, an observer that estimates the other subsystem output current is proposed and utilized. Effectiveness of the proposed drive has been verified by experimental results.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"241 1","pages":"2159-2165"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73435535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487439
N. Rajagopal, C. Dimarino, Brian T. DeBoi, A. Lemmon, Aaron D. Brovont
This work evaluates the electromagnetic interference (EMI) of a silicon carbide (SiC) MOSFET multi-chip power module (MCPM) with emerging organic direct bonded copper (ODBC) substrates. The thin, ductile organic insulator in ODBC substrates allows for thick copper to be used. The thick Cu enables higher current capacity and improved heat spreading. However, the thin dielectric increases capacitive coupling within the power module. This work evaluates the electromagnetic interference (EMI) characteristics of a SiC half-bridge module using ODBC substrates, and compares them to a commercial SiC module using standard ceramic DBC substrates. To mitigate the effects of the ODBC module’s increased capacitive coupling, a common-mode equivalent model (CEM) is leveraged to design a unique substrate layout that enables cancellation of leakage current through the baseplate. The proposed method shows that the ODBC module can achieve over 20 dB lower baseplate leakage current compared to a commercial power module for a single-phase half-bridge inverter implementation.
{"title":"EMI Evaluation of a SiC MOSFET Module with Organic DBC Substrate","authors":"N. Rajagopal, C. Dimarino, Brian T. DeBoi, A. Lemmon, Aaron D. Brovont","doi":"10.1109/APEC42165.2021.9487439","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487439","url":null,"abstract":"This work evaluates the electromagnetic interference (EMI) of a silicon carbide (SiC) MOSFET multi-chip power module (MCPM) with emerging organic direct bonded copper (ODBC) substrates. The thin, ductile organic insulator in ODBC substrates allows for thick copper to be used. The thick Cu enables higher current capacity and improved heat spreading. However, the thin dielectric increases capacitive coupling within the power module. This work evaluates the electromagnetic interference (EMI) characteristics of a SiC half-bridge module using ODBC substrates, and compares them to a commercial SiC module using standard ceramic DBC substrates. To mitigate the effects of the ODBC module’s increased capacitive coupling, a common-mode equivalent model (CEM) is leveraged to design a unique substrate layout that enables cancellation of leakage current through the baseplate. The proposed method shows that the ODBC module can achieve over 20 dB lower baseplate leakage current compared to a commercial power module for a single-phase half-bridge inverter implementation.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"29 1","pages":"2338-2344"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74610553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487113
Abualkasim Bakeer, A. Chub, D. Vinnikov
This paper proposes using an ac-switch at the output side of the series resonant converter (SRC) to boost the voltage with the full-bridge diodes rectifier. The proposed converter operates at a fixed switching frequency close to the resonant frequency. The output voltage of the converter could be regulated by adjusting the duty-cycle of the ac-switch instead of the frequency modulation. The proposed circuit features the soft-switching characteristics for the primary side semiconductors and the full-bridge diode rectifier. The mathematical model of the proposed converter is developed based on the described operating modes. The experimental results are obtained using a 300 W prototype to show the feasibility of the proposed converter at different input voltage and input power range. The peak efficiency of the proposed converter equals 97% at the nominal input voltage.
{"title":"Series Resonant DC-DC Converter with an AC-Switch-Based Full-Bridge Boost Rectifier","authors":"Abualkasim Bakeer, A. Chub, D. Vinnikov","doi":"10.1109/APEC42165.2021.9487113","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487113","url":null,"abstract":"This paper proposes using an ac-switch at the output side of the series resonant converter (SRC) to boost the voltage with the full-bridge diodes rectifier. The proposed converter operates at a fixed switching frequency close to the resonant frequency. The output voltage of the converter could be regulated by adjusting the duty-cycle of the ac-switch instead of the frequency modulation. The proposed circuit features the soft-switching characteristics for the primary side semiconductors and the full-bridge diode rectifier. The mathematical model of the proposed converter is developed based on the described operating modes. The experimental results are obtained using a 300 W prototype to show the feasibility of the proposed converter at different input voltage and input power range. The peak efficiency of the proposed converter equals 97% at the nominal input voltage.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"13 1","pages":"1985-1990"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75019141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-14DOI: 10.1109/APEC42165.2021.9487221
Saeed Khademi, R. Z. Davarani, R. Fadaeinedjad, G. Moschopoulos
Grid load data is an important factor in the placement and capacity of distributed generation (DG) in grid studies. Distribution networks are the largest part of electric networks and thus have the highest share of losses due to their low voltage and wide extent. Using power generation units near load centers can reduce grid losses considerably. For this purpose, the placement and capacity of DG units must be determined in order to maximize their potential. Usually, DG placement and capacity determination is done based on annual peak load data. This study shows that network load data such as peak load, average load, and hourly load strongly affect DG placement and capacity determination, and, therefore, will affect the annual network loss and the net present cost of DG installation during its useful life. In this study, different scenarios based on the type and number of network load input data, are considered and DG placement and capacity determination is performed for the IEEE 33 bus network. In order to do load flow studies, the Matpower program in the MATLAB environment is used and a genetic algorithm is used for optimization.
{"title":"Investigating the Effect of Grid Load Data on Optimal DG Placement and Capacity Determination","authors":"Saeed Khademi, R. Z. Davarani, R. Fadaeinedjad, G. Moschopoulos","doi":"10.1109/APEC42165.2021.9487221","DOIUrl":"https://doi.org/10.1109/APEC42165.2021.9487221","url":null,"abstract":"Grid load data is an important factor in the placement and capacity of distributed generation (DG) in grid studies. Distribution networks are the largest part of electric networks and thus have the highest share of losses due to their low voltage and wide extent. Using power generation units near load centers can reduce grid losses considerably. For this purpose, the placement and capacity of DG units must be determined in order to maximize their potential. Usually, DG placement and capacity determination is done based on annual peak load data. This study shows that network load data such as peak load, average load, and hourly load strongly affect DG placement and capacity determination, and, therefore, will affect the annual network loss and the net present cost of DG installation during its useful life. In this study, different scenarios based on the type and number of network load input data, are considered and DG placement and capacity determination is performed for the IEEE 33 bus network. In order to do load flow studies, the Matpower program in the MATLAB environment is used and a genetic algorithm is used for optimization.","PeriodicalId":7050,"journal":{"name":"2021 IEEE Applied Power Electronics Conference and Exposition (APEC)","volume":"36 1","pages":"2071-2076"},"PeriodicalIF":0.0,"publicationDate":"2021-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77738324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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