Pub Date : 2023-02-28DOI: 10.15598/aeee.v20i4.4594
Vutla Vijay, C. Venkaiah, Vinod Kumar Dulla Mallesham
. The application of Electric Vehicles (EVs) is increasing in many countries, causing many researchers to focus on EV Rapid Charging Station (RCS) related issues. The optimal planning of RCS considering only distribution networks is not a reli-able approach. Moreover, the RCS location should be convenient to the EV user in a given EV driving range and the performance of the distribution system. In this paper, a multi-objective approach for optimal planning of RCS and Distributed Generators (DG) in a distributed system coupled with a transportation network is analyzed. The proposed optimal planning method aims to achieve reduced active power loss, EV user costs, and voltage deviation for effective RCS and DG planning. The approach includes the analysis of the test system with the base case, solo planning of RCS, planning of DGs with fixed RCS, and simultaneous optimal planning of RCS and DGs. Daily load variation at buses and hourly charging probability of EVs have been used in the analysis. IEEE 33 bus distribution system superimposed with a 25-node transportation network is considered the test system. Rao 3 algorithm is applied for optimization, and the results have been compared with PSO and JAYA algorithms.
{"title":"Meta Heuristic Algorithm Based Multi Objective Optimal Planning of Rapid Charging Stations and Distribution Generators in a Distribution System Coupled with Transportation Network","authors":"Vutla Vijay, C. Venkaiah, Vinod Kumar Dulla Mallesham","doi":"10.15598/aeee.v20i4.4594","DOIUrl":"https://doi.org/10.15598/aeee.v20i4.4594","url":null,"abstract":". The application of Electric Vehicles (EVs) is increasing in many countries, causing many researchers to focus on EV Rapid Charging Station (RCS) related issues. The optimal planning of RCS considering only distribution networks is not a reli-able approach. Moreover, the RCS location should be convenient to the EV user in a given EV driving range and the performance of the distribution system. In this paper, a multi-objective approach for optimal planning of RCS and Distributed Generators (DG) in a distributed system coupled with a transportation network is analyzed. The proposed optimal planning method aims to achieve reduced active power loss, EV user costs, and voltage deviation for effective RCS and DG planning. The approach includes the analysis of the test system with the base case, solo planning of RCS, planning of DGs with fixed RCS, and simultaneous optimal planning of RCS and DGs. Daily load variation at buses and hourly charging probability of EVs have been used in the analysis. IEEE 33 bus distribution system superimposed with a 25-node transportation network is considered the test system. Rao 3 algorithm is applied for optimization, and the results have been compared with PSO and JAYA algorithms.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42952722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-28DOI: 10.15598/aeee.v20i4.4632
S. Patnaik, M. Nayak, M. Viswavandya
{"title":"Optimal Battery Energy Storage System Management with Wind Turbine Generator in Unbalanced Low Power Distribution System","authors":"S. Patnaik, M. Nayak, M. Viswavandya","doi":"10.15598/aeee.v20i4.4632","DOIUrl":"https://doi.org/10.15598/aeee.v20i4.4632","url":null,"abstract":"","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46039880","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-28DOI: 10.15598/aeee.v20i4.4664
Ani Harish, Prince Asok, J. Vasudevan
{"title":"Evaluation of Wavelet Transform Based Feature Extraction Techniques for Detection and Classification of Faults on Transmission Lines Using WAMS Data","authors":"Ani Harish, Prince Asok, J. Vasudevan","doi":"10.15598/aeee.v20i4.4664","DOIUrl":"https://doi.org/10.15598/aeee.v20i4.4664","url":null,"abstract":"","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45974909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-28DOI: 10.15598/aeee.v20i4.4562
V. Veeramsetty, Pravallika Jadhav, Eslavath Ramesh, Srividya Srinivasula, S. Salkuti
{"title":"Zero Crossing Point Detection in a Distorted Sinusoidal Signal Using Decision Tree Classifier","authors":"V. Veeramsetty, Pravallika Jadhav, Eslavath Ramesh, Srividya Srinivasula, S. Salkuti","doi":"10.15598/aeee.v20i4.4562","DOIUrl":"https://doi.org/10.15598/aeee.v20i4.4562","url":null,"abstract":"","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2023-02-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41296843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-03DOI: 10.15598/aeee.v20i3.4513
Adisorn Kwawsibsam, Danupat Duangmalai, Sittisak Yeeyoun, W. Jaikla
. This work presents the quadrature sinusoidal oscillator using two Voltage Differencing-Differential Input Buffered Amplifiers (VD-DIBAs), two resistors, and two capacitors. The VD-DIBA is an electronically controllable active building block with high input and low output impedances that can con-nect to other circuits directly without the buffers. With these distinguished features, the VD-DIBA is employed in this design. The proposed oscillator can produce two sine waves with a phase shift of 90 degrees. Over the entire tuning frequency range, the magnitude of the quadrature output voltages is constant. The proposed oscillator is independently adjustable in terms of frequency and oscillation condition. Moreover, the frequency of oscillation can be electronically and linearly adjusted by the bias currents. The condition of oscillation is adjustable by resistors, R 1 and R 2 . The performances of the proposed quadrature oscillator are tested through the PSpice simulation and the experiment. In the simulation, the VD-DIBA is built from the 0.18 µ m Taiwan Semiconductor Manufactur-ing Company (TSMC) CMOS process with ± 0 . 9 V supply voltages. In the experiment, the VD-DIBA is implemented using the commercial ICs, LM13700, and AD830 with ± 5 V supply voltages. The simulated To-tal Harmonic Distortion (THD) values of the output voltages, V o 1 and V o 2 at f 0 = 1 . 03 MHz are 1.63 % and 1.81 % , respectively. The experimental THD values of the output voltages, V o 1 and V o 2 at f 0 = 536 . 6 kHz, are 1.43 % and 1.00 % , respectively.
{"title":"Electronically and Independently Controllable Quadrature Sinusoidal Oscillator with Low Output Impedances","authors":"Adisorn Kwawsibsam, Danupat Duangmalai, Sittisak Yeeyoun, W. Jaikla","doi":"10.15598/aeee.v20i3.4513","DOIUrl":"https://doi.org/10.15598/aeee.v20i3.4513","url":null,"abstract":". This work presents the quadrature sinusoidal oscillator using two Voltage Differencing-Differential Input Buffered Amplifiers (VD-DIBAs), two resistors, and two capacitors. The VD-DIBA is an electronically controllable active building block with high input and low output impedances that can con-nect to other circuits directly without the buffers. With these distinguished features, the VD-DIBA is employed in this design. The proposed oscillator can produce two sine waves with a phase shift of 90 degrees. Over the entire tuning frequency range, the magnitude of the quadrature output voltages is constant. The proposed oscillator is independently adjustable in terms of frequency and oscillation condition. Moreover, the frequency of oscillation can be electronically and linearly adjusted by the bias currents. The condition of oscillation is adjustable by resistors, R 1 and R 2 . The performances of the proposed quadrature oscillator are tested through the PSpice simulation and the experiment. In the simulation, the VD-DIBA is built from the 0.18 µ m Taiwan Semiconductor Manufactur-ing Company (TSMC) CMOS process with ± 0 . 9 V supply voltages. In the experiment, the VD-DIBA is implemented using the commercial ICs, LM13700, and AD830 with ± 5 V supply voltages. The simulated To-tal Harmonic Distortion (THD) values of the output voltages, V o 1 and V o 2 at f 0 = 1 . 03 MHz are 1.63 % and 1.81 % , respectively. The experimental THD values of the output voltages, V o 1 and V o 2 at f 0 = 536 . 6 kHz, are 1.43 % and 1.00 % , respectively.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44484193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-03DOI: 10.15598/aeee.v20i3.4326
Mostafa Abdelouhab, Abdelilah Attar, R. Aboutni, J. Bouchnaif
. Improving the behavior of speed control in electric vehicles is currently a major challenge for re-searchers and engineers. For this study, we chose the context of a Switched Reluctance Motor (6/4 SRM) used in a hybrid Electric Vehicle with Extended Range (EREV). Speed regulation is an essential feature on long-distance trip. Speed regulators of backstepping type are very effective in this context given the nonlinear nature of switched reluctance motors. The estimation of non-linear quantities, flux and inductance, uses Legendre polynomials. The control strategy uses four regulators, one for speed and three for stator currents. It is based on the Torque Sharing Function (TSF) and the Torque Inverse Model (TIM). Our simulation consists of studying the behavior of this type of control when an Inter-Turn Short-Circuit (ITSC) fault appears on one of the phases of the 6/4 SRM. In this paper, we are interested in temporal behavior of phasic currents and we will show the interest of these quantities as fault indicators allowing the real time diagnosis of this type of controller-machine.
{"title":"Backstepping Control of a Switched Reluctance Motor with Inter-Turn Short-Circuit","authors":"Mostafa Abdelouhab, Abdelilah Attar, R. Aboutni, J. Bouchnaif","doi":"10.15598/aeee.v20i3.4326","DOIUrl":"https://doi.org/10.15598/aeee.v20i3.4326","url":null,"abstract":". Improving the behavior of speed control in electric vehicles is currently a major challenge for re-searchers and engineers. For this study, we chose the context of a Switched Reluctance Motor (6/4 SRM) used in a hybrid Electric Vehicle with Extended Range (EREV). Speed regulation is an essential feature on long-distance trip. Speed regulators of backstepping type are very effective in this context given the nonlinear nature of switched reluctance motors. The estimation of non-linear quantities, flux and inductance, uses Legendre polynomials. The control strategy uses four regulators, one for speed and three for stator currents. It is based on the Torque Sharing Function (TSF) and the Torque Inverse Model (TIM). Our simulation consists of studying the behavior of this type of control when an Inter-Turn Short-Circuit (ITSC) fault appears on one of the phases of the 6/4 SRM. In this paper, we are interested in temporal behavior of phasic currents and we will show the interest of these quantities as fault indicators allowing the real time diagnosis of this type of controller-machine.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48695192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-03DOI: 10.15598/aeee.v20i3.4461
A. Aboltins, A. Litvinenko, M. Terauds, A. Ahrens
. This paper proposes a novel linear precoding method for Orthogonal Frequency Division Multiplexing (OFDM) based on the employment of the chaotic waveforms generated by the fourth-order chaotic oscillator and orthonormalized by the Gram-Schmidt process. The proposed linear precoding method is aimed to increase resilience to the multipath propagation issues and reduce the Peak-to-Average Power Ratio (PAPR) of the transmitted signal. Moreover, the chaotic waveform enables novel timing synchronization methods to be implemented in the receiver. The modeling of baseband Linear Precoded OFDM (LP-OFDM) data transmission system with Rayleigh channel has been performed in Simulink en-vironment to validate the proposed method and to compare the performance to the classic precoding methods, such as Walsh-Hadamard Transform (WHT). Experiments have shown that in a high Signal-to-Noise Ratio (SNR) scenario, the employment of the novel precoding scheme allows reducing Bit Error Ratio (BER) by several dB compared to non-precoded OFDM. The proposed precoding method leads to the reduction of PAPR; however, it is not as efficient as classical precoding schemes, such as WHT. Experimental evidence of synchronization of the chaotic oscillators within 50 samples long time interval is presented.
{"title":"Use of Chaotic Oscillations for Precoding and Synchronization in OFDM","authors":"A. Aboltins, A. Litvinenko, M. Terauds, A. Ahrens","doi":"10.15598/aeee.v20i3.4461","DOIUrl":"https://doi.org/10.15598/aeee.v20i3.4461","url":null,"abstract":". This paper proposes a novel linear precoding method for Orthogonal Frequency Division Multiplexing (OFDM) based on the employment of the chaotic waveforms generated by the fourth-order chaotic oscillator and orthonormalized by the Gram-Schmidt process. The proposed linear precoding method is aimed to increase resilience to the multipath propagation issues and reduce the Peak-to-Average Power Ratio (PAPR) of the transmitted signal. Moreover, the chaotic waveform enables novel timing synchronization methods to be implemented in the receiver. The modeling of baseband Linear Precoded OFDM (LP-OFDM) data transmission system with Rayleigh channel has been performed in Simulink en-vironment to validate the proposed method and to compare the performance to the classic precoding methods, such as Walsh-Hadamard Transform (WHT). Experiments have shown that in a high Signal-to-Noise Ratio (SNR) scenario, the employment of the novel precoding scheme allows reducing Bit Error Ratio (BER) by several dB compared to non-precoded OFDM. The proposed precoding method leads to the reduction of PAPR; however, it is not as efficient as classical precoding schemes, such as WHT. Experimental evidence of synchronization of the chaotic oscillators within 50 samples long time interval is presented.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45713707","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-03DOI: 10.15598/aeee.v20i3.3998
Tomas Mizdos, M. Barkowsky, P. Počta, M. Uhrina
. From the beginnings of ITU-T H.261 to H.265 (HEVC), each new video coding standard has aimed at halving the bitrate at the same perceptual quality by redundancy and irrelevancy reduction. Each improvement has been explained by comparably small changes in the video coding toolset. This contribu-tion aims at starting the Quality of Experience (QoE) analysis of the accumulated improvements over the last thirty years. Based on an overview of the changes in the coding tools, we analyze the changes in the quantized residual information. Visual comparison and statistical measures are performed and some interpreta-tions are provided towards explaining how irrelevancy reduction may have led to such a huge reduction in bitrate. The interpretation of the results in terms of QoE paves the way towards an understanding of the coding tools in terms of visual quality. It may help in understanding how the irrelevancy reduction has been improved over the decades. the differences of the residuals relate to known or yet un-known properties of the human visual system, may en-able a closer collaboration between perception research and video compression research.
{"title":"30 Years of Video Coding Evolution - What Can We Learn from it in Terms of QoE?","authors":"Tomas Mizdos, M. Barkowsky, P. Počta, M. Uhrina","doi":"10.15598/aeee.v20i3.3998","DOIUrl":"https://doi.org/10.15598/aeee.v20i3.3998","url":null,"abstract":". From the beginnings of ITU-T H.261 to H.265 (HEVC), each new video coding standard has aimed at halving the bitrate at the same perceptual quality by redundancy and irrelevancy reduction. Each improvement has been explained by comparably small changes in the video coding toolset. This contribu-tion aims at starting the Quality of Experience (QoE) analysis of the accumulated improvements over the last thirty years. Based on an overview of the changes in the coding tools, we analyze the changes in the quantized residual information. Visual comparison and statistical measures are performed and some interpreta-tions are provided towards explaining how irrelevancy reduction may have led to such a huge reduction in bitrate. The interpretation of the results in terms of QoE paves the way towards an understanding of the coding tools in terms of visual quality. It may help in understanding how the irrelevancy reduction has been improved over the decades. the differences of the residuals relate to known or yet un-known properties of the human visual system, may en-able a closer collaboration between perception research and video compression research.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44831476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-03DOI: 10.15598/aeee.v20i3.4483
Hinal Shah, N. Chothani, J. Chakravorty
. Protective relays are installed in generation, transmission, and distribution system for detection, classi(cid:28)cation, and estimation of faults. To match the future load demand and to get uninterrupted power supply, use of renewable energy sources are increasing day by day. Faults can occur in transmission lines, transformers, generators, and busbars but the nature of these faults may change many times when renewable energy sources are considered. This research paper introduce techniques to detect and classify different faults on transmission line in the presence of wind energy sources using ef(cid:28)cient tools of ar-ti(cid:28)cial intelligence. The main challenges of the system fault detection, in presence of wind turbine lie in their non-linearity, uncertainty and unknown disturbances. PSCAD/EMTDC software tool is used to sim-ulate the power system model with RES which is implemented in MATLAB and Python software. Arti(cid:28)cial Neural Network (ANN) and Support Vector Machine (SVM) algorithms have been used to classify and detect faults on transmission lines connected with wind energy source. The proposed technique has been validated for internal faults on transmission line and external faults on power system. In total of 4320 internal and external fault cases with wide variation in system parameters have been used for validation of the proposed model. The proposed model gives an overall fault zone identi(cid:28)cation accuracy of more than 99 % in presence of wind energy source. The results obtained from validation show that the performance of SVM classi(cid:28)er is better than ANN in term of ef(cid:28)cacy and classi(cid:28)cation time.
{"title":"Fault Detection and Classification in Interconnected System with Wind Generation Using ANN and SVM","authors":"Hinal Shah, N. Chothani, J. Chakravorty","doi":"10.15598/aeee.v20i3.4483","DOIUrl":"https://doi.org/10.15598/aeee.v20i3.4483","url":null,"abstract":". Protective relays are installed in generation, transmission, and distribution system for detection, classi(cid:28)cation, and estimation of faults. To match the future load demand and to get uninterrupted power supply, use of renewable energy sources are increasing day by day. Faults can occur in transmission lines, transformers, generators, and busbars but the nature of these faults may change many times when renewable energy sources are considered. This research paper introduce techniques to detect and classify different faults on transmission line in the presence of wind energy sources using ef(cid:28)cient tools of ar-ti(cid:28)cial intelligence. The main challenges of the system fault detection, in presence of wind turbine lie in their non-linearity, uncertainty and unknown disturbances. PSCAD/EMTDC software tool is used to sim-ulate the power system model with RES which is implemented in MATLAB and Python software. Arti(cid:28)cial Neural Network (ANN) and Support Vector Machine (SVM) algorithms have been used to classify and detect faults on transmission lines connected with wind energy source. The proposed technique has been validated for internal faults on transmission line and external faults on power system. In total of 4320 internal and external fault cases with wide variation in system parameters have been used for validation of the proposed model. The proposed model gives an overall fault zone identi(cid:28)cation accuracy of more than 99 % in presence of wind energy source. The results obtained from validation show that the performance of SVM classi(cid:28)er is better than ANN in term of ef(cid:28)cacy and classi(cid:28)cation time.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48624663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
. Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects and potential applications in Integrated Circuit (IC) industry. based implementations with rapid response and simul-taneous generation of complemented output is all set to become indispensable in nano regime industry. This paper attempts to optimize and address performance-based analysis of digital circuits namely NAND, D flipflop and 3-bit asynchronous counter by practicing MCML based implementation. These circuits are con-templated on four design parameters namely delay ( t p ), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). This research focuses on relative analysis and emanate a salient optimal application of Complementary Metal-Oxide-Semiconductor (CMOS) and Carbon Nanotube Field Effect Transistor (CNFET) based 3-bit asynchronous counter. In ad-dition to this, the two configurations of the MCML counter are then compared against applied V DD at 16-nm technology nodes using HSPICE simulator. CNFET based 3-bit MCML counter is observed to be much faster (9.75 × ), significant improvement in gross power dissipation (11.93 × ), material refinement in PDP and EDP (116.39 × and 1165 × ) re-spectively as compared to the conventional counterpart. Therefore, CNFET based implementations comes to the fore as resilient technology supporting high level integration in nano scale regime.
{"title":"Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology","authors":"Ramsha Suhail, Pragya Srivastava, Richa Yadav, Richa Srivastava","doi":"10.15598/aeee.v20i3.4279","DOIUrl":"https://doi.org/10.15598/aeee.v20i3.4279","url":null,"abstract":". Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects and potential applications in Integrated Circuit (IC) industry. based implementations with rapid response and simul-taneous generation of complemented output is all set to become indispensable in nano regime industry. This paper attempts to optimize and address performance-based analysis of digital circuits namely NAND, D flipflop and 3-bit asynchronous counter by practicing MCML based implementation. These circuits are con-templated on four design parameters namely delay ( t p ), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). This research focuses on relative analysis and emanate a salient optimal application of Complementary Metal-Oxide-Semiconductor (CMOS) and Carbon Nanotube Field Effect Transistor (CNFET) based 3-bit asynchronous counter. In ad-dition to this, the two configurations of the MCML counter are then compared against applied V DD at 16-nm technology nodes using HSPICE simulator. CNFET based 3-bit MCML counter is observed to be much faster (9.75 × ), significant improvement in gross power dissipation (11.93 × ), material refinement in PDP and EDP (116.39 × and 1165 × ) re-spectively as compared to the conventional counterpart. Therefore, CNFET based implementations comes to the fore as resilient technology supporting high level integration in nano scale regime.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":null,"pages":null},"PeriodicalIF":0.6,"publicationDate":"2022-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46375555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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