Pub Date : 2021-09-28DOI: 10.15598/aeee.v19i3.4050
Hilmi F. Ameen, Fadhil T. Aula
This paper develops a mathematical model for analyzing the steady-state performance of the Slip Power Recovery Induction Motor Drive System (SPRIMDS) which operates under unbalance supply voltage conditions. The IEC definition indices of Voltage Unbalance Factor (VUF) and Complex Voltage Unbalance Factor (CVUF) which consist of magnitude and phase angle of the unbalance supply are used for the analysis. Also, this paper evaluates the impact of voltage unbalance and firing angle of the inverter on the stator and rotor motor parameters, motor currents, copper losses, efficiency, power factor, torque-speed characteristics, prediction of peak currents of the stator and rotor phase windings, and Total Harmonic Distortion (THD) of stator and rotor currents. The proposed mathematical model of SPRIMDS is validated using MATLAB-Simulink. The results have shown that the performance of the SPRIMDS and variation of motor currents, efficiency, THD and torque are depending on the magnitude of the voltage unbalance and inverter's firing angle.
{"title":"Performance Analysis of the Slip Power Recovery Induction Motor Drive System Under Unbalance Supply Voltages","authors":"Hilmi F. Ameen, Fadhil T. Aula","doi":"10.15598/aeee.v19i3.4050","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4050","url":null,"abstract":"This paper develops a mathematical model for analyzing the steady-state performance of the Slip Power Recovery Induction Motor Drive System (SPRIMDS) which operates under unbalance supply voltage conditions. The IEC definition indices of Voltage Unbalance Factor (VUF) and Complex Voltage Unbalance Factor (CVUF) which consist of magnitude and phase angle of the unbalance supply are used for the analysis. Also, this paper evaluates the impact of voltage unbalance and firing angle of the inverter on the stator and rotor motor parameters, motor currents, copper losses, efficiency, power factor, torque-speed characteristics, prediction of peak currents of the stator and rotor phase windings, and Total Harmonic Distortion (THD) of stator and rotor currents. The proposed mathematical model of SPRIMDS is validated using MATLAB-Simulink. The results have shown that the performance of the SPRIMDS and variation of motor currents, efficiency, THD and torque are depending on the magnitude of the voltage unbalance and inverter's firing angle.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44811500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.15598/aeee.v19i3.4071
M. Duong, J. Veselý, P. Hubáček, P. Janu, Phan Nhat Giang
The pulse with intra-pulse modulation plays an important role in the design of radar systems. The first class of the signals type is the linear frequency modulation technique. The linear frequency modulation is used to resolve range resolution problems. This paper provides a new algorithm for detecting linear frequency modulation signals at a low signal-to-noise ratio. The core idea of the proposed method is firstly to analyse the linear frequency modulation signals via Fast Fourier Transform; and then to accumulate all energy to achieve signal detection using cross-correlation methods. The proposed algorithm showed better results in comparison with current algorithms, which are used to estimate the parameters of the linear frequency modulation signals at a low signal-to-noise ratio.
{"title":"Parameter Estimation of LFM Signal in Low Signal-to-Noise Ratio Using Cross-Correlation Function","authors":"M. Duong, J. Veselý, P. Hubáček, P. Janu, Phan Nhat Giang","doi":"10.15598/aeee.v19i3.4071","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4071","url":null,"abstract":"The pulse with intra-pulse modulation plays an important role in the design of radar systems. The first class of the signals type is the linear frequency modulation technique. The linear frequency modulation is used to resolve range resolution problems. This paper provides a new algorithm for detecting linear frequency modulation signals at a low signal-to-noise ratio. The core idea of the proposed method is firstly to analyse the linear frequency modulation signals via Fast Fourier Transform; and then to accumulate all energy to achieve signal detection using cross-correlation methods. The proposed algorithm showed better results in comparison with current algorithms, which are used to estimate the parameters of the linear frequency modulation signals at a low signal-to-noise ratio.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45861857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.15598/aeee.v19i3.4124
P. C. Eze, Bonaventure Onyekachi Ekengwu, N. Asiegbu, ThankGod I. Ozue
This paper has presented hard braking control system based on Adjustable Gain Enhanced Fuzzy Logic Controller (AGE-FLC) for optimal wheel slip ratio tracking performance. The purpose of the study was to improve slip ratio tracking and eliminate cycling while achieving very much shortened distance during emergency braking. The model of a braking vehicle at speed of 30 m.s^-1 subject to wheel locking was developed and implemented in MATLAB/Simulink environment. Simulation was conducted without a controller to study the slip ratio performance of the system on different road surfaces. The simulation results showed that stopping distance was 135.2 m in 5 seconds. A Fuzzy Logic Controller (FLC) whose control signal was enhanced by adding an adjustable gain mechanism to its output was designed. Simulation results showed that the AGE-FLC controller offered optimal tracking of desired wheel slip ratio of 0.1 as fast as possible on all road surface scenarios, while improving the stopping distance by 70.4% on dry road surface, 63.3% on wet road surface, 57.5% on cobblestone road surface and 48.8% on snow road surface in 2.651seconds.
{"title":"Adjustable Gain Enhanced Fuzzy Logic Controller for Optimal Wheel Slip Ratio Tracking in Hard Braking Control System","authors":"P. C. Eze, Bonaventure Onyekachi Ekengwu, N. Asiegbu, ThankGod I. Ozue","doi":"10.15598/aeee.v19i3.4124","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4124","url":null,"abstract":"This paper has presented hard braking control system based on Adjustable Gain Enhanced Fuzzy Logic Controller (AGE-FLC) for optimal wheel slip ratio tracking performance. The purpose of the study was to improve slip ratio tracking and eliminate cycling while achieving very much shortened distance during emergency braking. The model of a braking vehicle at speed of 30 m.s^-1 subject to wheel locking was developed and implemented in MATLAB/Simulink environment. Simulation was conducted without a controller to study the slip ratio performance of the system on different road surfaces. The simulation results showed that stopping distance was 135.2 m in 5 seconds. A Fuzzy Logic Controller (FLC) whose control signal was enhanced by adding an adjustable gain mechanism to its output was designed. Simulation results showed that the AGE-FLC controller offered optimal tracking of desired wheel slip ratio of 0.1 as fast as possible on all road surface scenarios, while improving the stopping distance by 70.4% on dry road surface, 63.3% on wet road surface, 57.5% on cobblestone road surface and 48.8% on snow road surface in 2.651seconds.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47895281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.15598/aeee.v19i3.4116
T. Nguyen, D. Do
In a wireless system, dual-hop transmission requires Full-Duplex (FD) to transmit signals from the base station too far users. It is more beneficial if we deploy non-orthogonal multiple access to serve specific users, i.e. normal users (near and far users) and device-to-device users. The fairness and outage performance of these users can be studied. We particularly focus on mathematical analysis of outage performance which is computed based on Signal to Noise Ratio (SNR) of received signals at each kind of user. We derive a closed-form formula of such outage probability along with throughput. To realize both the FD NOMA, this paper performs system performance metrics and considers how self-interference make influences system performance. The simulation results validate the theoretical analysis and show that our scheme can obtain a better outage probability and throughput performance with high transmit SNR at the base station and lower required target rates.
{"title":"Exploiting Full-duplex and Fixed Power Allocation Approaches for Dual-hop Transmission in Downlink NOMA","authors":"T. Nguyen, D. Do","doi":"10.15598/aeee.v19i3.4116","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4116","url":null,"abstract":"In a wireless system, dual-hop transmission requires Full-Duplex (FD) to transmit signals from the base station too far users. It is more beneficial if we deploy non-orthogonal multiple access to serve specific users, i.e. normal users (near and far users) and device-to-device users. The fairness and outage performance of these users can be studied. We particularly focus on mathematical analysis of outage performance which is computed based on Signal to Noise Ratio (SNR) of received signals at each kind of user. We derive a closed-form formula of such outage probability along with throughput. To realize both the FD NOMA, this paper performs system performance metrics and considers how self-interference make influences system performance. The simulation results validate the theoretical analysis and show that our scheme can obtain a better outage probability and throughput performance with high transmit SNR at the base station and lower required target rates.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":"1 1","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67227864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.15598/AEEE.V19I3.4199
Riya Jain, Khushbu Pahwa, N. Pandey
There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical in terms of hardware and cannot afford to compromise accuracy or reliability. Multiplier, being one of the most heavily used components, becomes crucial in these applications. If optimized, multipliers can impact the overall performance of the system. Thus, in this paper, an attempt has been made to determine the potential of accurate multipliers while meeting minimal hardware requirements. In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier. These architectures have been developed using two types of Booth encoding: Radix-4 and Radix-8 for 16-bit, 32-bit and 64-bit multiplications. The algorithm is designed to be parameterizable to different bit widths, thereby offering higher flexibility. The proposed mul- tiplier offers advantage of enhanced performance with significant reduction in hardware while negligibly trad- ing off the Power Delay Product (PDP). It has been observed that the performance of the proposed architecture increases with increasing multiplier size due to significant reduction in hardware and slight increase in PDP. All the architectures have been implemented in Verilog HDL using Xilinx Vivado Design Suite.
{"title":"Booth-Encoded Karatsuba: A Novel Hardware-Efficient Multiplier","authors":"Riya Jain, Khushbu Pahwa, N. Pandey","doi":"10.15598/AEEE.V19I3.4199","DOIUrl":"https://doi.org/10.15598/AEEE.V19I3.4199","url":null,"abstract":"There is a recent boom being witnessed in emerging areas like IoMT (Internet of Medical Things), Artificial Intelligence for healthcare, and disaster management. These novel research frontiers are critical in terms of hardware and cannot afford to compromise accuracy or reliability. Multiplier, being one of the most heavily used components, becomes crucial in these applications. If optimized, multipliers can impact the overall performance of the system. Thus, in this paper, an attempt has been made to determine the potential of accurate multipliers while meeting minimal hardware requirements. In this paper, we propose a novel Booth-Encoded Karatsuba multiplier and provide its comparison with a Booth-Encoded Wallace tree multiplier. These architectures have been developed using two types of Booth encoding: Radix-4 and Radix-8 for 16-bit, 32-bit and 64-bit multiplications. The algorithm is designed to be parameterizable to different bit widths, thereby offering higher flexibility. The proposed mul- tiplier offers advantage of enhanced performance with significant reduction in hardware while negligibly trad- ing off the Power Delay Product (PDP). It has been observed that the performance of the proposed architecture increases with increasing multiplier size due to significant reduction in hardware and slight increase in PDP. All the architectures have been implemented in Verilog HDL using Xilinx Vivado Design Suite.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":"19 1","pages":"272-281"},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46134466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-09-28DOI: 10.15598/aeee.v19i3.4010
Nagaraju Mamidi, S. Gupta, Vijaya Bhadauria
The ever-increasing demand for high-quality digital video requires efficient compression techniques and fast video codecs. It necessitates increased complexity of the video codec algorithms. So, there is a need for hardware accelerators to implement such complex algorithms. The latest video compression algorithms such as High-Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) have been adopted Context-based Adaptive Binary Arithmetic Coding (CABAC) as the entropy coding method. The CABAC has two main data processing paths: regular and bypass bin path, which can achieve good compression when used with Syntax Elements (SEs) statistics. However, it is highly intrinsic data dependence and has sequential coding characteristics. Thus, it is challenging to parallelize. In this work, a 6-core bypass bin path having high-throughput and low hardware area has been proposed. It is a parallel architecture capable of processing up to 6 bypass bins per clock cycle to improve throughput. Further, the resource-sharing techniques within the binarization and a common controller block have reduced the hardware area. The proposed architecture has been simulated, synthesized, and prototyped on 28 nm Artix 7 Field Programmable Gate Array (FPGA). The implementation of Application Specific Integrated Circuit (ASIC) has been done using 65 nm CMOS technology. The proposed design achieved a throughput of 1.26 Gbin/s at 210 MHz operating frequency with a low hardware area compared to existing architectures. This architecture also supports multi-standard (HEVC/VVC) encoders for Ultra High Definition (UHD) applications.
{"title":"Design and Implementation of Parallel Bypass Bin Processing for CABAC Encoder","authors":"Nagaraju Mamidi, S. Gupta, Vijaya Bhadauria","doi":"10.15598/aeee.v19i3.4010","DOIUrl":"https://doi.org/10.15598/aeee.v19i3.4010","url":null,"abstract":"The ever-increasing demand for high-quality digital video requires efficient compression techniques and fast video codecs. It necessitates increased complexity of the video codec algorithms. So, there is a need for hardware accelerators to implement such complex algorithms. The latest video compression algorithms such as High-Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) have been adopted Context-based Adaptive Binary Arithmetic Coding (CABAC) as the entropy coding method. The CABAC has two main data processing paths: regular and bypass bin path, which can achieve good compression when used with Syntax Elements (SEs) statistics. However, it is highly intrinsic data dependence and has sequential coding characteristics. Thus, it is challenging to parallelize. In this work, a 6-core bypass bin path having high-throughput and low hardware area has been proposed. It is a parallel architecture capable of processing up to 6 bypass bins per clock cycle to improve throughput. Further, the resource-sharing techniques within the binarization and a common controller block have reduced the hardware area. The proposed architecture has been simulated, synthesized, and prototyped on 28 nm Artix 7 Field Programmable Gate Array (FPGA). The implementation of Application Specific Integrated Circuit (ASIC) has been done using 65 nm CMOS technology. The proposed design achieved a throughput of 1.26 Gbin/s at 210 MHz operating frequency with a low hardware area compared to existing architectures. This architecture also supports multi-standard (HEVC/VVC) encoders for Ultra High Definition (UHD) applications.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47693994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-30DOI: 10.15598/AEEE.V19I2.4149
D. Gašparovský, P. Janiga, J. Raditschová
Amongst many road lighting design criteria, energy performance plays an important role as it has a~direct link to operational costs, potential reduction of carbon dioxide emissions, mitigation of obtrusive light, and its impact on the night-time environment in urban and conurban settlements. The energy performance of road lighting is conveniently described by the pair of normative numerical indicators PDI and AECI established in European standards. This article aims to present typical values of these indicators for different combinations of road arrangements, road widths, lighting classes and light source technologies to illustrate what benchmarks can be expected using this assessment system. Objectives of the article also comprise discussion on factors influencing the energy performance and conclusion whether it is appropriate to introduce limiting value requirements and/or ranking systems to label energy performance of road lighting systems.
{"title":"Typical Values of Energy Performance Indicators in Road Lighting","authors":"D. Gašparovský, P. Janiga, J. Raditschová","doi":"10.15598/AEEE.V19I2.4149","DOIUrl":"https://doi.org/10.15598/AEEE.V19I2.4149","url":null,"abstract":"Amongst many road lighting design criteria, energy performance plays an important role as it has a~direct link to operational costs, potential reduction of carbon dioxide emissions, mitigation of obtrusive light, and its impact on the night-time environment in urban and conurban settlements. The energy performance of road lighting is conveniently described by the pair of normative numerical indicators PDI and AECI established in European standards. This article aims to present typical values of these indicators for different combinations of road arrangements, road widths, lighting classes and light source technologies to illustrate what benchmarks can be expected using this assessment system. Objectives of the article also comprise discussion on factors influencing the energy performance and conclusion whether it is appropriate to introduce limiting value requirements and/or ranking systems to label energy performance of road lighting systems.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44622947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-30DOI: 10.15598/aeee.v19i2.4133
A. Zawadzka, Kornelia Indykiewic, R. Paszkiewicz
One of the most significant processes in micro- and nanoelectronics technology is Electron Beam Lithography (EBL). This technique maintains a leading role in extremely high-resolution structures fabrication process with micro- and nanometer dimensions down to dozens of nanometers. The EBL is a highly complex process and determining fundamental technological factors that affect the final pattern shape is crucial. One of them is the used lithography system, consisting of a substrate and a polymer layer that affects the electron scattering effects. To obtain the required pattern geometry, it is also necessary to properly select the electron beam parameters for given materials. The aim of this work is to discuss the differences in the exposition process for various accelerating voltage (EHT) values. Additionally, the investigation of geometry features and the impact of the exposure dose and the structure dimensions on the final absorbed energy distribution profile in the resist layer is presented and discussed. Numerical studies, using CASINO software and Monte Carlo method, are presented to compare the energy distribution in the polymer that affects the structure formation in the resist layer.
{"title":"The Validation of Various Technological Factors Impact on the Electron Beam Lithography Process","authors":"A. Zawadzka, Kornelia Indykiewic, R. Paszkiewicz","doi":"10.15598/aeee.v19i2.4133","DOIUrl":"https://doi.org/10.15598/aeee.v19i2.4133","url":null,"abstract":"One of the most significant processes in micro- and nanoelectronics technology is Electron Beam Lithography (EBL). This technique maintains a leading role in extremely high-resolution structures fabrication process with micro- and nanometer dimensions down to dozens of nanometers. The EBL is a highly complex process and determining fundamental technological factors that affect the final pattern shape is crucial. One of them is the used lithography system, consisting of a substrate and a polymer layer that affects the electron scattering effects. To obtain the required pattern geometry, it is also necessary to properly select the electron beam parameters for given materials. The aim of this work is to discuss the differences in the exposition process for various accelerating voltage (EHT) values. Additionally, the investigation of geometry features and the impact of the exposure dose and the structure dimensions on the final absorbed energy distribution profile in the resist layer is presented and discussed. Numerical studies, using CASINO software and Monte Carlo method, are presented to compare the energy distribution in the polymer that affects the structure formation in the resist layer.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44918896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-30DOI: 10.15598/AEEE.V19I2.3945
M. Vins, J. Dragoun, Martin Sirový
Motivation and complex process of energy storage technology and converter topology design suitable for integration in thermal power plant systems to improve flexibility and primary frequency control is presented in the paper. The case study of typical thermal power plant is included and optimal power and capacity are determined. Next, there are discussed and compared perspective accumulation technologies. Most perspective state of the art battery-based technologies are further in detail evaluated including employed methodology. The next part is focused on suitable converter topology design. Employed converter control algorithms including simulation results are presented.
{"title":"Energy Storage Technology and Converter Topology for Primary Frequency Control in Thermal Power Plant","authors":"M. Vins, J. Dragoun, Martin Sirový","doi":"10.15598/AEEE.V19I2.3945","DOIUrl":"https://doi.org/10.15598/AEEE.V19I2.3945","url":null,"abstract":"Motivation and complex process of energy storage technology and converter topology design suitable for integration in thermal power plant systems to improve flexibility and primary frequency control is presented in the paper. The case study of typical thermal power plant is included and optimal power and capacity are determined. Next, there are discussed and compared perspective accumulation technologies. Most perspective state of the art battery-based technologies are further in detail evaluated including employed methodology. The next part is focused on suitable converter topology design. Employed converter control algorithms including simulation results are presented.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"45838090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2021-06-30DOI: 10.15598/AEEE.V19I2.4140
G. Cibira
Intrinsic resistivity of any semiconductor silicon layer strongly depends on dopants and impurities concentrations. Structural properties, treating, coating, finishing etc. affect dynamic resistance behaviour of a given p-n junction in a wafer. It is important for massively used photovoltaics, optoelectronics, microelectronics, and other solid-state electronics. In this work, efficient, universally applicable methodology is presented to investigate silicon resistive parameters. First, the silicon band gap models are studied. Influence of electrical resistivity on resistances and complex impedance parts is investigated. Dynamic iterative numerical modelling and simulations combined with sparse-matrix experimental measurements lead to extrapolated behaviours of these resistive parameters. All parameters are investigated within acceptable practical interval up to extremals.
{"title":"Silicon Resistivity Behaviour","authors":"G. Cibira","doi":"10.15598/AEEE.V19I2.4140","DOIUrl":"https://doi.org/10.15598/AEEE.V19I2.4140","url":null,"abstract":"Intrinsic resistivity of any semiconductor silicon layer strongly depends on dopants and impurities concentrations. Structural properties, treating, coating, finishing etc. affect dynamic resistance behaviour of a given p-n junction in a wafer. It is important for massively used photovoltaics, optoelectronics, microelectronics, and other solid-state electronics. In this work, efficient, universally applicable methodology is presented to investigate silicon resistive parameters. First, the silicon band gap models are studied. Influence of electrical resistivity on resistances and complex impedance parts is investigated. Dynamic iterative numerical modelling and simulations combined with sparse-matrix experimental measurements lead to extrapolated behaviours of these resistive parameters. All parameters are investigated within acceptable practical interval up to extremals.","PeriodicalId":7268,"journal":{"name":"Advances in Electrical and Electronic Engineering","volume":" ","pages":""},"PeriodicalIF":0.6,"publicationDate":"2021-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42209941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：