This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.
{"title":"Design of CDTA and VDTA Based Frequency Agile Filters","authors":"N. Pandey, Aseem Sayal, R. Choudhary, R. Pandey","doi":"10.1155/2014/176243","DOIUrl":"https://doi.org/10.1155/2014/176243","url":null,"abstract":"This paper presents frequency agile filters based on current difference transconductance amplifier (CDTA) and voltage difference transconductance amplifier (VDTA). The proposed agile filter configurations employ grounded passive components and hence are suitable for integration. Extensive SPICE simulations using 0.25 μm TSMC CMOS technology model parameters are carried out for functional verification. The proposed configurations are compared in terms of performance parameters such as power dissipation, signal to noise ratio (SNR), and maximum output noise voltage.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-15"},"PeriodicalIF":0.0,"publicationDate":"2014-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64377924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In many military and industrial applications, GaAs photovoltaic (PV) converters are connected in series in order to generate the required voltage compatible with most common electronics. Multimode optical fibers are usually used to carry high-intensity laser and illuminate the series connected GaAs PV converters in real time. However, multimode optical fiber illumination has a speckled intensity pattern. The series connected PV array is extremely sensitive to nonuniform illumination; its performance is limited severely by the converter that is illuminated the least. This paper quantifies the effects of multimode optical fiber illumination on the performance of series connected GaAs PV converters, analyzes the loss mechanisms due to speckles, and discusses the maximum illumination efficiency. In order to describe the illumination dependent behavior detailedly, modeling of the series connected PV array is accomplished based on the equivalent circuit for PV cells. Finally, a series of experiments are carried out to demonstrate the theory analysis.
{"title":"Performance of Series Connected GaAs Photovoltaic Converters under Multimode Optical Fiber Illumination","authors":"Tiqiang Shan, Xinglin Qi","doi":"10.1155/2014/824181","DOIUrl":"https://doi.org/10.1155/2014/824181","url":null,"abstract":"In many military and industrial applications, GaAs photovoltaic (PV) converters are connected in series in order to generate the required voltage compatible with most common electronics. Multimode optical fibers are usually used to carry high-intensity laser and illuminate the series connected GaAs PV converters in real time. However, multimode optical fiber illumination has a speckled intensity pattern. The series connected PV array is extremely sensitive to nonuniform illumination; its performance is limited severely by the converter that is illuminated the least. This paper quantifies the effects of multimode optical fiber illumination on the performance of series connected GaAs PV converters, analyzes the loss mechanisms due to speckles, and discusses the maximum illumination efficiency. In order to describe the illumination dependent behavior detailedly, modeling of the series connected PV array is accomplished based on the equivalent circuit for PV cells. Finally, a series of experiments are carried out to demonstrate the theory analysis.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/824181","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64693605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain the effective number of bit 9.55 in 100 KS/s sampling rate.
{"title":"Low Power Data Acquisition System for Bioimplantable Devices","authors":"Sadeque Reza Khan, M. S. Bhat","doi":"10.1155/2014/394057","DOIUrl":"https://doi.org/10.1155/2014/394057","url":null,"abstract":"Signal acquisition represents the most important block in biomedical devices, because of its responsibilities to retrieve precise data from the biological tissues. In this paper an energy efficient data acquisition unit is presented which includes low power high bandwidth front-end amplifier and a 10-bit fully differential successive approximation ADC. The proposed system is designed with 0.18 µm CMOS technology and the simulation results show that the bioamplifier maintains a wide bandwidth versus low noise trade-off and the proposed SAR-ADC consumes 450 nW power under 1.8 V supply and retain the effective number of bit 9.55 in 100 KS/s sampling rate.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-13"},"PeriodicalIF":0.0,"publicationDate":"2014-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/394057","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64476779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog signals, optimized for the communication medium, to the optimal on-chip signal representation, the digital one, for the IC medium. The signals in the AMS part itself are consequently not optimally matched to the IC medium. To further shift the frontiers of AMS design, a matching-driven design approach is crucial for AMS. Four levels will be addressed: technology-driven, states-driven, redundancy-driven, and nature-driven design. This is done based on an analysis of the various classes of AMS signals and their specific properties, seen from the angle of redundancy. This generic, but abstract way of looking at the design process will be substantiated with many specific examples.
{"title":"Shifting the Frontiers of Analog and Mixed-Signal Electronics","authors":"A. Roermund","doi":"10.1155/2014/590970","DOIUrl":"https://doi.org/10.1155/2014/590970","url":null,"abstract":"Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog signals, optimized for the communication medium, to the optimal on-chip signal representation, the digital one, for the IC medium. The signals in the AMS part itself are consequently not optimally matched to the IC medium. To further shift the frontiers of AMS design, a matching-driven design approach is crucial for AMS. Four levels will be addressed: technology-driven, states-driven, redundancy-driven, and nature-driven design. This is done based on an analysis of the various classes of AMS signals and their specific properties, seen from the angle of redundancy. This generic, but abstract way of looking at the design process will be substantiated with many specific examples.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"590970"},"PeriodicalIF":0.0,"publicationDate":"2014-12-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/590970","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64563382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SrTiO3:Pr3+ is the most representative titanate matrix red phosphor for field emission display (FED). The red luminous efficiency of SrTiO3:Pr3+ will be greatly improved after the compensation ions codoping, so SrTiO3:Pr3+ red phosphor has been a research focus at home and abroad. SrTiO3:Pr3+, SrTiO3:Pr3+, Mg2+, and SrTiO3:Pr3+, Al3+ phosphors are synthesized by a new sol-gel method. Crystal structure, spectral characteristics, and luminescence enhancement mechanism of the sample were studied by XRD and PL spectra. The results showed that after co-doped, SrTiO3:Pr3+ phosphor is single SrTiO3 cubic phase, the main emission front is located at 614 nm, corresponding to Pr3+ ions 1D2 3H4 transition emission. SrTiO3:Pr3+, Mg2+ and SrTiO3:Pr3+, Al3+ phosphor luminescence intensity is enhanced, but the main luminescence mechanism is not changed. Acceptor impurity = Mg2+, Al3+ will replace Ti bit after being doped into the crystal lattice to form charge compensation corresponding defect centers to reduce the demand of Sr2+ or Ti3+ vacancy. While Sr-doped Pr will make lattice distortion and transition energy of 4f-5d is very sensitive to crystal electric field changes around Pr atom. Doping different impurities will make electric field distribution around the icon have a different change. It increases energy transfer of 4f-5d transition and improves the luminous intensity of SrTiO3:Pr3+ red phosphor.
{"title":"Preparation of Compensation Ions Codoped SrTiO3:Pr3+ Red Phosphor with the Sol-Gel Method and Study of Its Luminescence Enhancement Mechanism","authors":"D. Guo, Xiaodong Zhang, J. Yun","doi":"10.1155/2014/674780","DOIUrl":"https://doi.org/10.1155/2014/674780","url":null,"abstract":"SrTiO3:Pr3+ is the most representative titanate matrix red phosphor for field emission display (FED). The red luminous efficiency of SrTiO3:Pr3+ will be greatly improved after the compensation ions codoping, so SrTiO3:Pr3+ red phosphor has been a research focus at home and abroad. SrTiO3:Pr3+, SrTiO3:Pr3+, Mg2+, and SrTiO3:Pr3+, Al3+ phosphors are synthesized by a new sol-gel method. Crystal structure, spectral characteristics, and luminescence enhancement mechanism of the sample were studied by XRD and PL spectra. The results showed that after co-doped, SrTiO3:Pr3+ phosphor is single SrTiO3 cubic phase, the main emission front is located at 614 nm, corresponding to Pr3+ ions 1D2 3H4 transition emission. SrTiO3:Pr3+, Mg2+ and SrTiO3:Pr3+, Al3+ phosphor luminescence intensity is enhanced, but the main luminescence mechanism is not changed. Acceptor impurity = Mg2+, Al3+ will replace Ti bit after being doped into the crystal lattice to form charge compensation corresponding defect centers to reduce the demand of Sr2+ or Ti3+ vacancy. While Sr-doped Pr will make lattice distortion and transition energy of 4f-5d is very sensitive to crystal electric field changes around Pr atom. Doping different impurities will make electric field distribution around the icon have a different change. It increases energy transfer of 4f-5d transition and improves the luminous intensity of SrTiO3:Pr3+ red phosphor.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2014-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/674780","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64606825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The principal objective of this paper is to demonstrate the capability of high speed measurement and acquisition equipment design and build in the laboratory at a very low cost. The presented architecture employees highly integrated market components eliminating thus the complexity of the hardware and software stack. The key element of the proposed system is a Hi-Speed USB to Serial/FIFO development module that is provided with full software and driver support for most popular operating systems. This module takes over every single task needed to get the data from the A/D to the user software gluelessly and transparently, solving this way the most difficult problem in data acquisition systems which is the fast and reliable communication with a host computer. Other ideas tested and included in this document offer Hall Effect measuring solutions using some excellent features and very low cost ICs widely available on the market today.
{"title":"Design and Build of an Electrical Machines’ High Speed Measurement System at Low Cost","authors":"Constantinos C. Kontogiannis, A. Safacas","doi":"10.1155/2014/745286","DOIUrl":"https://doi.org/10.1155/2014/745286","url":null,"abstract":"The principal objective of this paper is to demonstrate the capability of high speed measurement and acquisition equipment design and build in the laboratory at a very low cost. The presented architecture employees highly integrated market components eliminating thus the complexity of the hardware and software stack. The key element of the proposed system is a Hi-Speed USB to Serial/FIFO development module that is provided with full software and driver support for most popular operating systems. This module takes over every single task needed to get the data from the A/D to the user software gluelessly and transparently, solving this way the most difficult problem in data acquisition systems which is the fast and reliable communication with a host computer. Other ideas tested and included in this document offer Hall Effect measuring solutions using some excellent features and very low cost ICs widely available on the market today.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2014-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/745286","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64650670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.
{"title":"Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate","authors":"Gagandeep Singh, C. Goel","doi":"10.1155/2014/564613","DOIUrl":"https://doi.org/10.1155/2014/564613","url":null,"abstract":"In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/564613","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64547885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-09-07DOI: 10.1017/CBO9781316156148.003
D. Bhattacharya, N. Jha
Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.
{"title":"FinFETs: From Devices to Architectures","authors":"D. Bhattacharya, N. Jha","doi":"10.1017/CBO9781316156148.003","DOIUrl":"https://doi.org/10.1017/CBO9781316156148.003","url":null,"abstract":"Since Moore’s law driven scaling of planar MOSFETs \u0000faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing \u0000to the presence of multiple (two/three) gates, FinFETs/Trigate \u0000FETs are able to tackle short-channel effects (SCEs) better than \u0000conventional planar MOSFETs at deeply scaled technology nodes \u0000and thus enable continued transistor scaling. In this paper, we \u0000review research on FinFETs from the bottommost device level \u0000to the topmost architecture level. We survey different types of \u0000FinFETs, various possible FinFET asymmetries and their impact, \u0000and novel logic-level and architecture-level tradeoffs offered by \u0000FinFETs. We also review analysis and optimization tools that \u0000are available for characterizing FinFET devices, circuits, and \u0000architectures.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"21-55"},"PeriodicalIF":0.0,"publicationDate":"2014-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1017/CBO9781316156148.003","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"57120301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.
{"title":"Ultra-Low-Voltage Low-Power Bulk-Driven Quasi-Floating-Gate Operational Transconductance Amplifier","authors":"Ziad Alsibai, S. B. A. Dabbous","doi":"10.1155/2014/402840","DOIUrl":"https://doi.org/10.1155/2014/402840","url":null,"abstract":"A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2014-08-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/402840","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64480514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Image recognition with occlusion is one of the popular problems in pattern recognition. This paper partitions the images into some modules in two layers and the sparsity difference is used to evaluate the occluded modules. The final identification is processed on the unoccluded modules by sparse representation. Firstly, we partition the images into four blocks and sparse representation is performed on each block, so the sparsity of each block can be obtained; secondly, each block is partitioned again into two modules. Sparsity of each small module is calculated as the first step. Finally, the sparsity difference of small module with the corresponding block is used to detect the occluded modules; in this paper, the small modules with negative sparsity differences are considered as occluded modules. The identification is performed on the selected unoccluded modules by sparse representation. Experiments on the AR and Yale B database verify the robustness and effectiveness of the proposed method.
{"title":"Occluded Face Recognition Based on Double Layers Module Sparsity Difference","authors":"Shuhuan Zhao, Zheng-ping Hu","doi":"10.1155/2014/687827","DOIUrl":"https://doi.org/10.1155/2014/687827","url":null,"abstract":"Image recognition with occlusion is one of the popular problems in pattern recognition. This paper partitions the images into some modules in two layers and the sparsity difference is used to evaluate the occluded modules. The final identification is processed on the unoccluded modules by sparse representation. Firstly, we partition the images into four blocks and sparse representation is performed on each block, so the sparsity of each block can be obtained; secondly, each block is partitioned again into two modules. Sparsity of each small module is calculated as the first step. Finally, the sparsity difference of small module with the corresponding block is used to detect the occluded modules; in this paper, the small modules with negative sparsity differences are considered as occluded modules. The identification is performed on the selected unoccluded modules by sparse representation. Experiments on the AR and Yale B database verify the robustness and effectiveness of the proposed method.","PeriodicalId":7352,"journal":{"name":"Advances in Optoelectronics","volume":"2014 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2014-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1155/2014/687827","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"64616975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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