Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387623
P. Salmela, J. Antikainen, O. Silvén, J. Takala
Symbol detection with list sphere decoder (LSD) is an emerging technology targeted on multiple-input multiple-output (MIMO) telecommunication systems. The LSD algorithm requires maintaining a list of candidate symbols with shortest Euclidean distances to the received symbol. For energy efficiency, memory-based list is preferred over registers with long list lengths. In this paper, two hardware units for alleviating processing of such lists are presented. The list is stored as a heap in the memory and the proposed list updating units are incorporated with application specific processors. With presented principles, the number of clock cycles per list insertion gets very close to the theoretical lower bound with heap data structure.
{"title":"Memory-Based List Updating for List Sphere Decoders","authors":"P. Salmela, J. Antikainen, O. Silvén, J. Takala","doi":"10.1109/SIPS.2007.4387623","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387623","url":null,"abstract":"Symbol detection with list sphere decoder (LSD) is an emerging technology targeted on multiple-input multiple-output (MIMO) telecommunication systems. The LSD algorithm requires maintaining a list of candidate symbols with shortest Euclidean distances to the received symbol. For energy efficiency, memory-based list is preferred over registers with long list lengths. In this paper, two hardware units for alleviating processing of such lists are presented. The list is stored as a heap in the memory and the proposed list updating units are incorporated with application specific processors. With presented principles, the number of clock cycles per list insertion gets very close to the theoretical lower bound with heap data structure.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"32 5 1","pages":"633-638"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79780903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387630
Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, S. Goto, T. Ikenaga
H.264/AVC coding standard incorporates variable block size (VBS) motion estimation (ME) to improve the compression efficiency. For HDTV-1080p application, the massive computation and huge memory bandwidth by the large video frame size and the wide search range are two critical impediments to the real-time hardwired VB-SME engine design. In this paper, we present six techniques to circumvent these difficulties. First, the inter modes bellow 8 × 8 are eliminated in our design to reduce the hardware cost. Second, the low-pass filter based 4:1 down-sampling algorithm successfully reduces about 75% arithmetic computation in each search position. Third, the coarse to fine search scheme is made use of to reduce 25%-50% search candidates. Fourth, C+ memory organization is adopted to reduce the external IO bandwidth. Fifth, horizontal zigzag scan mode optimizes the search window memories. Finally, in circuit design, 4:2 compressor based CSA tree, multi-cycle path delay and 2 pipeline stage SAD tree techniques are utilized to improve the speed and reduce the hardware of each SAD tree. The hardwired integer motion estimation (IME) engine with 192 × 128 search range for HDTVl080p@30Hz is demonstrated in this paper. With TSMC 0.18¿m 1P6M CMOS technology, it is implemented with 485.7k gates standard cells and 327.68k bit on chip memories. The power dissipation is 729mw at 200MHz clock speed.
{"title":"32-Parallel SAD Tree Hardwired Engine for Variable Block Size Motion Estimation in HDTV1080P Real-Time Encoding Application","authors":"Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, S. Goto, T. Ikenaga","doi":"10.1109/SIPS.2007.4387630","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387630","url":null,"abstract":"H.264/AVC coding standard incorporates variable block size (VBS) motion estimation (ME) to improve the compression efficiency. For HDTV-1080p application, the massive computation and huge memory bandwidth by the large video frame size and the wide search range are two critical impediments to the real-time hardwired VB-SME engine design. In this paper, we present six techniques to circumvent these difficulties. First, the inter modes bellow 8 × 8 are eliminated in our design to reduce the hardware cost. Second, the low-pass filter based 4:1 down-sampling algorithm successfully reduces about 75% arithmetic computation in each search position. Third, the coarse to fine search scheme is made use of to reduce 25%-50% search candidates. Fourth, C+ memory organization is adopted to reduce the external IO bandwidth. Fifth, horizontal zigzag scan mode optimizes the search window memories. Finally, in circuit design, 4:2 compressor based CSA tree, multi-cycle path delay and 2 pipeline stage SAD tree techniques are utilized to improve the speed and reduce the hardware of each SAD tree. The hardwired integer motion estimation (IME) engine with 192 × 128 search range for HDTVl080p@30Hz is demonstrated in this paper. With TSMC 0.18¿m 1P6M CMOS technology, it is implemented with 485.7k gates standard cells and 327.68k bit on chip memories. The power dissipation is 729mw at 200MHz clock speed.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"28 1","pages":"675-680"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84260530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387516
Q. Qi, C. Chakrabarti
Motivated by the need for high throughput sphere decoding for multiple-input-multiple-output (MIMO) communication systems, we propose a parallel depth-first sphere decoding (PDSD) algorithm that provides the advantages of both parallel processing and rapid search space reduction. The PDSD algorithm is designed for efficient implementation on programmable multi-processor platforms. We investigate the trade-off between the throughput and computation overhead when the number of processing elements is 2, 4 and 8, for a 4 × 4 16-QAM system across a wide range of SNR conditions. Through simulation, we show that PDSD can offer significant throughput improvement without incurring substantial computation overhead by selecting the appropriate number of processing elements according to specific SNR conditions.
{"title":"Sphere Decoding for Multiprocessor Architectures","authors":"Q. Qi, C. Chakrabarti","doi":"10.1109/SIPS.2007.4387516","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387516","url":null,"abstract":"Motivated by the need for high throughput sphere decoding for multiple-input-multiple-output (MIMO) communication systems, we propose a parallel depth-first sphere decoding (PDSD) algorithm that provides the advantages of both parallel processing and rapid search space reduction. The PDSD algorithm is designed for efficient implementation on programmable multi-processor platforms. We investigate the trade-off between the throughput and computation overhead when the number of processing elements is 2, 4 and 8, for a 4 × 4 16-QAM system across a wide range of SNR conditions. Through simulation, we show that PDSD can offer significant throughput improvement without incurring substantial computation overhead by selecting the appropriate number of processing elements according to specific SNR conditions.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"17 1","pages":"50-55"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78192087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387534
Su-Hon Lin, M. Sheu, K. Wang, Jun-Jie Zhu, Si-Ying Chen
A novel Hybrid-Carry-Selection (HCS) approach used for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture which is mainly built by modified carry look-ahead adder (MCLA), carry prediction unit and simple multiplexer (MUX) is simple and regular for all n values. For VLSI implementation based on 180nm standard-cell technology, the HCS-based modulo 2n-1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the latest existing solutions. The layout area and clock rate for HCS-based 216-1 modular adder chip are 25709 um2 and 518MHz respectively.
{"title":"Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection","authors":"Su-Hon Lin, M. Sheu, K. Wang, Jun-Jie Zhu, Si-Ying Chen","doi":"10.1109/SIPS.2007.4387534","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387534","url":null,"abstract":"A novel Hybrid-Carry-Selection (HCS) approach used for deriving an efficient modulo 2n-1 addition is presented in this study. Its resulting adder architecture which is mainly built by modified carry look-ahead adder (MCLA), carry prediction unit and simple multiplexer (MUX) is simple and regular for all n values. For VLSI implementation based on 180nm standard-cell technology, the HCS-based modulo 2n-1 adder demonstrates the superiority in AreaxTime (AT) performance over those of the latest existing solutions. The layout area and clock rate for HCS-based 216-1 modular adder chip are 25709 um2 and 518MHz respectively.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"25 1","pages":"142-145"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87655381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387520
Jungeun Park, Yanghee Won, Sangwon Kang
In this paper, a vector quantization-block constrained trellis coded quantization (VQ-BCTCQ) is presented to quantize line spectrum frequency (LSF) parameters of the wideband speech codec. Both the predictive structure and safety-net concept are combined into VQ-BCTCQ to develop the predictive VQ-BCTCQ. The performance of this quantization is compared with that of the linear predictive coding (LPC) vector quantizer used in the AMR-WB codec, and reductions in spectral distortion (SD) and encoding complexity are demonstrated.
{"title":"Vector Quantization-Block Constrained Trellis Coded Quantization of Speech Line Spectral Frequencies","authors":"Jungeun Park, Yanghee Won, Sangwon Kang","doi":"10.1109/SIPS.2007.4387520","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387520","url":null,"abstract":"In this paper, a vector quantization-block constrained trellis coded quantization (VQ-BCTCQ) is presented to quantize line spectrum frequency (LSF) parameters of the wideband speech codec. Both the predictive structure and safety-net concept are combined into VQ-BCTCQ to develop the predictive VQ-BCTCQ. The performance of this quantization is compared with that of the linear predictive coding (LPC) vector quantizer used in the AMR-WB codec, and reductions in spectral distortion (SD) and encoding complexity are demonstrated.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"34 1","pages":"73-75"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82701389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387532
Lupin Chen, Jinjin He, Zhongfeng Wang
This paper presents a new low-power memory-efficient trace-back (TB) scheme for high constraint length Viterbi decoder (VD). With the trace-back modifications and path merging techniques, up to 50% memory read operations in the survivor memory unit (SMU) can be reduced. The memory size of SMU can be reduced by 33% and the decoding latency can be reduced by 14%. The simulation results show that compared to the conventional TB scheme, the performance loss of this scheme is negligible.
{"title":"Design of Low-Power Memory-Efficient Viterbi Decoder","authors":"Lupin Chen, Jinjin He, Zhongfeng Wang","doi":"10.1109/SIPS.2007.4387532","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387532","url":null,"abstract":"This paper presents a new low-power memory-efficient trace-back (TB) scheme for high constraint length Viterbi decoder (VD). With the trace-back modifications and path merging techniques, up to 50% memory read operations in the survivor memory unit (SMU) can be reduced. The memory size of SMU can be reduced by 33% and the decoding latency can be reduced by 14%. The simulation results show that compared to the conventional TB scheme, the performance loss of this scheme is negligible.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"80 1","pages":"132-135"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82365632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387632
Cheng-Chen Lin, Y. Hwang, Kwan-Hsun Tseng, Shao-Wen Chen
In the paper we propose a new lossless video coding system utilizing both Motion Compensated Temporal Filtering (MCTF) and integer wavelet transform techniques to explore data redundancy in both spatial and temporal domain, respectively. We elaborate the design issues such MCTF scheme, filter selection, group of picture size, wavelet coefficient coding, and develop an efficient coding system. Simulation results show that the proposed system using 1/3 filter has the best coding performance. The bit rate saving is over 20% compared with lossless still image coder such as JPEG-LS. The saving is also around 10% when compared with other wavelet based lossless video coder.
{"title":"Wavelet Based Lossless Video Compression Using Motion Compensated Temporal Filtering","authors":"Cheng-Chen Lin, Y. Hwang, Kwan-Hsun Tseng, Shao-Wen Chen","doi":"10.1109/SIPS.2007.4387632","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387632","url":null,"abstract":"In the paper we propose a new lossless video coding system utilizing both Motion Compensated Temporal Filtering (MCTF) and integer wavelet transform techniques to explore data redundancy in both spatial and temporal domain, respectively. We elaborate the design issues such MCTF scheme, filter selection, group of picture size, wavelet coefficient coding, and develop an efficient coding system. Simulation results show that the proposed system using 1/3 filter has the best coding performance. The bit rate saving is over 20% compared with lossless still image coder such as JPEG-LS. The saving is also around 10% when compared with other wavelet based lossless video coder.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"12 1","pages":"686-691"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78693164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387542
T. Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, A. Wu
A single-chip reconfigurable Color Doppler DSP engine is presented. It acts as the computation kernel of the high-frequency ultrasonic imaging system under development. The flexibility of the proposed DSP engine enables users to acquire sufficient information as needed, while the specificity of the hardware compared to general-purpose processors reduces cost and power consumption. This chip is implemented by TSMC 0.18 ¿m 1P6M CMOS technology. The die size is 2.94*2.94 mm2, and the power consumption is 184 mW when frame rate = 50, frame size = 512*256, and packet size = 8.
{"title":"Reconfigurable Color Doppler DSP Engine for High-Frequency Ultrasonic Imaging Systems","authors":"T. Yu, Shih-Yu Sun, Chih-Liang Ding, Pai-Chi Li, A. Wu","doi":"10.1109/SIPS.2007.4387542","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387542","url":null,"abstract":"A single-chip reconfigurable Color Doppler DSP engine is presented. It acts as the computation kernel of the high-frequency ultrasonic imaging system under development. The flexibility of the proposed DSP engine enables users to acquire sufficient information as needed, while the specificity of the hardware compared to general-purpose processors reduces cost and power consumption. This chip is implemented by TSMC 0.18 ¿m 1P6M CMOS technology. The die size is 2.94*2.94 mm2, and the power consumption is 184 mW when frame rate = 50, frame size = 512*256, and packet size = 8.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"109 1","pages":"187-192"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88052339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a quality scalable H.264/AVC baseline intra encoder with two hardware sharing mechanisms and three timing optimizing schemes. The proposed hardware sharing schemes share the common terms among intra prediction of different modes to reduce the hardware cost. The proposed timing optimizing schemes are used to improve the data throughput rate. The proposed design supports different clock rates of 26/33/47 MHz and 70/85 MHz to encode SD and HD720 video sequences with 30fps respectively with different qualities. According to a 0.13¿m CMOS technology, the proposed design costs 170K gates and 4.43 KB of internal SRAM at clock rate of 130MHz.
本文提出了一种具有两种硬件共享机制和三种时序优化方案的高质量可扩展H.264/AVC基线内编码器。所提出的硬件共享方案在不同模式的内部预测之间共享公共项，以降低硬件成本。采用所提出的时序优化方案提高了数据吞吐率。本设计支持26/33/47 MHz和70/85 MHz的不同时钟频率，分别对30fps的SD和HD720视频序列进行不同质量的编码。根据0.13 μ m CMOS技术，提出的设计成本为170K门和4.43 KB内部SRAM，时钟速率为130MHz。
{"title":"A Quality Scalable H.264/AVC Baseline Intra Encoder for High Definition Video Applicaitons","authors":"Chun-Hao Chang, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Jinn-Shyan Wang, Jiun-In Guo","doi":"10.1109/SIPS.2007.4387602","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387602","url":null,"abstract":"In this paper, we propose a quality scalable H.264/AVC baseline intra encoder with two hardware sharing mechanisms and three timing optimizing schemes. The proposed hardware sharing schemes share the common terms among intra prediction of different modes to reduce the hardware cost. The proposed timing optimizing schemes are used to improve the data throughput rate. The proposed design supports different clock rates of 26/33/47 MHz and 70/85 MHz to encode SD and HD720 video sequences with 30fps respectively with different qualities. According to a 0.13¿m CMOS technology, the proposed design costs 170K gates and 4.43 KB of internal SRAM at clock rate of 130MHz.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"16 1","pages":"521-526"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88544504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387616
Somya Rathi, Zhongfeng Wang
Embedded Block Coding with optimized Truncation (EBCOT) is a very computation and hardware intensive algorithm. It consumes more than 50 percent processing time of JPEG2000 encoding system. In this paper, we present a new algorithm and architecture of Block Coder based on serial mode in JPEG2000. It processes two bit planes simultaneously along with the encoding of four bits of a stripe concurrently. The architecture is capable of encoding in the causal mode of the standard. The paper also describes a variant of pass switching arithmetic encoder which further reduces the computation time of tier 1 with minimal increase in hardware. The proposed architecture not only saves memory by 4K bits but also significantly increases the throughput. It is estimated that the throughput can be increased by over 50%. In addition, the new architecture also reduces memory access.
{"title":"Fast EBCOT Encoder Architecture for JPEG 2000","authors":"Somya Rathi, Zhongfeng Wang","doi":"10.1109/SIPS.2007.4387616","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387616","url":null,"abstract":"Embedded Block Coding with optimized Truncation (EBCOT) is a very computation and hardware intensive algorithm. It consumes more than 50 percent processing time of JPEG2000 encoding system. In this paper, we present a new algorithm and architecture of Block Coder based on serial mode in JPEG2000. It processes two bit planes simultaneously along with the encoding of four bits of a stripe concurrently. The architecture is capable of encoding in the causal mode of the standard. The paper also describes a variant of pass switching arithmetic encoder which further reduces the computation time of tier 1 with minimal increase in hardware. The proposed architecture not only saves memory by 4K bits but also significantly increases the throughput. It is estimated that the throughput can be increased by over 50%. In addition, the new architecture also reduces memory access.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"31 1","pages":"595-599"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75358788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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