Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387557
C. Spagnol, W. Marnane, E. Popovici
Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.
{"title":"FPGA Implementations of LDPC over GF(2m) Decoders","authors":"C. Spagnol, W. Marnane, E. Popovici","doi":"10.1109/SIPS.2007.4387557","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387557","url":null,"abstract":"Low Density Parity Check (LDPC) codes over GF(2m) are an extension of binary LDPC codes that have not been studied extensively. Performances of GF(2m) LDPC codes have been shown to be higher than binary LDPC codes, but the complexity of the encoders/decoders increases. Hence there iS a substantial lack of hardware implementations for LDPC over GF(2m) codes. This paper presents a FPGA serial implementation of two decoding algorithms for LDPC over GF(2m). The results prove that the implementation of LDPC over GF(2m) decoding is feasible and the extra complexity of the decoder is balanced by the superior performance of GF(2m) LDPC codes.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"15 1","pages":"273-278"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81134076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387563
Q. Du, Wei Zhu, J. Fowler
Remotely sensed hyperspectral imagery has vast data volume, for which data compression is a necessary processing step. Spectral decorrelation is critical to successful hyperspectral-image compression. Principal component analysis (PCA) is well-known for its superior performance in data decorrelation, and it has been demonstrated that using PCA for spectral decorrelation can yield rate-distortion and data-analysis performance superior to other widely used approaches, such as the discrete wavelet transform (DWT). However, PCA is a data-dependent transform, and its complicated implementation in hardware hinders its use in practice. In this paper, schemes for low-complexity PCA are discussed, including spatial down-sampling, the use of non-zero mean data, and the adoption of a simple PCA neural-network. System-design issues are also investigated. Experimental results focused on the fidelity of pixel values and pixel spectral signatures demonstrate that the proposed schemes achieve a trade-off between compression performance and system-design complexity.
{"title":"Implementation of Low-Complexity Principal Component Analysis for Remotely Sensed Hyperspectral-Image Compression","authors":"Q. Du, Wei Zhu, J. Fowler","doi":"10.1109/SIPS.2007.4387563","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387563","url":null,"abstract":"Remotely sensed hyperspectral imagery has vast data volume, for which data compression is a necessary processing step. Spectral decorrelation is critical to successful hyperspectral-image compression. Principal component analysis (PCA) is well-known for its superior performance in data decorrelation, and it has been demonstrated that using PCA for spectral decorrelation can yield rate-distortion and data-analysis performance superior to other widely used approaches, such as the discrete wavelet transform (DWT). However, PCA is a data-dependent transform, and its complicated implementation in hardware hinders its use in practice. In this paper, schemes for low-complexity PCA are discussed, including spatial down-sampling, the use of non-zero mean data, and the adoption of a simple PCA neural-network. System-design issues are also investigated. Experimental results focused on the fidelity of pixel values and pixel spectral signatures demonstrate that the proposed schemes achieve a trade-off between compression performance and system-design complexity.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"70 1","pages":"307-312"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87345402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387553
T. Koh, B. Ng, Y. Guan, T. Li
A memory-based, pipelined, serial architecture is developed for implementing product accumulate codes in field programmable gate arrays. A three-stage pipeline structure is exploited on the min-sum decoding algorithm to achieve full utilization of instantiated resources, to reduce latency, and to increase throughput while keeping the performance degradation minimal. Different types of interleavers are investigated and the quadratic permutation polynomial based inter-leaver is shown to be the best choice in terms of implementation cost, reconfigurability and bit error rate performance. The proposed decoder implemented in Xilinx 2v3000FG676-4 chips is capable of processing one full decoding iteration for 1 encoded bit every clock. Thus regardless of the block size, throughput will be determined only by the number of iterations done while latency is linear to block size.
{"title":"Reconfigurable FPGA Implementation of Product Accumulate Codes","authors":"T. Koh, B. Ng, Y. Guan, T. Li","doi":"10.1109/SIPS.2007.4387553","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387553","url":null,"abstract":"A memory-based, pipelined, serial architecture is developed for implementing product accumulate codes in field programmable gate arrays. A three-stage pipeline structure is exploited on the min-sum decoding algorithm to achieve full utilization of instantiated resources, to reduce latency, and to increase throughput while keeping the performance degradation minimal. Different types of interleavers are investigated and the quadratic permutation polynomial based inter-leaver is shown to be the best choice in terms of implementation cost, reconfigurability and bit error rate performance. The proposed decoder implemented in Xilinx 2v3000FG676-4 chips is capable of processing one full decoding iteration for 1 encoded bit every clock. Thus regardless of the block size, throughput will be determined only by the number of iterations done while latency is linear to block size.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"92 1","pages":"249-254"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76801524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387543
Tae-Hwan Kim, I. Park
Targeting IEEE 802.16d systems, this paper presents a new approach for coarse time synchronization and carrier frequency offset estimation. In contrast to the previous architecture that usually computes both of them jointly within a unified auto-correlator, the proposed one performs them separately to achieve more reliable frequency synchronization and to reduce the overall hardware complexity by optimizing them individually. Experimental results show that the proposed architecture leads to better frequency synchronization compared to the previous joint estimation, and is more efficient in both respects of silicon area and power consumption.
{"title":"Two-Step Aprroach for Coarse Time Synchronization and Frequency Offset Estimation for IEEE 802.16D Systems","authors":"Tae-Hwan Kim, I. Park","doi":"10.1109/SIPS.2007.4387543","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387543","url":null,"abstract":"Targeting IEEE 802.16d systems, this paper presents a new approach for coarse time synchronization and carrier frequency offset estimation. In contrast to the previous architecture that usually computes both of them jointly within a unified auto-correlator, the proposed one performs them separately to achieve more reliable frequency synchronization and to reduce the overall hardware complexity by optimizing them individually. Experimental results show that the proposed architecture leads to better frequency synchronization compared to the previous joint estimation, and is more efficient in both respects of silicon area and power consumption.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"110 1","pages":"193-198"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74760453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387522
Xinyi Wang, Tingzhi Shen, Wei-jiang Wang
This paper describes a novel structure and its implementation method of a long-distance network echo canceller. The proposed NEC system copes with double talking situations by using a modified double-talk detector. An improved adaptive filter structure is also presented based on algorithm delay estimator. To deal with residual echo after filtering a nonlinear processor is employed. The resulting algorithm enables long-distance network echo cancellation with low computational requirements. It reached grater echo return loss enhancement and shows faster convergences speed as compared with conventional network echo canceller.
{"title":"A Novel Real-Time Implementation for Network Echo Cancellation System","authors":"Xinyi Wang, Tingzhi Shen, Wei-jiang Wang","doi":"10.1109/SIPS.2007.4387522","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387522","url":null,"abstract":"This paper describes a novel structure and its implementation method of a long-distance network echo canceller. The proposed NEC system copes with double talking situations by using a modified double-talk detector. An improved adaptive filter structure is also presented based on algorithm delay estimator. To deal with residual echo after filtering a nonlinear processor is employed. The resulting algorithm enables long-distance network echo cancellation with low computational requirements. It reached grater echo return loss enhancement and shows faster convergences speed as compared with conventional network echo canceller.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"27 1","pages":"82-85"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78648300","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387608
Young Han Lee, H. Kim
In this paper, we propose a bandwidth extension (BWE) algorithm for a low-bit-rate narrowband CELP coder using a spectral envelope sharing approach to develop a wideband speech coder. The developed wideband speech coder, referred to here as the BWE coder, is constructed using an embedded structure by adding an enhancement layer to the narrowband CELP coder. To minimize the bit-rate increase caused by the enhancement layer, the proposed BWE coder shares the spectral envelope and excitation parameters both with the narrowband CELP coder and the enhancement layer. In this paper, we choose G.729EV layer 2 as the baseline narrowband speech coder, and mel-frequency cepstral coefficients (MFCCs) are used to reconstruct the higher frequency components at the enhancement layer. By doing this, the bit-rate of the proposed BWE coder is found to be 12.7 kbit/s, just 0.7 kbit/s higher than that of G.729EV layer 2. It is also demonstrated from a MUSHRA test with audio signals from four different music genres, that the BWE coder gives better quality than G.729EV layer 2 and comparable quality to G.729EV layer 3, corresponding to an overall bit-rate reduction of 1.3 kbit/s.
{"title":"Bandwidth Extension of a Narrowband Speech Coder for Music Streaming Services Over IP Networks","authors":"Young Han Lee, H. Kim","doi":"10.1109/SIPS.2007.4387608","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387608","url":null,"abstract":"In this paper, we propose a bandwidth extension (BWE) algorithm for a low-bit-rate narrowband CELP coder using a spectral envelope sharing approach to develop a wideband speech coder. The developed wideband speech coder, referred to here as the BWE coder, is constructed using an embedded structure by adding an enhancement layer to the narrowband CELP coder. To minimize the bit-rate increase caused by the enhancement layer, the proposed BWE coder shares the spectral envelope and excitation parameters both with the narrowband CELP coder and the enhancement layer. In this paper, we choose G.729EV layer 2 as the baseline narrowband speech coder, and mel-frequency cepstral coefficients (MFCCs) are used to reconstruct the higher frequency components at the enhancement layer. By doing this, the bit-rate of the proposed BWE coder is found to be 12.7 kbit/s, just 0.7 kbit/s higher than that of G.729EV layer 2. It is also demonstrated from a MUSHRA test with audio signals from four different music genres, that the BWE coder gives better quality than G.729EV layer 2 and comparable quality to G.729EV layer 3, corresponding to an overall bit-rate reduction of 1.3 kbit/s.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"37 1","pages":"552-555"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79059957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387549
Zhen Mao, Yun He
Typical VLC schemes use fixed Huffman tables, thus the coding efficiency is far from the real Huffman coder. By employing multiple fixed code tables, the performance should be increased and approach the ideal Huffman coder. Since the fixed table VLC method is not the "minimum redundant" one, there is a believe that the redundancy between symbols still exists and there should be methods which could further remove it, and the possible way is encoding concatenation of codewords together, i.e., applying a post-processing on the VLC code streams. Some models are given to describe how much equivalent redundancy exist within the VLC code streams by using the channel coding concepts. Starting from those models, we introduce some modifications to evaluate the inter symbol redundancy for source coding. The estimation based on the models for the redundancies of H.263 and AVS are shown, which may lead us to understand the post-processing efficiency could achieve.
{"title":"Redundancy Analysis for Variable Length Coding","authors":"Zhen Mao, Yun He","doi":"10.1109/SIPS.2007.4387549","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387549","url":null,"abstract":"Typical VLC schemes use fixed Huffman tables, thus the coding efficiency is far from the real Huffman coder. By employing multiple fixed code tables, the performance should be increased and approach the ideal Huffman coder. Since the fixed table VLC method is not the \"minimum redundant\" one, there is a believe that the redundancy between symbols still exists and there should be methods which could further remove it, and the possible way is encoding concatenation of codewords together, i.e., applying a post-processing on the VLC code streams. Some models are given to describe how much equivalent redundancy exist within the VLC code streams by using the channel coding concepts. Starting from those models, we introduce some modifications to evaluate the inter symbol redundancy for source coding. The estimation based on the models for the redundancies of H.263 and AVS are shown, which may lead us to understand the post-processing efficiency could achieve.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"66 1","pages":"228-231"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74323955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387595
Christophe Lucarz, M. Mattavelli, J. Thomas-Kerr, J. Janneck
Multimedia coding technology, after about 20 years of active research, has delivered a rich variety of different and complex coding algorithms. Selecting an appropriate subset of these algorithms would, in principle, enable a designer to produce the codec supporting any desired functionality as well as any desired trade-off between compression performance and implementation complexity. Currently, interoperability demands that this selection process be hard-wired into the normative descriptions of the codec, or at a lower level, into a predefined number of choices, known as profiles, codified within each standard specification. This paper presents an alternative paradigm for codec deployment that is currently under development by MPEG, known as Reconfigurable Media Coding (RMC). Using the RMC framework, arbitrary combinations of fundamental algorithms may be assembled, without predefined standardization, because everything necessary for specifying the decoding process is delivered alongside the content itself. This side-information consists of a description of the bitstream syntax, as well as a description of the decoder configuration. Decoder configuration information is provided as a description of the interconnections between algorithmic blocks. The approach has been validated by development of an RMC format that matches MPEG-4 Video, and then extending the format by adding new chroma-subsampling patterns.
{"title":"Reconfigurable Media Coding: A New Specification Model for Multimedia Coders","authors":"Christophe Lucarz, M. Mattavelli, J. Thomas-Kerr, J. Janneck","doi":"10.1109/SIPS.2007.4387595","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387595","url":null,"abstract":"Multimedia coding technology, after about 20 years of active research, has delivered a rich variety of different and complex coding algorithms. Selecting an appropriate subset of these algorithms would, in principle, enable a designer to produce the codec supporting any desired functionality as well as any desired trade-off between compression performance and implementation complexity. Currently, interoperability demands that this selection process be hard-wired into the normative descriptions of the codec, or at a lower level, into a predefined number of choices, known as profiles, codified within each standard specification. This paper presents an alternative paradigm for codec deployment that is currently under development by MPEG, known as Reconfigurable Media Coding (RMC). Using the RMC framework, arbitrary combinations of fundamental algorithms may be assembled, without predefined standardization, because everything necessary for specifying the decoding process is delivered alongside the content itself. This side-information consists of a description of the bitstream syntax, as well as a description of the decoder configuration. Decoder configuration information is provided as a description of the interconnections between algorithmic blocks. The approach has been validated by development of an RMC format that matches MPEG-4 Video, and then extending the format by adding new chroma-subsampling patterns.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"41 1","pages":"481-486"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82047509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387564
T. Asakura, S. Imamura, M. Minami
This research is concerned with image recognition for a robot vision detecting target objects by using Chaotic Search in model-based matching. As a nonlinear dynamical system to generate a chaos, BVP model is treated, which shows the behavior of neurons in biological system. This model has the "edge of chaos", which exists on the boundary between a periodic solution and a chaos solution. This edge of chaos is an important area to maintain an organization to be flexible. In this research, the Chaotic Search is applied to image recognition utilizing the edge of chaos. First, the occurrence of chaos in BVP model is examined using the Lyapunov exponent. Second, in order to perform image recognition, we propose a method of Chaotic Search in which it can distinguish the target object from surroundings effectively, using a method of pattern matching. Finally, through two illustrative examples, the effectiveness of Chaotic Search is verified for both static and dynamic targets.
{"title":"Vision Recognition System by Using Chaotic Search","authors":"T. Asakura, S. Imamura, M. Minami","doi":"10.1109/SIPS.2007.4387564","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387564","url":null,"abstract":"This research is concerned with image recognition for a robot vision detecting target objects by using Chaotic Search in model-based matching. As a nonlinear dynamical system to generate a chaos, BVP model is treated, which shows the behavior of neurons in biological system. This model has the \"edge of chaos\", which exists on the boundary between a periodic solution and a chaos solution. This edge of chaos is an important area to maintain an organization to be flexible. In this research, the Chaotic Search is applied to image recognition utilizing the edge of chaos. First, the occurrence of chaos in BVP model is examined using the Lyapunov exponent. Second, in order to perform image recognition, we propose a method of Chaotic Search in which it can distinguish the target object from surroundings effectively, using a method of pattern matching. Finally, through two illustrative examples, the effectiveness of Chaotic Search is verified for both static and dynamic targets.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"81 1","pages":"313-318"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76845283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387619
Jung-Yang Kao
This paper proposes a method to address the computation load and memory access frequency problems during interpolation for video processing (coding or decoding). The motion compensation process in video processing is computationally intensive and takes considerable computation time of the system, while the interpolation step in the process incurs the heaviest computation load. Exploiting the characteristics of strong correlation between natural images in a frame, this paper proposes a patented method that stores the computed interpolation values and then manages the values using memory address rotation (MAR) technique to decrease the computation load and memory access frequency.
{"title":"Method for Decreasing Computation Load and Memory Access Frequency during Interpolation for Video Coding","authors":"Jung-Yang Kao","doi":"10.1109/SIPS.2007.4387619","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387619","url":null,"abstract":"This paper proposes a method to address the computation load and memory access frequency problems during interpolation for video processing (coding or decoding). The motion compensation process in video processing is computationally intensive and takes considerable computation time of the system, while the interpolation step in the process incurs the heaviest computation load. Exploiting the characteristics of strong correlation between natural images in a frame, this paper proposes a patented method that stores the computed interpolation values and then manages the values using memory address rotation (MAR) technique to decrease the computation load and memory access frequency.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2 1","pages":"610-614"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76995154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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