Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387546
Sangwon Seo, T. Mudge, Yuming Zhu, C. Chakrabarti
Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.
{"title":"Design and Analysis of LDPC Decoders for Software Defined Radio","authors":"Sangwon Seo, T. Mudge, Yuming Zhu, C. Chakrabarti","doi":"10.1109/SIPS.2007.4387546","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387546","url":null,"abstract":"Low Density Parity Check (LDPC) codes are one of the most promising error correction codes that are being adopted by many wireless standards. This paper presents a case study for a scalable LDPC decoder supporting multiple code rates and multiple block sizes on a software defined radio (SDR) platform. Since technology scaling alone is not sufficient for current SDR architectures to meet the requirements of the next generation wireless standards, this paper presents three techniques to improve the throughput performance. The techniques are use of data path accelerators, addition of memory units and addition of a few assembly instructions. The proposed LDPC decoder implementation achieved 30.4 Mbps decoding throughput for the n=2304 and R=5/6 LDPC code outlined in the IEEE 802.16e standard.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"80 1","pages":"210-215"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75388031","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387551
Haisheng Liu, J. Diguet, C. Jégo, M. Jézéquel, E. Boutillon
In the field of mobile communications, the energy issue of a turbo decoder becomes an equivalent constraint as through-put and performance. This paper describes a technique to reduce the internal bitwidth of the state metrics, and hence, to decrease the entire energy dissipation of a turbo decoder. This approach is based on the saturation of the state metrics. Two cases are investigated: saturation outside the ACS recursion loop and saturation inside the ACS recursion loop. The targeted system is the Universal Mobile Telecommunications System (UMTS) with an 8-state turbo decoder using the Max-Log-MAP algorithm. When received symbols and extrinsic informations are respectively 4-bit and 6-bit quantized, the internal bitwidth of the state metrics can be reduced from 7 bits downto 4 bits. This reduction is paid by a loss of 0.1 dB at a Bit Error Rate (BER) of 1-6. In addition, when 40 SISO decoders perform in parallel, the proposed optimization yields to a reduction of memory area by 10% and leads to an energy reduction of 24% for a 70 nm technology.
{"title":"Energy Efficient Turbo Decoder with Reduced State Metric Quantization","authors":"Haisheng Liu, J. Diguet, C. Jégo, M. Jézéquel, E. Boutillon","doi":"10.1109/SIPS.2007.4387551","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387551","url":null,"abstract":"In the field of mobile communications, the energy issue of a turbo decoder becomes an equivalent constraint as through-put and performance. This paper describes a technique to reduce the internal bitwidth of the state metrics, and hence, to decrease the entire energy dissipation of a turbo decoder. This approach is based on the saturation of the state metrics. Two cases are investigated: saturation outside the ACS recursion loop and saturation inside the ACS recursion loop. The targeted system is the Universal Mobile Telecommunications System (UMTS) with an 8-state turbo decoder using the Max-Log-MAP algorithm. When received symbols and extrinsic informations are respectively 4-bit and 6-bit quantized, the internal bitwidth of the state metrics can be reduced from 7 bits downto 4 bits. This reduction is paid by a loss of 0.1 dB at a Bit Error Rate (BER) of 1-6. In addition, when 40 SISO decoders perform in parallel, the proposed optimization yields to a reduction of memory area by 10% and leads to an energy reduction of 24% for a 70 nm technology.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"260 3","pages":"237-242"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/SIPS.2007.4387551","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72401106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387592
K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, Xiaobai Sun, Jungsub Kim, P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan
A hardware efficient approach is introduced for elementary function evaluations in certain structured matrix computations. It is a comprehensive approach that utilizes lookup tables for compactness, employs interpolations with adders and multipliers for their adaptivity to non-tabulated values and, more distinctively, exploits the function properties and the matrix structures to claim better control over numerical dynamic ranges. We demonstrate the effectiveness of the approach with simulation and synthesis results on evaluating, in particular, the cosine function, the exponential function and the zero-order Bessel function of the first kind.
{"title":"Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations","authors":"K. Sobti, L. Deng, C. Chakrabarti, N. Pitsianis, Xiaobai Sun, Jungsub Kim, P. Mangalagiri, K. Irick, M. Kandemir, N. Vijaykrishnan","doi":"10.1109/SIPS.2007.4387592","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387592","url":null,"abstract":"A hardware efficient approach is introduced for elementary function evaluations in certain structured matrix computations. It is a comprehensive approach that utilizes lookup tables for compactness, employs interpolations with adders and multipliers for their adaptivity to non-tabulated values and, more distinctively, exploits the function properties and the matrix structures to claim better control over numerical dynamic ranges. We demonstrate the effectiveness of the approach with simulation and synthesis results on evaluating, in particular, the cosine function, the exponential function and the zero-order Bessel function of the first kind.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"178 1","pages":"463-468"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77834943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387550
Chunguang Liu, C. Ta, Stephan Weiss
Oversampled filter banks (OSFBs) have recently been considered for channel coding since their redundancy introduced into the transmitted signal permits more freedom in the design of joint transmitter and receiver. Further specifically, they can be exploited to transmit over low noise subspaces or even mitigate dispersiveness of the channel. In this paper we propose a joint precoding and equalisation design using OSFBs, which find a compromise between transmitting over the low-noise subspace of channel noise's polyphase components, and the high-gain subspace of the channel's polyphase components. Polynomial building blocks are permitted and the minimisation of the mean square error (MSE) at the receiver output is achieved. We describe the design, and highlight the communalities and differences of this approach to existing methods. Simulation results show the benefit of the proposed system design compared to existing design approaches.
{"title":"Joint Precoding and Equalisation Design Using Oversampled Filter Banks for Dispersive Channels with Correlated Noise","authors":"Chunguang Liu, C. Ta, Stephan Weiss","doi":"10.1109/SIPS.2007.4387550","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387550","url":null,"abstract":"Oversampled filter banks (OSFBs) have recently been considered for channel coding since their redundancy introduced into the transmitted signal permits more freedom in the design of joint transmitter and receiver. Further specifically, they can be exploited to transmit over low noise subspaces or even mitigate dispersiveness of the channel. In this paper we propose a joint precoding and equalisation design using OSFBs, which find a compromise between transmitting over the low-noise subspace of channel noise's polyphase components, and the high-gain subspace of the channel's polyphase components. Polynomial building blocks are permitted and the minimisation of the mean square error (MSE) at the receiver output is achieved. We describe the design, and highlight the communalities and differences of this approach to existing methods. Simulation results show the benefit of the proposed system design compared to existing design approaches.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"284 1","pages":"232-236"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79463432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387512
Kai-Yuan Jheng, Yuan-Jyue Chen, A. Wu
Linear amplifier with nonlinear components (LINC) is a power amplifier (PA) linearization technique which offers both high PA efficiency and high linearity of wireless transmitters. But at the output stage, LINC uses a power combiner which results in low system efficiency. To solve this problem, we propose a multilevel out-phasing (MOP) scheme and a corresponding architecture, multilevel LINC (MLINC), to increase power combiner efficiency of wireless transmitters. Under WCDMA system linearity requirements, we demonstrate the 3-level MLINC as a design example which enhances power combiner efficiency from 44.5% to 75.5%.
{"title":"Multilevel Linc System Design for Power Efficiency Enhancement","authors":"Kai-Yuan Jheng, Yuan-Jyue Chen, A. Wu","doi":"10.1109/SIPS.2007.4387512","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387512","url":null,"abstract":"Linear amplifier with nonlinear components (LINC) is a power amplifier (PA) linearization technique which offers both high PA efficiency and high linearity of wireless transmitters. But at the output stage, LINC uses a power combiner which results in low system efficiency. To solve this problem, we propose a multilevel out-phasing (MOP) scheme and a corresponding architecture, multilevel LINC (MLINC), to increase power combiner efficiency of wireless transmitters. Under WCDMA system linearity requirements, we demonstrate the 3-level MLINC as a design example which enhances power combiner efficiency from 44.5% to 75.5%.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"104 1","pages":"31-34"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79610499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387540
G. Pastuszak
The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binarization unit, which is a part of the last stage of the video coder. The module supports CABAC and CAVLC modes and conforms to H.264/AVC High Profile. The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. For both modes, the architecture achieves the similar throughput able to support HDTV.
硬件视频编码器的效率取决于处理路径中嵌入的所有模块。本文介绍了H.264/AVC二值化单元的结构，该单元是视频编码器最后阶段的一部分。该模块支持CABAC和CAVLC模式，符合H.264/AVC High Profile标准。由于两种编码模式共享相同的逻辑和存储元素，因此该体系结构节省了大量硬件资源。对于这两种模式，该架构实现了相似的吞吐量，能够支持HDTV。
{"title":"Architecture Design of the Double-Mode Binarization for High-Profile H.264/AVC Compression","authors":"G. Pastuszak","doi":"10.1109/SIPS.2007.4387540","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387540","url":null,"abstract":"The efficiency of hardware video encoders depends on all modules embedded in the processing path. This paper presents the architecture of the H.264/AVC binarization unit, which is a part of the last stage of the video coder. The module supports CABAC and CAVLC modes and conforms to H.264/AVC High Profile. The architecture saves a considerable amount of hardware resources since two coding modes share the same logic and storage elements. For both modes, the architecture achieves the similar throughput able to support HDTV.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"2640 1","pages":"175-180"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81407257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387582
O. Ndili, T. Ogunfunmi
Recently, in [1] we developed a theoretical frame-work for achieving the maximum possible speed on a constrained digital channel with a finite alphabet. We obtained the capacity of the channel numerically, using a constrained Blahut-Arimoto algorithm which incorporated an average power constraint P at the transmitter. Our simulations showed that under certain conditions the capacity approached very closely, the Shannon bound. We also showed the maximizing input distributions. In this paper, the theoretical framework developed in [1] is applied to a practical example, the downstream channel of an asymmetric digital subscriber loop (ADSL), connection where the inputs to the channel are quantized and the outputs are real. We test how closely we approach the minimum configuration bound for this Channel under a practical noise environment.
{"title":"Achieving Maximum Possible Download Speed on ADSL Systems","authors":"O. Ndili, T. Ogunfunmi","doi":"10.1109/SIPS.2007.4387582","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387582","url":null,"abstract":"Recently, in [1] we developed a theoretical frame-work for achieving the maximum possible speed on a constrained digital channel with a finite alphabet. We obtained the capacity of the channel numerically, using a constrained Blahut-Arimoto algorithm which incorporated an average power constraint P at the transmitter. Our simulations showed that under certain conditions the capacity approached very closely, the Shannon bound. We also showed the maximizing input distributions. In this paper, the theoretical framework developed in [1] is applied to a practical example, the downstream channel of an asymmetric digital subscriber loop (ADSL), connection where the inputs to the channel are quantized and the outputs are real. We test how closely we approach the minimum configuration bound for this Channel under a practical noise environment.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"8 1","pages":"407-411"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82317648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387633
Tian-sheng Tang, Jin Wang, Yunqiang Liu, Yizhi Gao, Songyu Yu
Whole-frame loss of the compressed video is very common in transmission over error-prone networks since each coded picture is usually packetized into one single packet in order to reduce the bitstream overhead for transmission. In this paper we present an adaptive frame recovery algorithm which innovatively introduces the three-dimensional recursive search (3DRS) motion estimation method into fram reovr (FR), and dynamically selects between 3DRS based recovery and motion vector copy (MVC) based recovery according to the statistics of motion activity of previous frames. If the motion activity of the frame is large, we adopt 3DRS-based frame recovery. Otherwise MVC-based FR is used. For the former method, we first perform the modfief 3DRS to re-estimate the motion vectors (MVs) of the previous frame considering that the available motion information of previous frames is not close to the true motion trajectory. Then the MVs are extrapolated and refined as the MVs of the lost frame. The missing frame is recovered using motion compensation. For MVC-based FR, motion information of previous frames, derived from the decoder is reused. Experimental results show that our proposed solutions can achieve significant improvements in both PSNR and visual quality.
{"title":"Adaptive frame recovery based on motion activity","authors":"Tian-sheng Tang, Jin Wang, Yunqiang Liu, Yizhi Gao, Songyu Yu","doi":"10.1109/SIPS.2007.4387633","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387633","url":null,"abstract":"Whole-frame loss of the compressed video is very common in transmission over error-prone networks since each coded picture is usually packetized into one single packet in order to reduce the bitstream overhead for transmission. In this paper we present an adaptive frame recovery algorithm which innovatively introduces the three-dimensional recursive search (3DRS) motion estimation method into fram reovr (FR), and dynamically selects between 3DRS based recovery and motion vector copy (MVC) based recovery according to the statistics of motion activity of previous frames. If the motion activity of the frame is large, we adopt 3DRS-based frame recovery. Otherwise MVC-based FR is used. For the former method, we first perform the modfief 3DRS to re-estimate the motion vectors (MVs) of the previous frame considering that the available motion information of previous frames is not close to the true motion trajectory. Then the MVs are extrapolated and refined as the MVs of the lost frame. The missing frame is recovered using motion compensation. For MVC-based FR, motion information of previous frames, derived from the decoder is reused. Experimental results show that our proposed solutions can achieve significant improvements in both PSNR and visual quality.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"16 1","pages":"692-697"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82884024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387604
K. Lin
Microscopic auto focusing (AF) is an important technique in applications for precision measurement and inspection. This paper presents an AF algorithm composed of three stages (i.e., initial search for direction, a rough search, and a fine search). Sophisticated decision makings and recovery mechanism are built in the algorithm to enhance the overall performance. It is illustrated that a previous measure of image focus value (FV) could be subject to low signal-to-noise ratio. The variance of sub-windowing measures is proposed to enhance the ratio and improve the AF reliability and accuracy. Experimental tests have been widely conducted. Selected results of the tests are included in this paper. Good overshoot responses are achieved via adaptation of the AF step sizes. The steady-state focusing errors are within the tolerance of depth of focus for each lens. Robustness against undesired local peak and abnormal conditions is enhanced by a designated significant level of FV and an integrated recovery mechanism. The AF time spreads over the range of 400-1700 ms and it is less than 1000 ms in average.
{"title":"Auto Focusing Under Microscopic Views","authors":"K. Lin","doi":"10.1109/SIPS.2007.4387604","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387604","url":null,"abstract":"Microscopic auto focusing (AF) is an important technique in applications for precision measurement and inspection. This paper presents an AF algorithm composed of three stages (i.e., initial search for direction, a rough search, and a fine search). Sophisticated decision makings and recovery mechanism are built in the algorithm to enhance the overall performance. It is illustrated that a previous measure of image focus value (FV) could be subject to low signal-to-noise ratio. The variance of sub-windowing measures is proposed to enhance the ratio and improve the AF reliability and accuracy. Experimental tests have been widely conducted. Selected results of the tests are included in this paper. Good overshoot responses are achieved via adaptation of the AF step sizes. The steady-state focusing errors are within the tolerance of depth of focus for each lens. Robustness against undesired local peak and abnormal conditions is enhanced by a designated significant level of FV and an integrated recovery mechanism. The AF time spreads over the range of 400-1700 ms and it is less than 1000 ms in average.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"365 1","pages":"533-538"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81954123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-21DOI: 10.1109/SIPS.2007.4387509
M. Sima, M. McGuire
OFDM demodulation under fast fading radio channels is very computationally demanding, making the implementation of Software Defined Radio (SDR) solutions problematic. A sub-optimal demodulation algorithm based on QR decomposition of blocks of the channel transfer matrix offers near optimal performance at lower computational cost, but hardware support is still needed. We first propose a COordinate Rotation DIgital Computer (CORDIC) rotator in reconfigurable hardware to expose and then exploit at software level the intra-block paralellism of the QR decomposition. In particular, we show that although the rotator is deeply pipelined, the scale factor inherent to CORDIC algorithm can still be distributedly compensated throughout the pipeline at no additional cycle time penalty. Then, for a Nios II processor augmented with a Reconfigurable Functional Unit (RFU) that incorporates the proposed CORDIC rotator, we also propose a computing scenario that keeps all the data to be processed inside the RFU, to minimize overhead of the data trafic between the Register File and the CORDIC rotator. Overall, we show that OFDM demodulation under fast-fading can be performed in fixed-point arithmetic and in real-time on a Nios II reconfigurable embedded system, proving that an SDR solution for OFDM demodulation under fast fading is possible.
{"title":"Embedded Reconfigurable Solution for OFDM Detection Over Fast Fading Radio Channels","authors":"M. Sima, M. McGuire","doi":"10.1109/SIPS.2007.4387509","DOIUrl":"https://doi.org/10.1109/SIPS.2007.4387509","url":null,"abstract":"OFDM demodulation under fast fading radio channels is very computationally demanding, making the implementation of Software Defined Radio (SDR) solutions problematic. A sub-optimal demodulation algorithm based on QR decomposition of blocks of the channel transfer matrix offers near optimal performance at lower computational cost, but hardware support is still needed. We first propose a COordinate Rotation DIgital Computer (CORDIC) rotator in reconfigurable hardware to expose and then exploit at software level the intra-block paralellism of the QR decomposition. In particular, we show that although the rotator is deeply pipelined, the scale factor inherent to CORDIC algorithm can still be distributedly compensated throughout the pipeline at no additional cycle time penalty. Then, for a Nios II processor augmented with a Reconfigurable Functional Unit (RFU) that incorporates the proposed CORDIC rotator, we also propose a computing scenario that keeps all the data to be processed inside the RFU, to minimize overhead of the data trafic between the Register File and the CORDIC rotator. Overall, we show that OFDM demodulation under fast-fading can be performed in fixed-point arithmetic and in real-time on a Nios II reconfigurable embedded system, proving that an SDR solution for OFDM demodulation under fast fading is possible.","PeriodicalId":93225,"journal":{"name":"Proceedings. IEEE Workshop on Signal Processing Systems (2007-2014)","volume":"28 1","pages":"13-18"},"PeriodicalIF":0.0,"publicationDate":"2007-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83530663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：