Pub Date : 2023-02-22DOI: 10.1109/TSIPI.2023.3247617
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2023.3247617","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3247617","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2023-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/10040918/10049297.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-22DOI: 10.1109/TSIPI.2023.3247619
{"title":"IEEE Transactions on Signal and Power Integrity Information for Authors","authors":"","doi":"10.1109/TSIPI.2023.3247619","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3247619","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2023-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/10040918/10049296.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A circuit modeling application for three-dimensional (3D) integrated circuits (IC)/packages is proposed in this article. The method is based on the partial element equivalent circuit (PEEC) method and layered Green's functions (LGF). The LGFs are calculated from the discrete complex image method with three terms, direct coupling, complex images, and surface wave extracted to analyze the wave behaviors. The dominant terms for the LGFs are analyzed for four canonical stack-ups in 3D IC/packaging systems. Analytical formulas that include the contribution of the complex images calculated from the LGFs are used for the partial capacitance calculation. A fast-modeling approach is proposed by applying the LGF in PEEC using three acceleration treatments to handle the 3D IC/packaging geometry without sacrificing accuracy. An on-chip power distribution network geometry is used to illustrate and validate the method.
{"title":"PEEC Modeling in 3D IC/Packaging Applications Based on Layered Green's Functions","authors":"Biyao Zhao;Siqi Bai;Jun Fan;Brice Achkir;Albert Ruehli","doi":"10.1109/TSIPI.2023.3244893","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3244893","url":null,"abstract":"A circuit modeling application for three-dimensional (3D) integrated circuits (IC)/packages is proposed in this article. The method is based on the partial element equivalent circuit (PEEC) method and layered Green's functions (LGF). The LGFs are calculated from the discrete complex image method with three terms, direct coupling, complex images, and surface wave extracted to analyze the wave behaviors. The dominant terms for the LGFs are analyzed for four canonical stack-ups in 3D IC/packaging systems. Analytical formulas that include the contribution of the complex images calculated from the LGFs are used for the partial capacitance calculation. A fast-modeling approach is proposed by applying the LGF in PEEC using three acceleration treatments to handle the 3D IC/packaging geometry without sacrificing accuracy. An on-chip power distribution network geometry is used to illustrate and validate the method.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"23-31"},"PeriodicalIF":0.0,"publicationDate":"2023-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-06DOI: 10.1109/TSIPI.2023.3242855
Zihao Wang;Zhifei Xu;Jiayi He;Hervé Delingette;Jun Fan
A trainable neural equalizer based on the long short-term memory (LSTM) neural network architecture is proposed in this article to recover the channel output signal. The current widely used solution for the transmission line signal recovery is generally realized through a decision feedback equalizer (DFE) or : Feed forward equalizer (FFE) combination. The novel learning-based equalizer is suitable for highly nonlinear signal restoration, thanks to its recurrent design. The effectiveness of the LSTM equalizer (LSTME) is shown through an advance design system simulation channel signal equalization task, including a quantitative and qualitative comparison with an FFE–DFE combination. The LSTM neural network shows good equalization results compared with that of the FFE–DFE combination. The advantage of a trainable LSTME lies in its ability to learn its parameters in a flexible manner and to tackle complex scenarios without any hardware modification. This can reduce the equalizer implantation cost for variant transmission channels and bring additional portability in practical applications.
{"title":"Long Short-Term Memory Neural Equalizer","authors":"Zihao Wang;Zhifei Xu;Jiayi He;Hervé Delingette;Jun Fan","doi":"10.1109/TSIPI.2023.3242855","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3242855","url":null,"abstract":"A trainable neural equalizer based on the long short-term memory (LSTM) neural network architecture is proposed in this article to recover the channel output signal. The current widely used solution for the transmission line signal recovery is generally realized through a decision feedback equalizer (DFE) or : Feed forward equalizer (FFE) combination. The novel learning-based equalizer is suitable for highly nonlinear signal restoration, thanks to its recurrent design. The effectiveness of the LSTM equalizer (LSTME) is shown through an advance design system simulation channel signal equalization task, including a quantitative and qualitative comparison with an FFE–DFE combination. The LSTM neural network shows good equalization results compared with that of the FFE–DFE combination. The advantage of a trainable LSTME lies in its ability to learn its parameters in a flexible manner and to tackle complex scenarios without any hardware modification. This can reduce the equalizer implantation cost for variant transmission channels and bring additional portability in practical applications.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"13-22"},"PeriodicalIF":0.0,"publicationDate":"2023-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we first propose and demonstrate a novel target-impedance (Z) extraction based optimal power distribution network (PDN) design methodology for high performance solid-state-drive (SSD) products. Instead of using the current profile of a chip power models (CPMs), the suggested methodology uses both measured current spectra and hierarchical PDN-Z models for target-Z calculation. We successfully measured the PCB-level current consumed by a memory package on SSD device using a test interposer specifically designed for current probing without interrupting the normal operations. Then, the measured PCB-level current is converted to the chip-level current value using Y-matrix of the hierarchical PDN-Z model. Compared with the simulation time for extracting a CPM current model, the proposed current measurement has relatively no time limit and, therefore, the target-Z covering a broadband frequency range is calculated based on the measured current spectrum. In addition, passive components such as decoupling capacitor are effectively selected using the deep-Q learning algorithm to satisfy the target- Z extracted by the proposed method and to optimize the PDN design. Finally, we verified for the first time that the mass-produced SSD product with the optimized PDN design satisfies the target voltage ripple in both simulation and measurement demonstrations.
{"title":"Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning","authors":"Jinwook Song;Daniel Hyunsuk Jung;Jaeyoung Shin;Chunghyun Ryu;Youngjun Ko;Sungwoo Jin;Soyoung Jung;Kyungsuk Kim;Youngmin Ku;Jung-Hwan Choi;Sunghoon Chun;Jonggyu Park","doi":"10.1109/TSIPI.2023.3235310","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3235310","url":null,"abstract":"In this article, we first propose and demonstrate a novel target-impedance (Z) extraction based optimal power distribution network (PDN) design methodology for high performance solid-state-drive (SSD) products. Instead of using the current profile of a chip power models (CPMs), the suggested methodology uses both measured current spectra and hierarchical PDN-Z models for target-Z calculation. We successfully measured the PCB-level current consumed by a memory package on SSD device using a test interposer specifically designed for current probing without interrupting the normal operations. Then, the measured PCB-level current is converted to the chip-level current value using Y-matrix of the hierarchical PDN-Z model. Compared with the simulation time for extracting a CPM current model, the proposed current measurement has relatively no time limit and, therefore, the target-Z covering a broadband frequency range is calculated based on the measured current spectrum. In addition, passive components such as decoupling capacitor are effectively selected using the deep-Q learning algorithm to satisfy the target- Z extracted by the proposed method and to optimize the PDN design. Finally, we verified for the first time that the mass-produced SSD product with the optimized PDN design satisfies the target voltage ripple in both simulation and measurement demonstrations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-28DOI: 10.1109/TSIPI.2022.3232196
Presents the 2022 author/subject index for this issue of the publication.
为本期出版物提供2022年作者/主题索引。
{"title":"2022 Index IEEE Transactions on Signal and Power Integrity Vol. 1","authors":"","doi":"10.1109/TSIPI.2022.3232196","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3232196","url":null,"abstract":"Presents the 2022 author/subject index for this issue of the publication.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2022-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/9770004/09999734.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-20DOI: 10.1109/TSIPI.2022.3229779
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本期出版物的编辑委员会、董事会、现任工作人员、委员会成员和/或协会编辑。
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2022.3229779","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3229779","url":null,"abstract":"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2022-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/9770004/09994596.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-19DOI: 10.1109/TSIPI.2022.3229735
These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.
这些说明为编写本出版物的论文提供了指导。为在本期刊上发表文章的作者提供信息。
{"title":"IEEE Transactions on Signal and Power Integrity Information for Authors","authors":"","doi":"10.1109/TSIPI.2022.3229735","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3229735","url":null,"abstract":"These instructions give guidelines for preparing papers for this publication. Presents information for authors publishing in this journal.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2022-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/9770004/09992179.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.
{"title":"Immunity Testing of Mixed Signal Electronics Against Power Supply Disturbances in the Frequency Range From 10 kHz To 5 MHz","authors":"Federico Sordi;Leonardo Vignoli;Lorenzo Capineri;Carlo Carobbi","doi":"10.1109/TSIPI.2022.3225511","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3225511","url":null,"abstract":"A method is presented to test the immunity of mixed signal (digital and analog) electronics to power supply disturbances in the frequency range between 10 and 5 MHz, as those originating from switched mode power supplies. An example of application of the method to a serializer/deserializer integrated circuit is illustrated. For these electronic devices, the power supply noise can critically affect performance. The SerDes is hosted by an evaluation board supplied by an external power module (PM). An adhoc disturbance source and coupling/Decoupling network (CDN) have been designed to couple a disturbance of significant amplitude to the power supply of the evaluation board while decoupling it from the power module (PM). The radiofrequency mpedance of the bypass network of the evaluation board has been considered for the design of both the disturbance source and the CDN. Details about the architecture and operation of the high-current, broadband and linear power amplifier used for disturbance generation are provided, along with component selection and verification of the CDN. The practical implementation of the test, including a feedback control loop capable of generating the specified disturbance level over the frequency range of interest, is described. Finally, test results are reported in terms of the SerDes bit error rate degradation as a function of disturbance amplitude and frequency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"170-178"},"PeriodicalIF":0.0,"publicationDate":"2022-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-11-16DOI: 10.1109/TSIPI.2022.3222122
Hanzhi Ma;Da Li;Tuomin Tao;Xingjian Shangguan;En-Xiao Liu;Jose Schutt-Aine;Andreas C. Cangellaris;Er-Ping Li
A dimensionality reduction based neural network framework is introduced for uncertainty quantification of time-domain response based on system uncertain design parameters for neuromorphic chips. The proposed method firstly makes use of the singular value decomposition (SVD) method to find the basis functions and corresponding coefficients of time-domain response, of which coefficients are used as a lower dimensional target outputs in neural network model compared with time sampling points prediction. This newly proposed method then develops an integrated neural network structure to simultaneously find the mean and variance of target coefficients with a combined definition of loss function, which can be utilized together with basis functions to construct the prediction interval of time-domain response. A memrisor-based crossbar array is applied in this work to verify the performance of the proposed method with the comparison of Monte Carlo method.
{"title":"Uncertainty Quantification of Signal Integrity Analysis for Neuromorphic Chips","authors":"Hanzhi Ma;Da Li;Tuomin Tao;Xingjian Shangguan;En-Xiao Liu;Jose Schutt-Aine;Andreas C. Cangellaris;Er-Ping Li","doi":"10.1109/TSIPI.2022.3222122","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3222122","url":null,"abstract":"A dimensionality reduction based neural network framework is introduced for uncertainty quantification of time-domain response based on system uncertain design parameters for neuromorphic chips. The proposed method firstly makes use of the singular value decomposition (SVD) method to find the basis functions and corresponding coefficients of time-domain response, of which coefficients are used as a lower dimensional target outputs in neural network model compared with time sampling points prediction. This newly proposed method then develops an integrated neural network structure to simultaneously find the mean and variance of target coefficients with a combined definition of loss function, which can be utilized together with basis functions to construct the prediction interval of time-domain response. A memrisor-based crossbar array is applied in this work to verify the performance of the proposed method with the comparison of Monte Carlo method.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"160-169"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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