Pub Date : 2024-04-19DOI: 10.1109/TSIPI.2024.3391212
Fayu Wan;Hongchuan Jia;Blaise Ravelo
An unfamiliar negative group delay (NGD) analysis of folded printed circuit board (PCB) trace constituted by coupled line (CL) is investigated. The PCB trace parameters are identified by defining the modified CL named li-topology, which behaves as a bandpass (BP) NGD function. The main specifications of the BP-NGD function from the S-parameter model are described. The theoretical equations of li-topology parameters are formulated. Then, proofs-of-concept (POC) of folded li-trace with different angles between “l” and “i” transmission line (TL) designed in microstrip technology are presented. Good agreement simulation and measurement results of folded li-POC enable conjecture on the variation of NGD value, NGD center frequency, reflection, and transmission coefficients are discussed. A new behavior characterized by the NGD effect is revealed in the function of the geometrical angle between the “l” and “i” TLs constituting the PCB trace POCs.
研究了由耦合线（CL）构成的折叠印刷电路板（PCB）迹线的陌生负群延迟（NGD）分析。通过定义名为 li-topology 的改良 CL 来确定 PCB 线路参数，该 PCB 线路表现为带通 (BP) NGD 函数。从 S 参数模型描述了 BP-NGD 函数的主要规格。制定了 li 拓扑参数的理论方程。然后，介绍了采用微带技术设计的具有不同 "l "和 "i "传输线（TL）夹角的折叠 li-trace 概念验证（POC）。折叠 li-POC 的仿真和测量结果非常吻合，因此可以猜测 NGD 值、NGD 中心频率、反射和传输系数的变化。构成 PCB 跟踪 POC 的 "l "和 "i "TL 之间的几何角度的函数揭示了以 NGD 效应为特征的新行为。
{"title":"Bandpass NGD Analysis of PCB Folded Li-Shape Trace","authors":"Fayu Wan;Hongchuan Jia;Blaise Ravelo","doi":"10.1109/TSIPI.2024.3391212","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3391212","url":null,"abstract":"An unfamiliar negative group delay (NGD) analysis of folded printed circuit board (PCB) trace constituted by coupled line (CL) is investigated. The PCB trace parameters are identified by defining the modified CL named li-topology, which behaves as a bandpass (BP) NGD function. The main specifications of the BP-NGD function from the S-parameter model are described. The theoretical equations of li-topology parameters are formulated. Then, proofs-of-concept (POC) of folded li-trace with different angles between “l” and “i” transmission line (TL) designed in microstrip technology are presented. Good agreement simulation and measurement results of folded li-POC enable conjecture on the variation of NGD value, NGD center frequency, reflection, and transmission coefficients are discussed. A new behavior characterized by the NGD effect is revealed in the function of the geometrical angle between the “l” and “i” TLs constituting the PCB trace POCs.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"56-66"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140818755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-30DOI: 10.1109/TSIPI.2024.3406267
Yang Liu;Yuwei Luo;Zhifei Xu;Xiuqin Chu;Jun Wang;Kai-Da Xu
Flexible printed circuit boards (FPCB) can provide more circuit design solutions for the miniaturization of electronic devices due to their small size, lightweight, and flexibility for bending. However, RF interference from RF antennas or other radiation sources may lead to signal integrity issues in FPCB signal transmission with the increase in transmission rate. To address this issue, a method based on the reciprocity theorem is proposed for rapidly estimating the near-field coupling between two single-port devices on an FPCB under bending conditions. Three different cases for the FPCB, i.e., no bending, bending outside the victim transmission line (TL), and bending across the victim TL, are analyzed to characterize the near-field coupling by deriving the expressions of the scattering parameters. Moreover, the bending angle, rotating angle, bending position, and bending diameter of FPCB are further analyzed for their impact on coupling under bending conditions. The proposed method can be used to analyze various FPCB bending situations.
{"title":"Near-Field Coupling Analysis of Flexible Printed Circuit Boards","authors":"Yang Liu;Yuwei Luo;Zhifei Xu;Xiuqin Chu;Jun Wang;Kai-Da Xu","doi":"10.1109/TSIPI.2024.3406267","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3406267","url":null,"abstract":"Flexible printed circuit boards (FPCB) can provide more circuit design solutions for the miniaturization of electronic devices due to their small size, lightweight, and flexibility for bending. However, RF interference from RF antennas or other radiation sources may lead to signal integrity issues in FPCB signal transmission with the increase in transmission rate. To address this issue, a method based on the reciprocity theorem is proposed for rapidly estimating the near-field coupling between two single-port devices on an FPCB under bending conditions. Three different cases for the FPCB, i.e., no bending, bending outside the victim transmission line (TL), and bending across the victim TL, are analyzed to characterize the near-field coupling by deriving the expressions of the scattering parameters. Moreover, the bending angle, rotating angle, bending position, and bending diameter of FPCB are further analyzed for their impact on coupling under bending conditions. The proposed method can be used to analyze various FPCB bending situations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"140-150"},"PeriodicalIF":0.0,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142397338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-29DOI: 10.1109/TSIPI.2024.3407030
Junho Joo;Manish K. Mathew;Arun Chada;Soumya Singh;Seema PK;Bhyrav Mutnury;DongHyun Kim
As the complexity of server platforms increases, the noise produced by switching voltage regulator modules (VRMs) is more likely to be coupled to nearby high-speed traces. This study aims to investigate the mechanism of noise coupling between the noise generated by a VRM and a high-speed signal trace, as well as to evaluate various noise-reduction methods. A VRM's rapid switching of field effect transistors generates an unintentional coupling region that primarily injects noise into high-speed traces routed in the inner signal layers of the printed circuit boards (PCBs) in server platforms. To analyze various VRM noise coupling mechanisms in practical high-speed channels, a simplified PCB design based on a high-speed server platform is designed and fabricated. In addition, case studies are conducted under various conditions to validate the most efficient VRM noise coupling reduction method by both simulation and measurement. Finally, various design factors that influence VRM noise coupling are evaluated to propose guidelines for high-speed channel designers. This study presents the first comprehensive analysis of different noise coupling mechanisms and an IR drop aware guideline to reduce noise in dense high-speed systems containing a VRM.
{"title":"Investigation of Voltage Regulator Module (VRM)-Induced Noise to High-Speed Signals With VRM via Design Factors","authors":"Junho Joo;Manish K. Mathew;Arun Chada;Soumya Singh;Seema PK;Bhyrav Mutnury;DongHyun Kim","doi":"10.1109/TSIPI.2024.3407030","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3407030","url":null,"abstract":"As the complexity of server platforms increases, the noise produced by switching voltage regulator modules (VRMs) is more likely to be coupled to nearby high-speed traces. This study aims to investigate the mechanism of noise coupling between the noise generated by a VRM and a high-speed signal trace, as well as to evaluate various noise-reduction methods. A VRM's rapid switching of field effect transistors generates an unintentional coupling region that primarily injects noise into high-speed traces routed in the inner signal layers of the printed circuit boards (PCBs) in server platforms. To analyze various VRM noise coupling mechanisms in practical high-speed channels, a simplified PCB design based on a high-speed server platform is designed and fabricated. In addition, case studies are conducted under various conditions to validate the most efficient VRM noise coupling reduction method by both simulation and measurement. Finally, various design factors that influence VRM noise coupling are evaluated to propose guidelines for high-speed channel designers. This study presents the first comprehensive analysis of different noise coupling mechanisms and an IR drop aware guideline to reduce noise in dense high-speed systems containing a VRM.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"97-109"},"PeriodicalIF":0.0,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141319673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-10DOI: 10.1109/TSIPI.2024.3399099
Mu-Shui Zhang;Yingfeng Ding;Zixin Wang
As the wired communication data rate increases up to 112 Gb/s and even higher, the differential crosstalk from neighboring pairs becomes much more serious and could significantly deteriorate signal integrity. In this article, a perturbed pin map design method is proposed to reduce the differential crosstalk for 112 Gb/s four-level pulse amplitude modulation applications. Three physical parameters, the distance of two signal pins in a pair, the angle of two adjacent signal pairs, and the positions of surrounding ground vias, are perturbed for maximum crosstalk reduction. Without changing the signal-to-ground ratio and area per differential pair, the proposed pin map patterns can significantly mitigate the total differential crosstalk in via connection field, by both common-mode cancelation enhancement of signal vias and shielding effect improvement of ground vias through perturbation. Numerical examples are performed to verify the validity of crosstalk reduction in both square and triangular pin arrays. Finally, the effect of perturbation amplitude on crosstalk reduction is analyzed; it is shown that differential crosstalk decreases fast when the perturbed offset is smaller than 2 r ( r is the radius of balls), and it becomes slow when the perturbed offset is larger than 2r . Compared with the nonperturbed square and triangular patterns, the integrated crosstalk noises of the perturbed patterns are reduced by 70.62% and 68.72%, respectively, at 112 Gb/s, and the insertion loss to crosstalk ratios are averagely increased by 11 dB and 8 dB, respectively, up to 40 GHz, with a perturbed offset of 2 r .
{"title":"Perturbed Pin Map Design for Low Differential Crosstalk in 112 Gb/s PAM4 Applications","authors":"Mu-Shui Zhang;Yingfeng Ding;Zixin Wang","doi":"10.1109/TSIPI.2024.3399099","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3399099","url":null,"abstract":"As the wired communication data rate increases up to 112 Gb/s and even higher, the differential crosstalk from neighboring pairs becomes much more serious and could significantly deteriorate signal integrity. In this article, a perturbed pin map design method is proposed to reduce the differential crosstalk for 112 Gb/s four-level pulse amplitude modulation applications. Three physical parameters, the distance of two signal pins in a pair, the angle of two adjacent signal pairs, and the positions of surrounding ground vias, are perturbed for maximum crosstalk reduction. Without changing the signal-to-ground ratio and area per differential pair, the proposed pin map patterns can significantly mitigate the total differential crosstalk in via connection field, by both common-mode cancelation enhancement of signal vias and shielding effect improvement of ground vias through perturbation. Numerical examples are performed to verify the validity of crosstalk reduction in both square and triangular pin arrays. Finally, the effect of perturbation amplitude on crosstalk reduction is analyzed; it is shown that differential crosstalk decreases fast when the perturbed offset is smaller than 2\u0000<italic>r</i>\u0000 (\u0000<italic>r</i>\u0000 is the radius of balls), and it becomes slow when the perturbed offset is larger than \u0000<italic>2r</i>\u0000. Compared with the nonperturbed square and triangular patterns, the integrated crosstalk noises of the perturbed patterns are reduced by 70.62% and 68.72%, respectively, at 112 Gb/s, and the insertion loss to crosstalk ratios are averagely increased by 11 dB and 8 dB, respectively, up to 40 GHz, with a perturbed offset of 2\u0000<italic>r</i>\u0000.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"85-96"},"PeriodicalIF":0.0,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141245180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mobile industry processor interface (MIPI) C-PHY is a signal transmission interface with three-phase encoding technology on the three-wire high-speed channel. The traditional method of superposition to generate an eye diagram on this kind of channel is time-consuming. The novel eye estimation methods for the C-PHY protocol are proposed. A new greedy algorithm and dynamic programming method are proposed to predict the worst-case eye diagram, respectively. The accuracy and efficiency of these two methods are compared. In addition, the algorithms for estimating the statistical eye diagram of MIPI C-PHY with and without considering the driver nonlinearity are also proposed and compared respectively. All the proposed algorithms are validated by experimental measurement. The excellent agreement could be well seen.
{"title":"Eye Estimation Methods for MIPI C-PHY","authors":"Yu-Ying Cheng;Pei-Yang Weng;Suani-Kai Yang;Shih-Hsien Wu;Tzong-Lin Wu","doi":"10.1109/TSIPI.2024.3396436","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3396436","url":null,"abstract":"Mobile industry processor interface (MIPI) C-PHY is a signal transmission interface with three-phase encoding technology on the three-wire high-speed channel. The traditional method of superposition to generate an eye diagram on this kind of channel is time-consuming. The novel eye estimation methods for the C-PHY protocol are proposed. A new greedy algorithm and dynamic programming method are proposed to predict the worst-case eye diagram, respectively. The accuracy and efficiency of these two methods are compared. In addition, the algorithms for estimating the statistical eye diagram of MIPI C-PHY with and without considering the driver nonlinearity are also proposed and compared respectively. All the proposed algorithms are validated by experimental measurement. The excellent agreement could be well seen.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"75-84"},"PeriodicalIF":0.0,"publicationDate":"2024-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140948956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-16DOI: 10.1109/TSIPI.2024.3366499
Vinod Kumar Verma;Jai Narayan Tripathi
This work presents a comprehensive study on the impact of variability on jitter in CMOS integrated circuits. As a case study, an analytical model of a CMOS inverter has been developed, and the input–output relationship is derived considering the effect of power supply noise, variations in design parameters due to fabrication process inaccuracies, and temperature. These parameters are taken as random variables, and the timing deviation in the transition edges of the output response has been modeled analytically. The proposed approach has been validated using numerical examples by comparing results obtained from the proposed analysis with the results obtained from the SPICE-based simulator. A couple of measurement examples and an application case study are also presented to validate the state-of-the-art investigation. The considered examples and application case study suggest the importance of the current study to ensure the timing budget of a system. The proposed approach can be used to estimate critical variability issues affecting the timing budgets of the systems.
{"title":"Variability-Aware Modeling of Power Supply Induced Jitter","authors":"Vinod Kumar Verma;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2024.3366499","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3366499","url":null,"abstract":"This work presents a comprehensive study on the impact of variability on jitter in CMOS integrated circuits. As a case study, an analytical model of a CMOS inverter has been developed, and the input–output relationship is derived considering the effect of power supply noise, variations in design parameters due to fabrication process inaccuracies, and temperature. These parameters are taken as random variables, and the timing deviation in the transition edges of the output response has been modeled analytically. The proposed approach has been validated using numerical examples by comparing results obtained from the proposed analysis with the results obtained from the SPICE-based simulator. A couple of measurement examples and an application case study are also presented to validate the state-of-the-art investigation. The considered examples and application case study suggest the importance of the current study to ensure the timing budget of a system. The proposed approach can be used to estimate critical variability issues affecting the timing budgets of the systems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"47-55"},"PeriodicalIF":0.0,"publicationDate":"2024-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140291213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-06DOI: 10.1109/TSIPI.2024.3362317
Quankun Chen;Hanzhi Ma;Da Li;Tuomin Tao;Shurun Tan;En-Xiao Liu;Jose Schutt-Aine;Er-Ping Li
This article introduces a comprehensive approach for designing and analyzing signal integrity in heterogeneous integrated systems that incorporate neuromorphic Darwin chips. The proposed integrated system architecture includes a neuromorphic Darwin chip, digital signal processing unit, microcontroller unit, field programmable gate arrays, and coding and decoding modules to encode and reconstruct analog spiking signals. The study evaluates the encoding module and the heterogeneous integration structure and conducts signal integrity analysis. To achieve optimal signal integrity performance, the article proposes a novel binocular eye diagram analysis technique. This innovative approach guides the encoding algorithm modification and improves the overall system performance. This research is the first to combine joint field-circuit simulation, heterogeneous integration modeling, and signal integrity analysis of the Darwin neuromorphic chip, and it is expected to serve as a valuable reference for future studies on similar systems.
{"title":"Hybrid Signal Integrity Modeling and Analysis of Heterogeneous Integrated System With Neuromorphic Darwin Chip","authors":"Quankun Chen;Hanzhi Ma;Da Li;Tuomin Tao;Shurun Tan;En-Xiao Liu;Jose Schutt-Aine;Er-Ping Li","doi":"10.1109/TSIPI.2024.3362317","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3362317","url":null,"abstract":"This article introduces a comprehensive approach for designing and analyzing signal integrity in heterogeneous integrated systems that incorporate neuromorphic Darwin chips. The proposed integrated system architecture includes a neuromorphic Darwin chip, digital signal processing unit, microcontroller unit, field programmable gate arrays, and coding and decoding modules to encode and reconstruct analog spiking signals. The study evaluates the encoding module and the heterogeneous integration structure and conducts signal integrity analysis. To achieve optimal signal integrity performance, the article proposes a novel binocular eye diagram analysis technique. This innovative approach guides the encoding algorithm modification and improves the overall system performance. This research is the first to combine joint field-circuit simulation, heterogeneous integration modeling, and signal integrity analysis of the Darwin neuromorphic chip, and it is expected to serve as a valuable reference for future studies on similar systems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"37-46"},"PeriodicalIF":0.0,"publicationDate":"2024-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139987179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-02-05DOI: 10.1109/TSIPI.2024.3361863
Ze Sun;Jian Liu;Xiaoyan Xiong;DongHyun Kim;Daryl Beetner;Victor Khilkevich
The intentional roughness created on conductor surfaces during the printed circuit board (PCB) manufacturing process leads to a substantial increase of conductor loss at frequencies in the order of tens of gigahertz. It is essential to know the roughness of PCB conductors to create adequate models of the high-speed channels. This article presents a novel method for extracting the roughness level of conductor foils using only measured S -parameters and cross-sectional information. The proposed technique is relatively easy to perform, cost-effective, and does not require the destruction of test boards, making it a promising alternative to existing methods that rely on optical or scanning electron microscope imaging. Besides, the proposed method can handle boards with nonequal roughness on different conductor surfaces, which is common in PCBs. The method is validated through both simulation and measurement, and a good correlation is achieved between the extracted roughness level and the values obtained by microscopic imaging.
在印刷电路板（PCB）制造过程中，导体表面有意产生的粗糙度导致导体损耗在数十兆赫兹的频率下大幅增加。了解印刷电路板导体的粗糙度对于建立适当的高速通道模型至关重要。本文介绍了一种仅使用测量的 S 参数和横截面信息来提取导体箔粗糙度的新方法。所提出的技术操作相对简单，成本效益高，而且不需要破坏测试电路板，因此有望替代依赖光学或扫描电子显微镜成像的现有方法。此外，所提出的方法还能处理不同导体表面粗糙度不均等的电路板，这在印刷电路板中很常见。该方法通过模拟和测量进行了验证，提取的粗糙度水平与显微镜成像获得的值之间具有良好的相关性。
{"title":"Extraction of Transmission Line Surface Roughness Using S-Parameter Measurements and Cross-Sectional Information","authors":"Ze Sun;Jian Liu;Xiaoyan Xiong;DongHyun Kim;Daryl Beetner;Victor Khilkevich","doi":"10.1109/TSIPI.2024.3361863","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3361863","url":null,"abstract":"The intentional roughness created on conductor surfaces during the printed circuit board (PCB) manufacturing process leads to a substantial increase of conductor loss at frequencies in the order of tens of gigahertz. It is essential to know the roughness of PCB conductors to create adequate models of the high-speed channels. This article presents a novel method for extracting the roughness level of conductor foils using only measured \u0000<italic>S</i>\u0000-parameters and cross-sectional information. The proposed technique is relatively easy to perform, cost-effective, and does not require the destruction of test boards, making it a promising alternative to existing methods that rely on optical or scanning electron microscope imaging. Besides, the proposed method can handle boards with nonequal roughness on different conductor surfaces, which is common in PCBs. The method is validated through both simulation and measurement, and a good correlation is achieved between the extracted roughness level and the values obtained by microscopic imaging.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"30-36"},"PeriodicalIF":0.0,"publicationDate":"2024-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139916584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The power-aware input/output buffer information specification (IBIS) model does not correctly account for the delay change caused by supply-voltage noise. This article presents a new modification algorithm that improves the accuracy of the IBIS model by including the power-supply-induced jitter (PSIJ) sensitivity effect; more specifically, the dc-jitter-sensitivity effect. The procedure of extracting the key parameters and modifying the switching coefficients is presented and applied in a real design. The performance of the modified IBIS model is validated using two designs, and the simulation accuracy is improved significantly compared with that of the traditional IBIS model. The improved IBIS model is applicable to situations when there is dc or ac noise on the power rail. The predriver propagation delay can also be characterized in the simulation by including the predriver PSIJ effect. The algorithm is efficient while straightforward and easily implemented by introducing just one parameter to the IBIS model.
{"title":"IBIS Model Simulation Accuracy Improvement by Including Power-Supply-Induced Jitter Effect","authors":"Yifan Ding;Yin Sun;Randy Wolff;Zhiping Yang;Chulsoon Hwang","doi":"10.1109/TSIPI.2023.3349229","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3349229","url":null,"abstract":"The power-aware input/output buffer information specification (IBIS) model does not correctly account for the delay change caused by supply-voltage noise. This article presents a new modification algorithm that improves the accuracy of the IBIS model by including the power-supply-induced jitter (PSIJ) sensitivity effect; more specifically, the dc-jitter-sensitivity effect. The procedure of extracting the key parameters and modifying the switching coefficients is presented and applied in a real design. The performance of the modified IBIS model is validated using two designs, and the simulation accuracy is improved significantly compared with that of the traditional IBIS model. The improved IBIS model is applicable to situations when there is dc or ac noise on the power rail. The predriver propagation delay can also be characterized in the simulation by including the predriver PSIJ effect. The algorithm is efficient while straightforward and easily implemented by introducing just one parameter to the IBIS model.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"21-29"},"PeriodicalIF":0.0,"publicationDate":"2024-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139710539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-28DOI: 10.1109/TSIPI.2023.3348197
{"title":"2023 Index IEEE Transactions on Signal and Power Integrity Vol. 2","authors":"","doi":"10.1109/TSIPI.2023.3348197","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3348197","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2023-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10375861","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139060271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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