The performances of Ensemble non return-to-zero (ENRZ) under the interferences of crosstalk, along with non-return-to-zero (NRZ), pulse amplitude modulation of three-level (PAM3), and pulse amplitude modulation of four-level (PAM4) are investigated. Two scenarios, 0 dB and high loss, with varying levels of dual-side far-end crosstalk (FEXT) and near-end crosstalk applied, are studied. A detailed description of the ENRZ algorithm is provided. The reasons that lead to the performance edge of ENRZ in contrast to the rest three modulations are analyzed. The methodologies of injecting the crosstalk interferences into the differential/multiwire channels are discussed. A widely existing issue in computing FEXT is pointed out, with the recommended technique presented. A holistic channel simulation method called frequency domain matrix multiplication is employed in this study for its better handling of multiwire-based channels. The simulated eye diagrams obtained with the four modulation techniques are compared and analyzed. The study shows that ENRZ's inherence of insensitivity to channel loss makes it remain robust under the interferences of crosstalk in comparison with the other three types of modulations. Meanwhile, overall ENRZ and NRZ are more robust than PAM3 and PAM4 when the crosstalk level increases.
{"title":"Crosstalk Performance Analysis: ENRZ, NRZ, PAM3, and PAM4","authors":"Sherman Shan Chen;Zhifei Xu;Armin Tajalli;Brian Holden","doi":"10.1109/TSIPI.2023.3253461","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3253461","url":null,"abstract":"The performances of Ensemble non return-to-zero (ENRZ) under the interferences of crosstalk, along with non-return-to-zero (NRZ), pulse amplitude modulation of three-level (PAM3), and pulse amplitude modulation of four-level (PAM4) are investigated. Two scenarios, 0 dB and high loss, with varying levels of dual-side far-end crosstalk (FEXT) and near-end crosstalk applied, are studied. A detailed description of the ENRZ algorithm is provided. The reasons that lead to the performance edge of ENRZ in contrast to the rest three modulations are analyzed. The methodologies of injecting the crosstalk interferences into the differential/multiwire channels are discussed. A widely existing issue in computing FEXT is pointed out, with the recommended technique presented. A holistic channel simulation method called frequency domain matrix multiplication is employed in this study for its better handling of multiwire-based channels. The simulated eye diagrams obtained with the four modulation techniques are compared and analyzed. The study shows that ENRZ's inherence of insensitivity to channel loss makes it remain robust under the interferences of crosstalk in comparison with the other three types of modulations. Meanwhile, overall ENRZ and NRZ are more robust than PAM3 and PAM4 when the crosstalk level increases.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"53-63"},"PeriodicalIF":0.0,"publicationDate":"2023-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-11DOI: 10.1109/TSIPI.2023.3275124
Yan Li;Heyuan Yu;Erping Li
Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural networks, SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity (SI) problems in three-dimensional (3-D) packaging. In this article, the resistance–inductance–capacitance–conductance (RLGC) equivalent circuit of through-silicon vias (TSV) and redistribution layer (RDL) structure was modeled in 3-D packaging. Furthermore, the spike SI issues, such as reflection, delay, and loss of spike signals, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself and not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This article presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.
{"title":"Signal Integrity Analysis of Neuronal Spike Signal in 3-D Packaging","authors":"Yan Li;Heyuan Yu;Erping Li","doi":"10.1109/TSIPI.2023.3275124","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3275124","url":null,"abstract":"Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural networks, SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity (SI) problems in three-dimensional (3-D) packaging. In this article, the resistance–inductance–capacitance–conductance (RLGC) equivalent circuit of through-silicon vias (TSV) and redistribution layer (RDL) structure was modeled in 3-D packaging. Furthermore, the spike SI issues, such as reflection, delay, and loss of spike signals, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself and not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This article presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"84-93"},"PeriodicalIF":0.0,"publicationDate":"2023-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-23DOI: 10.1109/TSIPI.2023.3248539
Jiayi He;Ling Zhang;Zurab Kiguradze;Arun Chada;Adam Klivans;Bhyrav Mutnury;Er-Ping Li;Jun Fan
This article presents a flexible and efficient methodology to optimize stack-up for multilayer printed circuit boards (PCBs) with enormous search space and various design constraints. PCB stack-up optimization is crucial in high-speed system design to achieve the desired electrical performance while reducing system costs. The stack-up optimization process is labor-intensive and time-consuming for a large number of layers. Moreover, after the optimization process, the electrical performance of a real design, such as the impedance and loss, may deviate from the target design due to manufacturing variations. Estimating the worst cases due to the manufacturing variations, referred to as “corner cases” in this article, is essential for a confident PCB design but challenging since the number of related parameters is large. In this article, PCB stack-up optimization and corner-case searching are addressed and greatly accelerated using the integer programming technique. All constraints are converted to mathematical equalities and inequalities that can be solved rapidly by an integer programming solver to obtain feasible stack-up solutions. After the cross sections of the transmission lines are optimized based on the stack-up design to achieve a target electrical performance, the upper and lower bound of impedance and loss are acquired using integer programming when the design parameters vary in a particular range. The proposed method is verified using multilayer PCB designs with practical constraints and demonstrates its effectiveness and high efficiency.
{"title":"Fast PCB Stack-Up Optimization Using Integer Programming","authors":"Jiayi He;Ling Zhang;Zurab Kiguradze;Arun Chada;Adam Klivans;Bhyrav Mutnury;Er-Ping Li;Jun Fan","doi":"10.1109/TSIPI.2023.3248539","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3248539","url":null,"abstract":"This article presents a flexible and efficient methodology to optimize stack-up for multilayer printed circuit boards (PCBs) with enormous search space and various design constraints. PCB stack-up optimization is crucial in high-speed system design to achieve the desired electrical performance while reducing system costs. The stack-up optimization process is labor-intensive and time-consuming for a large number of layers. Moreover, after the optimization process, the electrical performance of a real design, such as the impedance and loss, may deviate from the target design due to manufacturing variations. Estimating the worst cases due to the manufacturing variations, referred to as “corner cases” in this article, is essential for a confident PCB design but challenging since the number of related parameters is large. In this article, PCB stack-up optimization and corner-case searching are addressed and greatly accelerated using the integer programming technique. All constraints are converted to mathematical equalities and inequalities that can be solved rapidly by an integer programming solver to obtain feasible stack-up solutions. After the cross sections of the transmission lines are optimized based on the stack-up design to achieve a target electrical performance, the upper and lower bound of impedance and loss are acquired using integer programming when the design parameters vary in a particular range. The proposed method is verified using multilayer PCB designs with practical constraints and demonstrates its effectiveness and high efficiency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"32-42"},"PeriodicalIF":0.0,"publicationDate":"2023-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-22DOI: 10.1109/TSIPI.2023.3247617
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2023.3247617","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3247617","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2023-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/10040918/10049297.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896246","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-22DOI: 10.1109/TSIPI.2023.3247619
{"title":"IEEE Transactions on Signal and Power Integrity Information for Authors","authors":"","doi":"10.1109/TSIPI.2023.3247619","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3247619","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2023-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/10040918/10049296.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A circuit modeling application for three-dimensional (3D) integrated circuits (IC)/packages is proposed in this article. The method is based on the partial element equivalent circuit (PEEC) method and layered Green's functions (LGF). The LGFs are calculated from the discrete complex image method with three terms, direct coupling, complex images, and surface wave extracted to analyze the wave behaviors. The dominant terms for the LGFs are analyzed for four canonical stack-ups in 3D IC/packaging systems. Analytical formulas that include the contribution of the complex images calculated from the LGFs are used for the partial capacitance calculation. A fast-modeling approach is proposed by applying the LGF in PEEC using three acceleration treatments to handle the 3D IC/packaging geometry without sacrificing accuracy. An on-chip power distribution network geometry is used to illustrate and validate the method.
{"title":"PEEC Modeling in 3D IC/Packaging Applications Based on Layered Green's Functions","authors":"Biyao Zhao;Siqi Bai;Jun Fan;Brice Achkir;Albert Ruehli","doi":"10.1109/TSIPI.2023.3244893","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3244893","url":null,"abstract":"A circuit modeling application for three-dimensional (3D) integrated circuits (IC)/packages is proposed in this article. The method is based on the partial element equivalent circuit (PEEC) method and layered Green's functions (LGF). The LGFs are calculated from the discrete complex image method with three terms, direct coupling, complex images, and surface wave extracted to analyze the wave behaviors. The dominant terms for the LGFs are analyzed for four canonical stack-ups in 3D IC/packaging systems. Analytical formulas that include the contribution of the complex images calculated from the LGFs are used for the partial capacitance calculation. A fast-modeling approach is proposed by applying the LGF in PEEC using three acceleration treatments to handle the 3D IC/packaging geometry without sacrificing accuracy. An on-chip power distribution network geometry is used to illustrate and validate the method.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"23-31"},"PeriodicalIF":0.0,"publicationDate":"2023-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-06DOI: 10.1109/TSIPI.2023.3242855
Zihao Wang;Zhifei Xu;Jiayi He;Hervé Delingette;Jun Fan
A trainable neural equalizer based on the long short-term memory (LSTM) neural network architecture is proposed in this article to recover the channel output signal. The current widely used solution for the transmission line signal recovery is generally realized through a decision feedback equalizer (DFE) or : Feed forward equalizer (FFE) combination. The novel learning-based equalizer is suitable for highly nonlinear signal restoration, thanks to its recurrent design. The effectiveness of the LSTM equalizer (LSTME) is shown through an advance design system simulation channel signal equalization task, including a quantitative and qualitative comparison with an FFE–DFE combination. The LSTM neural network shows good equalization results compared with that of the FFE–DFE combination. The advantage of a trainable LSTME lies in its ability to learn its parameters in a flexible manner and to tackle complex scenarios without any hardware modification. This can reduce the equalizer implantation cost for variant transmission channels and bring additional portability in practical applications.
{"title":"Long Short-Term Memory Neural Equalizer","authors":"Zihao Wang;Zhifei Xu;Jiayi He;Hervé Delingette;Jun Fan","doi":"10.1109/TSIPI.2023.3242855","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3242855","url":null,"abstract":"A trainable neural equalizer based on the long short-term memory (LSTM) neural network architecture is proposed in this article to recover the channel output signal. The current widely used solution for the transmission line signal recovery is generally realized through a decision feedback equalizer (DFE) or : Feed forward equalizer (FFE) combination. The novel learning-based equalizer is suitable for highly nonlinear signal restoration, thanks to its recurrent design. The effectiveness of the LSTM equalizer (LSTME) is shown through an advance design system simulation channel signal equalization task, including a quantitative and qualitative comparison with an FFE–DFE combination. The LSTM neural network shows good equalization results compared with that of the FFE–DFE combination. The advantage of a trainable LSTME lies in its ability to learn its parameters in a flexible manner and to tackle complex scenarios without any hardware modification. This can reduce the equalizer implantation cost for variant transmission channels and bring additional portability in practical applications.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"13-22"},"PeriodicalIF":0.0,"publicationDate":"2023-02-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, we first propose and demonstrate a novel target-impedance (Z) extraction based optimal power distribution network (PDN) design methodology for high performance solid-state-drive (SSD) products. Instead of using the current profile of a chip power models (CPMs), the suggested methodology uses both measured current spectra and hierarchical PDN-Z models for target-Z calculation. We successfully measured the PCB-level current consumed by a memory package on SSD device using a test interposer specifically designed for current probing without interrupting the normal operations. Then, the measured PCB-level current is converted to the chip-level current value using Y-matrix of the hierarchical PDN-Z model. Compared with the simulation time for extracting a CPM current model, the proposed current measurement has relatively no time limit and, therefore, the target-Z covering a broadband frequency range is calculated based on the measured current spectrum. In addition, passive components such as decoupling capacitor are effectively selected using the deep-Q learning algorithm to satisfy the target- Z extracted by the proposed method and to optimize the PDN design. Finally, we verified for the first time that the mass-produced SSD product with the optimized PDN design satisfies the target voltage ripple in both simulation and measurement demonstrations.
{"title":"Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning","authors":"Jinwook Song;Daniel Hyunsuk Jung;Jaeyoung Shin;Chunghyun Ryu;Youngjun Ko;Sungwoo Jin;Soyoung Jung;Kyungsuk Kim;Youngmin Ku;Jung-Hwan Choi;Sunghoon Chun;Jonggyu Park","doi":"10.1109/TSIPI.2023.3235310","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3235310","url":null,"abstract":"In this article, we first propose and demonstrate a novel target-impedance (Z) extraction based optimal power distribution network (PDN) design methodology for high performance solid-state-drive (SSD) products. Instead of using the current profile of a chip power models (CPMs), the suggested methodology uses both measured current spectra and hierarchical PDN-Z models for target-Z calculation. We successfully measured the PCB-level current consumed by a memory package on SSD device using a test interposer specifically designed for current probing without interrupting the normal operations. Then, the measured PCB-level current is converted to the chip-level current value using Y-matrix of the hierarchical PDN-Z model. Compared with the simulation time for extracting a CPM current model, the proposed current measurement has relatively no time limit and, therefore, the target-Z covering a broadband frequency range is calculated based on the measured current spectrum. In addition, passive components such as decoupling capacitor are effectively selected using the deep-Q learning algorithm to satisfy the target- Z extracted by the proposed method and to optimize the PDN design. Finally, we verified for the first time that the mass-produced SSD product with the optimized PDN design satisfies the target voltage ripple in both simulation and measurement demonstrations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2023-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-28DOI: 10.1109/TSIPI.2022.3232196
Presents the 2022 author/subject index for this issue of the publication.
为本期出版物提供2022年作者/主题索引。
{"title":"2022 Index IEEE Transactions on Signal and Power Integrity Vol. 1","authors":"","doi":"10.1109/TSIPI.2022.3232196","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3232196","url":null,"abstract":"Presents the 2022 author/subject index for this issue of the publication.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2022-12-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/9770004/09999734.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-12-20DOI: 10.1109/TSIPI.2022.3229779
Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.
列出本期出版物的编辑委员会、董事会、现任工作人员、委员会成员和/或协会编辑。
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2022.3229779","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3229779","url":null,"abstract":"Presents a listing of the editorial board, board of governors, current staff, committee members, and/or society editors for this issue of the publication.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2022-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/9770004/09994596.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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