Pub Date : 2024-10-29DOI: 10.1109/TSIPI.2024.3487539
Chaofeng Li;Xiao-Ding Cai;Manish K. Mathew;Junyong Park;Mehdi Mousavi;Shameem Ahmed;Bidyut Sen;DongHyun Kim
A high-speed via model considering equivalent high-order-mode inductance for frequencies above 70 GHz is proposed in this article. The proposed via model, which considers the equivalent high-order-mode inductance, is a high-accuracy and high-bandwidth via model, improved from the previously proposed mode-decomposition-based equivalent via (MEV) model. The equivalent high-order-mode inductance is an inductance produced by the magnetic fields of high-order modes in the via domain. By including the empirical equivalent high-order-mode inductance, the proposed via model accurately predicts the insertion and return losses of the via with a large antipad size up to the frequency of 150 GHz, which expands the application range of the previously proposed MEV model. In this article, the limitation of the previously proposed MEV model is analyzed by comparing the input impedance extracted from the MEV model and the full-wave simulation. An empirical closed-form formula is proposed to calculate the equivalent high-order-mode inductance at high frequencies to improve the accuracy of the previously proposed model. In addition, the proposed single high-speed via model was expanded to a differential via pair model. The proposed high-speed via model was verified using simulation and measurement results.
{"title":"Effective High-Speed via Model Considering Equivalent High-Order-Mode Inductance","authors":"Chaofeng Li;Xiao-Ding Cai;Manish K. Mathew;Junyong Park;Mehdi Mousavi;Shameem Ahmed;Bidyut Sen;DongHyun Kim","doi":"10.1109/TSIPI.2024.3487539","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3487539","url":null,"abstract":"A high-speed via model considering equivalent high-order-mode inductance for frequencies above 70 GHz is proposed in this article. The proposed via model, which considers the equivalent high-order-mode inductance, is a high-accuracy and high-bandwidth via model, improved from the previously proposed mode-decomposition-based equivalent via (MEV) model. The equivalent high-order-mode inductance is an inductance produced by the magnetic fields of high-order modes in the via domain. By including the empirical equivalent high-order-mode inductance, the proposed via model accurately predicts the insertion and return losses of the via with a large antipad size up to the frequency of 150 GHz, which expands the application range of the previously proposed MEV model. In this article, the limitation of the previously proposed MEV model is analyzed by comparing the input impedance extracted from the MEV model and the full-wave simulation. An empirical closed-form formula is proposed to calculate the equivalent high-order-mode inductance at high frequencies to improve the accuracy of the previously proposed model. In addition, the proposed single high-speed via model was expanded to a differential via pair model. The proposed high-speed via model was verified using simulation and measurement results.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"169-177"},"PeriodicalIF":0.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142671987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-29DOI: 10.1109/TSIPI.2024.3487547
Kuei-Ju Lin;Chien-Min Lin;Ruey-Beei Wu
As high-speed digital systems require faster transmission and computing speed, the impact of complex interconnects in a limited space on the electrical performance of the channel-link system becomes more and more serious. This article aims to optimize the interconnection links between the enhanced second-generation high-bandwidth memory modules and systems on chip (CPU or GPU) for achieving the optimized signal and power integrity. Since the signal lines are susceptible to crosstalk, an improved diagonal-staggering wiring scheme is proposed to reduce the coupling coefficient between the signal lines by at least five times. The contour map for the mismatched systems with the peak distortion analysis is then applied to quickly find the optimal impedance design of lines for the best eye diagram. At a data rate of 6.4 Gb/s with a rise time of 15 ps, the eye height is optimized to be 4.6 times that in the original layout. Finally, the power supply and grounds are interleaved to increase the capacitance and alleviate the power noise through the power delivery network (PDN) in the construction of the four-element voltage regulator module along with the on-chip capacitor and the specific power–ground layers. Modifying the layout scheme in the PDN with reasonable decoupling capacitance can lead to an additional 1.4 times improvement in the eye height over the original design.
{"title":"Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging","authors":"Kuei-Ju Lin;Chien-Min Lin;Ruey-Beei Wu","doi":"10.1109/TSIPI.2024.3487547","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3487547","url":null,"abstract":"As high-speed digital systems require faster transmission and computing speed, the impact of complex interconnects in a limited space on the electrical performance of the channel-link system becomes more and more serious. This article aims to optimize the interconnection links between the enhanced second-generation high-bandwidth memory modules and systems on chip (CPU or GPU) for achieving the optimized signal and power integrity. Since the signal lines are susceptible to crosstalk, an improved diagonal-staggering wiring scheme is proposed to reduce the coupling coefficient between the signal lines by at least five times. The contour map for the mismatched systems with the peak distortion analysis is then applied to quickly find the optimal impedance design of lines for the best eye diagram. At a data rate of 6.4 Gb/s with a rise time of 15 ps, the eye height is optimized to be 4.6 times that in the original layout. Finally, the power supply and grounds are interleaved to increase the capacitance and alleviate the power noise through the power delivery network (PDN) in the construction of the four-element voltage regulator module along with the on-chip capacitor and the specific power–ground layers. Modifying the layout scheme in the PDN with reasonable decoupling capacitance can lead to an additional 1.4 times improvement in the eye height over the original design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"159-168"},"PeriodicalIF":0.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Routing density is becoming in big challenge in die-to-die interconnects. In this article, we propose use of the dual-stripline configuration for routing signals in high-density interconnects. The scheme can improve the routing density by up to 33% when compared with the conventionally used stripline configuration. To address the challenges of crosstalk due to the proximity between vertically adjacent signal lines, half-pitch offset between lines on vertically adjacent layers has been proposed. The proposed routing scheme has been validated using 3-D full-wave electromagnetic simulations. The simulations show that the scheme can be used for increasing the routing density in the bunch-of-wires interface by 25%, while meeting all the bunch-of-wires channel specifications, which include eye-opening value above 68% unit interval at a bit error rate of $10^{-15}$ , with data rates of 16 Gbps per wire.
{"title":"Dual-Stripline Configuration for High-Density Routing in Chiplet Interconnects","authors":"Shekar Geedimatla;Jayaprakash Balachandran;Midhun Vysakham;Srinivas Venkataraman;Shalabh Gupta","doi":"10.1109/TSIPI.2024.3471470","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3471470","url":null,"abstract":"Routing density is becoming in big challenge in die-to-die interconnects. In this article, we propose use of the dual-stripline configuration for routing signals in high-density interconnects. The scheme can improve the routing density by up to 33% when compared with the conventionally used stripline configuration. To address the challenges of crosstalk due to the proximity between vertically adjacent signal lines, half-pitch offset between lines on vertically adjacent layers has been proposed. The proposed routing scheme has been validated using 3-D full-wave electromagnetic simulations. The simulations show that the scheme can be used for increasing the routing density in the bunch-of-wires interface by 25%, while meeting all the bunch-of-wires channel specifications, which include eye-opening value above 68% unit interval at a bit error rate of \u0000<inline-formula><tex-math>$10^{-15}$</tex-math></inline-formula>\u0000, with data rates of 16 Gbps per wire.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"151-158"},"PeriodicalIF":0.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/TSIPI.2024.3442986
Yingfeng Ding;Mu-Shui Zhang;Yufang Xu;Haopeng Feng;Zixin Wang
For most board-level digital systems, the power-noise interference covers a wide frequency range from near dc to several GHz. Current power-noise suppression methods can only selectively suppress low-frequency or high-frequency band-limited power noise. In this article, a novel plane pair embedded with lossy capacitors, each of which is formed by a conventional capacitor in series with a large resistor, is developed for ultrawideband power-noise suppression in high-speed digital systems, ranging from 10 kHz to several GHz. The noise suppression mechanism of the proposed structure is keeping the quality factor ( Q -factor) of a plane pair to a very low level, say Q <4,>Q -factor of a unit cell of the plane pair and adjusted by changing the physical parameters, such as series resistance, dielectric thickness, and period. The measured results show that the proposed plane pair embedded with lossy capacitors can achieve ultrawide −30-dB stopband, from 10 kHz to above 5 GHz.
{"title":"Ultrawideband Power-Noise Suppression Based on Lossy Capacitors With Low-Frequency Stopband Enhancement for Digital Systems","authors":"Yingfeng Ding;Mu-Shui Zhang;Yufang Xu;Haopeng Feng;Zixin Wang","doi":"10.1109/TSIPI.2024.3442986","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3442986","url":null,"abstract":"For most board-level digital systems, the power-noise interference covers a wide frequency range from near dc to several GHz. Current power-noise suppression methods can only selectively suppress low-frequency or high-frequency band-limited power noise. In this article, a novel plane pair embedded with lossy capacitors, each of which is formed by a conventional capacitor in series with a large resistor, is developed for ultrawideband power-noise suppression in high-speed digital systems, ranging from 10 kHz to several GHz. The noise suppression mechanism of the proposed structure is keeping the quality factor (\u0000<italic>Q</i>\u0000-factor) of a plane pair to a very low level, say \u0000<italic>Q</i>\u0000<4,>Q</i>\u0000-factor of a unit cell of the plane pair and adjusted by changing the physical parameters, such as series resistance, dielectric thickness, and period. The measured results show that the proposed plane pair embedded with lossy capacitors can achieve ultrawide −30-dB stopband, from 10 kHz to above 5 GHz.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"126-139"},"PeriodicalIF":0.0,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142077616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/TSIPI.2024.3416088
Junho Joo;Daniel L. Commerou;Hayden Huang;Chun-Yi Yeh;Jiaming Kang;Hank Lin;Bin-Chyi Tseng;Chulsoon Hwang
This article analyzes different methods for modeling a buck regulator among the variety of voltage regulator modules from the perspective of power integrity and assesses the accuracy of power supply induced jitter (PSIJ) predictions for each buck regulator model. To compare the buck regulator modeling approaches, methods for conventional passive component modeling and behavior modeling are introduced. Four different buck regulator models are compared with measurements in terms of time-domain voltage ripple and nonlinearity. Then, each model is applied to a simulation-based system-level PSIJ prediction setup to quantify the accuracy of the buck regulator models from the perspective of PSIJ. A printed circuit board with an inverter chain powered by an external buck regulator is selected as the device under test. In the presence of power supply fluctuations due to load current injection on the buck regulator, the time interval error of the inverter is measured. The measured peak-to-peak jitter is then reproduced by various simulation setups with the different buck regulator modeling methods. Finally, the PSIJ simulation accuracy is investigated for each buck regulator model.
{"title":"Modeling of a Voltage Regulator Module for Power Integrity: Power Supply Induced Jitter","authors":"Junho Joo;Daniel L. Commerou;Hayden Huang;Chun-Yi Yeh;Jiaming Kang;Hank Lin;Bin-Chyi Tseng;Chulsoon Hwang","doi":"10.1109/TSIPI.2024.3416088","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3416088","url":null,"abstract":"This article analyzes different methods for modeling a buck regulator among the variety of voltage regulator modules from the perspective of power integrity and assesses the accuracy of power supply induced jitter (PSIJ) predictions for each buck regulator model. To compare the buck regulator modeling approaches, methods for conventional passive component modeling and behavior modeling are introduced. Four different buck regulator models are compared with measurements in terms of time-domain voltage ripple and nonlinearity. Then, each model is applied to a simulation-based system-level PSIJ prediction setup to quantify the accuracy of the buck regulator models from the perspective of PSIJ. A printed circuit board with an inverter chain powered by an external buck regulator is selected as the device under test. In the presence of power supply fluctuations due to load current injection on the buck regulator, the time interval error of the inverter is measured. The measured peak-to-peak jitter is then reproduced by various simulation setups with the different buck regulator modeling methods. Finally, the PSIJ simulation accuracy is investigated for each buck regulator model.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"110-125"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141494828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-19DOI: 10.1109/TSIPI.2024.3391210
Junyong Park;Chaofeng Li;Eddie Mok;Joe Dickson;Joan Tourné;Aritharan Thurairajaratnam;DongHyun Kim
This article proposes a new vertical conductive structure (VeCS) to replace the general via structure for signal connection on printed circuit boards (PCBs). Vias have been widely used as interconnects for in-between layers in PCBs. However, vias have limitations due to their discontinuous characteristic impedance. The VeCS consists of a conductive structure shielded vertically by a metal structure, which provides impedance control. Thus, the VeCS has the constant characteristic impedance that can get better signal integrity for the high-speed channel than the general via structure. This article also proposes a scalable 3-D electromagnetic simulation model of the VeCS for signal integrity analysis. Simulated annealing and linear regression revealed that the scalable model accurately represents the VeCS. The electrical performances of a VeCS and a via were compared up to 70 GHz. The measured insertion losses at 70 GHz for the VeCS and the via were 35 dB and 70 dB, respectively, because PCB vias exhibit significant reflection loss above 10 GHz. In conclusion, this article proposes a novel vertical interconnection for PCBs.
{"title":"A Novel Vertical Conductive Structure for Printed Circuit Boards and its Scalable Model","authors":"Junyong Park;Chaofeng Li;Eddie Mok;Joe Dickson;Joan Tourné;Aritharan Thurairajaratnam;DongHyun Kim","doi":"10.1109/TSIPI.2024.3391210","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3391210","url":null,"abstract":"This article proposes a new vertical conductive structure (VeCS) to replace the general via structure for signal connection on printed circuit boards (PCBs). Vias have been widely used as interconnects for in-between layers in PCBs. However, vias have limitations due to their discontinuous characteristic impedance. The VeCS consists of a conductive structure shielded vertically by a metal structure, which provides impedance control. Thus, the VeCS has the constant characteristic impedance that can get better signal integrity for the high-speed channel than the general via structure. This article also proposes a scalable 3-D electromagnetic simulation model of the VeCS for signal integrity analysis. Simulated annealing and linear regression revealed that the scalable model accurately represents the VeCS. The electrical performances of a VeCS and a via were compared up to 70 GHz. The measured insertion losses at 70 GHz for the VeCS and the via were 35 dB and 70 dB, respectively, because PCB vias exhibit significant reflection loss above 10 GHz. In conclusion, this article proposes a novel vertical interconnection for PCBs.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"67-74"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-19DOI: 10.1109/TSIPI.2024.3391212
Fayu Wan;Hongchuan Jia;Blaise Ravelo
An unfamiliar negative group delay (NGD) analysis of folded printed circuit board (PCB) trace constituted by coupled line (CL) is investigated. The PCB trace parameters are identified by defining the modified CL named li-topology, which behaves as a bandpass (BP) NGD function. The main specifications of the BP-NGD function from the S-parameter model are described. The theoretical equations of li-topology parameters are formulated. Then, proofs-of-concept (POC) of folded li-trace with different angles between “l” and “i” transmission line (TL) designed in microstrip technology are presented. Good agreement simulation and measurement results of folded li-POC enable conjecture on the variation of NGD value, NGD center frequency, reflection, and transmission coefficients are discussed. A new behavior characterized by the NGD effect is revealed in the function of the geometrical angle between the “l” and “i” TLs constituting the PCB trace POCs.
研究了由耦合线（CL）构成的折叠印刷电路板（PCB）迹线的陌生负群延迟（NGD）分析。通过定义名为 li-topology 的改良 CL 来确定 PCB 线路参数，该 PCB 线路表现为带通 (BP) NGD 函数。从 S 参数模型描述了 BP-NGD 函数的主要规格。制定了 li 拓扑参数的理论方程。然后，介绍了采用微带技术设计的具有不同 "l "和 "i "传输线（TL）夹角的折叠 li-trace 概念验证（POC）。折叠 li-POC 的仿真和测量结果非常吻合，因此可以猜测 NGD 值、NGD 中心频率、反射和传输系数的变化。构成 PCB 跟踪 POC 的 "l "和 "i "TL 之间的几何角度的函数揭示了以 NGD 效应为特征的新行为。
{"title":"Bandpass NGD Analysis of PCB Folded Li-Shape Trace","authors":"Fayu Wan;Hongchuan Jia;Blaise Ravelo","doi":"10.1109/TSIPI.2024.3391212","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3391212","url":null,"abstract":"An unfamiliar negative group delay (NGD) analysis of folded printed circuit board (PCB) trace constituted by coupled line (CL) is investigated. The PCB trace parameters are identified by defining the modified CL named li-topology, which behaves as a bandpass (BP) NGD function. The main specifications of the BP-NGD function from the S-parameter model are described. The theoretical equations of li-topology parameters are formulated. Then, proofs-of-concept (POC) of folded li-trace with different angles between “l” and “i” transmission line (TL) designed in microstrip technology are presented. Good agreement simulation and measurement results of folded li-POC enable conjecture on the variation of NGD value, NGD center frequency, reflection, and transmission coefficients are discussed. A new behavior characterized by the NGD effect is revealed in the function of the geometrical angle between the “l” and “i” TLs constituting the PCB trace POCs.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"56-66"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140818755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-30DOI: 10.1109/TSIPI.2024.3406267
Yang Liu;Yuwei Luo;Zhifei Xu;Xiuqin Chu;Jun Wang;Kai-Da Xu
Flexible printed circuit boards (FPCB) can provide more circuit design solutions for the miniaturization of electronic devices due to their small size, lightweight, and flexibility for bending. However, RF interference from RF antennas or other radiation sources may lead to signal integrity issues in FPCB signal transmission with the increase in transmission rate. To address this issue, a method based on the reciprocity theorem is proposed for rapidly estimating the near-field coupling between two single-port devices on an FPCB under bending conditions. Three different cases for the FPCB, i.e., no bending, bending outside the victim transmission line (TL), and bending across the victim TL, are analyzed to characterize the near-field coupling by deriving the expressions of the scattering parameters. Moreover, the bending angle, rotating angle, bending position, and bending diameter of FPCB are further analyzed for their impact on coupling under bending conditions. The proposed method can be used to analyze various FPCB bending situations.
{"title":"Near-Field Coupling Analysis of Flexible Printed Circuit Boards","authors":"Yang Liu;Yuwei Luo;Zhifei Xu;Xiuqin Chu;Jun Wang;Kai-Da Xu","doi":"10.1109/TSIPI.2024.3406267","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3406267","url":null,"abstract":"Flexible printed circuit boards (FPCB) can provide more circuit design solutions for the miniaturization of electronic devices due to their small size, lightweight, and flexibility for bending. However, RF interference from RF antennas or other radiation sources may lead to signal integrity issues in FPCB signal transmission with the increase in transmission rate. To address this issue, a method based on the reciprocity theorem is proposed for rapidly estimating the near-field coupling between two single-port devices on an FPCB under bending conditions. Three different cases for the FPCB, i.e., no bending, bending outside the victim transmission line (TL), and bending across the victim TL, are analyzed to characterize the near-field coupling by deriving the expressions of the scattering parameters. Moreover, the bending angle, rotating angle, bending position, and bending diameter of FPCB are further analyzed for their impact on coupling under bending conditions. The proposed method can be used to analyze various FPCB bending situations.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"140-150"},"PeriodicalIF":0.0,"publicationDate":"2024-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142397338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-29DOI: 10.1109/TSIPI.2024.3407030
Junho Joo;Manish K. Mathew;Arun Chada;Soumya Singh;Seema PK;Bhyrav Mutnury;DongHyun Kim
As the complexity of server platforms increases, the noise produced by switching voltage regulator modules (VRMs) is more likely to be coupled to nearby high-speed traces. This study aims to investigate the mechanism of noise coupling between the noise generated by a VRM and a high-speed signal trace, as well as to evaluate various noise-reduction methods. A VRM's rapid switching of field effect transistors generates an unintentional coupling region that primarily injects noise into high-speed traces routed in the inner signal layers of the printed circuit boards (PCBs) in server platforms. To analyze various VRM noise coupling mechanisms in practical high-speed channels, a simplified PCB design based on a high-speed server platform is designed and fabricated. In addition, case studies are conducted under various conditions to validate the most efficient VRM noise coupling reduction method by both simulation and measurement. Finally, various design factors that influence VRM noise coupling are evaluated to propose guidelines for high-speed channel designers. This study presents the first comprehensive analysis of different noise coupling mechanisms and an IR drop aware guideline to reduce noise in dense high-speed systems containing a VRM.
{"title":"Investigation of Voltage Regulator Module (VRM)-Induced Noise to High-Speed Signals With VRM via Design Factors","authors":"Junho Joo;Manish K. Mathew;Arun Chada;Soumya Singh;Seema PK;Bhyrav Mutnury;DongHyun Kim","doi":"10.1109/TSIPI.2024.3407030","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3407030","url":null,"abstract":"As the complexity of server platforms increases, the noise produced by switching voltage regulator modules (VRMs) is more likely to be coupled to nearby high-speed traces. This study aims to investigate the mechanism of noise coupling between the noise generated by a VRM and a high-speed signal trace, as well as to evaluate various noise-reduction methods. A VRM's rapid switching of field effect transistors generates an unintentional coupling region that primarily injects noise into high-speed traces routed in the inner signal layers of the printed circuit boards (PCBs) in server platforms. To analyze various VRM noise coupling mechanisms in practical high-speed channels, a simplified PCB design based on a high-speed server platform is designed and fabricated. In addition, case studies are conducted under various conditions to validate the most efficient VRM noise coupling reduction method by both simulation and measurement. Finally, various design factors that influence VRM noise coupling are evaluated to propose guidelines for high-speed channel designers. This study presents the first comprehensive analysis of different noise coupling mechanisms and an IR drop aware guideline to reduce noise in dense high-speed systems containing a VRM.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"97-109"},"PeriodicalIF":0.0,"publicationDate":"2024-03-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141319673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-03-10DOI: 10.1109/TSIPI.2024.3399099
Mu-Shui Zhang;Yingfeng Ding;Zixin Wang
As the wired communication data rate increases up to 112 Gb/s and even higher, the differential crosstalk from neighboring pairs becomes much more serious and could significantly deteriorate signal integrity. In this article, a perturbed pin map design method is proposed to reduce the differential crosstalk for 112 Gb/s four-level pulse amplitude modulation applications. Three physical parameters, the distance of two signal pins in a pair, the angle of two adjacent signal pairs, and the positions of surrounding ground vias, are perturbed for maximum crosstalk reduction. Without changing the signal-to-ground ratio and area per differential pair, the proposed pin map patterns can significantly mitigate the total differential crosstalk in via connection field, by both common-mode cancelation enhancement of signal vias and shielding effect improvement of ground vias through perturbation. Numerical examples are performed to verify the validity of crosstalk reduction in both square and triangular pin arrays. Finally, the effect of perturbation amplitude on crosstalk reduction is analyzed; it is shown that differential crosstalk decreases fast when the perturbed offset is smaller than 2 r ( r is the radius of balls), and it becomes slow when the perturbed offset is larger than 2r . Compared with the nonperturbed square and triangular patterns, the integrated crosstalk noises of the perturbed patterns are reduced by 70.62% and 68.72%, respectively, at 112 Gb/s, and the insertion loss to crosstalk ratios are averagely increased by 11 dB and 8 dB, respectively, up to 40 GHz, with a perturbed offset of 2 r .
{"title":"Perturbed Pin Map Design for Low Differential Crosstalk in 112 Gb/s PAM4 Applications","authors":"Mu-Shui Zhang;Yingfeng Ding;Zixin Wang","doi":"10.1109/TSIPI.2024.3399099","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3399099","url":null,"abstract":"As the wired communication data rate increases up to 112 Gb/s and even higher, the differential crosstalk from neighboring pairs becomes much more serious and could significantly deteriorate signal integrity. In this article, a perturbed pin map design method is proposed to reduce the differential crosstalk for 112 Gb/s four-level pulse amplitude modulation applications. Three physical parameters, the distance of two signal pins in a pair, the angle of two adjacent signal pairs, and the positions of surrounding ground vias, are perturbed for maximum crosstalk reduction. Without changing the signal-to-ground ratio and area per differential pair, the proposed pin map patterns can significantly mitigate the total differential crosstalk in via connection field, by both common-mode cancelation enhancement of signal vias and shielding effect improvement of ground vias through perturbation. Numerical examples are performed to verify the validity of crosstalk reduction in both square and triangular pin arrays. Finally, the effect of perturbation amplitude on crosstalk reduction is analyzed; it is shown that differential crosstalk decreases fast when the perturbed offset is smaller than 2\u0000<italic>r</i>\u0000 (\u0000<italic>r</i>\u0000 is the radius of balls), and it becomes slow when the perturbed offset is larger than \u0000<italic>2r</i>\u0000. Compared with the nonperturbed square and triangular patterns, the integrated crosstalk noises of the perturbed patterns are reduced by 70.62% and 68.72%, respectively, at 112 Gb/s, and the insertion loss to crosstalk ratios are averagely increased by 11 dB and 8 dB, respectively, up to 40 GHz, with a perturbed offset of 2\u0000<italic>r</i>\u0000.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"85-96"},"PeriodicalIF":0.0,"publicationDate":"2024-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141245180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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