Pub Date : 2024-11-28DOI: 10.1109/TSIPI.2024.3505141
Xiao-Pei Zhou;Da-Wei Wang;Wen-Sheng Zhao;Peng Zhang;Jia-Hao Pan
In this article, the application of through-silicon capacitor (TSC) in the power distribution network (PDN) of three-dimensional (3-D) integrated circuits (ICs) is systematically investigated for the first time. Additionally, the deep reinforcement learning (DRL) algorithm is integrated to minimize the deployment of TSCs while achieving the target impedance, thereby reducing the cost in practical applications. By selectively replacing the specified through-silicon vias (TSV) with TSCs in the existing TSV array, this method not only ensures uniform stress distribution within the structure but also effectively reduces the required area for decoupling capacitors and enables greater flexibility in TSC applications. A comprehensive investigation is carried out to assess the electrical characteristics of TSCs and their efficiency in mitigating PDN impedance. Then, an advanced approach, combining vector fitting and neural networks, is employed for the parametric modeling of TSCs. The impedance of PDN in 3-D IC is computed using transmission matrix method. By incorporating 3-D IC PDN and TSC information as inputs, the DRL algorithm determines the optimal placement and types of TSCs. The impedance suppression effect of TSC in 3-D IC PDN is verified through various test cases, and the optimization results of DRL were compared with those of other intelligent algorithms. Finally, a comparative analysis was carried out, highlighting the significance of this article.
本文首次系统地研究了通硅电容（TSC）在三维集成电路配电网（PDN）中的应用。此外，集成了深度强化学习（DRL）算法，在实现目标阻抗的同时最大限度地减少了tsc的部署，从而降低了实际应用中的成本。该方法通过选择性地将现有TSV阵列中指定的通硅通孔（TSV）替换为TSC，不仅保证了结构内应力分布均匀，而且有效地减少了去耦电容器所需的面积，使TSC应用具有更大的灵活性。进行了全面的调查，以评估tsc的电特性及其在减轻PDN阻抗方面的效率。然后，采用向量拟合和神经网络相结合的先进方法对tsc进行参数化建模。采用传输矩阵法计算了三维集成电路中PDN的阻抗。DRL算法通过将3-D IC PDN和TSC信息作为输入，确定TSC的最佳位置和类型。通过各种测试用例验证了TSC在三维IC PDN中的阻抗抑制效果，并将DRL的优化结果与其他智能算法的优化结果进行了比较。最后进行了对比分析，凸显了本文的意义。
{"title":"Modeling of Through-Silicon Capacitor and Its Applications for the Optimization of Power Distribution Network in 3-D Integrated Circuits","authors":"Xiao-Pei Zhou;Da-Wei Wang;Wen-Sheng Zhao;Peng Zhang;Jia-Hao Pan","doi":"10.1109/TSIPI.2024.3505141","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3505141","url":null,"abstract":"In this article, the application of through-silicon capacitor (TSC) in the power distribution network (PDN) of three-dimensional (3-D) integrated circuits (ICs) is systematically investigated for the first time. Additionally, the deep reinforcement learning (DRL) algorithm is integrated to minimize the deployment of TSCs while achieving the target impedance, thereby reducing the cost in practical applications. By selectively replacing the specified through-silicon vias (TSV) with TSCs in the existing TSV array, this method not only ensures uniform stress distribution within the structure but also effectively reduces the required area for decoupling capacitors and enables greater flexibility in TSC applications. A comprehensive investigation is carried out to assess the electrical characteristics of TSCs and their efficiency in mitigating PDN impedance. Then, an advanced approach, combining vector fitting and neural networks, is employed for the parametric modeling of TSCs. The impedance of PDN in 3-D IC is computed using transmission matrix method. By incorporating 3-D IC PDN and TSC information as inputs, the DRL algorithm determines the optimal placement and types of TSCs. The impedance suppression effect of TSC in 3-D IC PDN is verified through various test cases, and the optimization results of DRL were compared with those of other intelligent algorithms. Finally, a comparative analysis was carried out, highlighting the significance of this article.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"199-211"},"PeriodicalIF":0.0,"publicationDate":"2024-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142797929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-07DOI: 10.1109/TSIPI.2024.3493817
Aditya Rao;Eric Bogatin;Melinda Piket-May;Mohammed F. Hadi
This article details the impact of non-TEM propagation on a microstrip structure's crosstalk, impedance, and effective dielectric constant. A new onset frequency is defined to quantify where non-TEM dispersion is significant in microstrip transmission lines for high-speed digital applications. The impact of non-TEM dispersion on eye diagrams for digital signals is explored, showing a significant impact from non-TEM dispersion. Using this analysis, guidelines have been defined for when a full-wave simulator must be utilized to simulate a microstrip structure and when a quasi-static simulator provides accurate results at a given data rate.
本文详细介绍了非 TEM 传播对微带结构的串扰、阻抗和有效介电常数的影响。文章定义了一个新的起始频率，以量化高速数字应用中微带传输线的非 TEM 色散显著性。探讨了非 TEM 色散对数字信号眼图的影响，显示了非 TEM 色散的重大影响。通过这一分析，确定了何时必须使用全波模拟器模拟微带结构，以及何时准静态模拟器可在给定数据速率下提供准确结果的指导原则。
{"title":"Non-TEM Dispersion in Microstrip Structures at High Data Rates","authors":"Aditya Rao;Eric Bogatin;Melinda Piket-May;Mohammed F. Hadi","doi":"10.1109/TSIPI.2024.3493817","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3493817","url":null,"abstract":"This article details the impact of non-TEM propagation on a microstrip structure's crosstalk, impedance, and effective dielectric constant. A new onset frequency is defined to quantify where non-TEM dispersion is significant in microstrip transmission lines for high-speed digital applications. The impact of non-TEM dispersion on eye diagrams for digital signals is explored, showing a significant impact from non-TEM dispersion. Using this analysis, guidelines have been defined for when a full-wave simulator must be utilized to simulate a microstrip structure and when a quasi-static simulator provides accurate results at a given data rate.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"178-185"},"PeriodicalIF":0.0,"publicationDate":"2024-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-04DOI: 10.1109/TSIPI.2024.3490512
Jack Juang;Ling Zhang;Haran Manoharan;Francesco De Paulis;Chulsoon Hwang
In power distribution network designs, a large number of decoupling capacitors (decaps) may be needed to satisfy target impedance limits. Many algorithms have been proposed and implemented for finding the optimal decap placement, including genetic algorithms (GA), and machine learning methods. In this work, an improved GA is proposed for finding the decap placement pattern that can satisfy a target impedance using the minimum number of decaps. The distribution of capacitors expected to appear in the global minimum solution is first predicted by determining how effective each decap type is toward satisfying certain critical impedance points. This estimation is used to inform the generation of initial solutions in order to put the initial search space nearer the global minimum and ensure certain solution characteristics appear. GA search using this improved population generation is found to be an improvement over a Canonical GA implementation, by finding solutions where the latter could not, or finding a solution using fewer decaps.
在配电网络设计中，可能需要大量去耦电容器（decap）来满足目标阻抗限制。人们提出并实施了许多算法，包括遗传算法（GA）和机器学习方法，用于寻找最佳的去耦电容器位置。在这项工作中，我们提出了一种改进的遗传算法，用于寻找能够满足目标阻抗的去盖帽放置模式，并使用最少的去盖帽数量。首先，通过确定每种分路器类型对满足某些临界阻抗点的有效性，来预测预计会出现在全局最小解决方案中的电容器分布。这种估算用于生成初始解决方案，以便使初始搜索空间更接近全局最小值，并确保出现某些解决方案特征。使用这种改进的种群生成方法进行 GA 搜索，发现比 Canonical GA 实施方法有了改进，可以找到后者无法找到的解决方案，或使用更少的分封点找到解决方案。
{"title":"Augmented Genetic Algorithm for Decoupling Capacitor Optimization in Power Distribution Network Design Through Improved Population Generation","authors":"Jack Juang;Ling Zhang;Haran Manoharan;Francesco De Paulis;Chulsoon Hwang","doi":"10.1109/TSIPI.2024.3490512","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3490512","url":null,"abstract":"In power distribution network designs, a large number of decoupling capacitors (decaps) may be needed to satisfy target impedance limits. Many algorithms have been proposed and implemented for finding the optimal decap placement, including genetic algorithms (GA), and machine learning methods. In this work, an improved GA is proposed for finding the decap placement pattern that can satisfy a target impedance using the minimum number of decaps. The distribution of capacitors expected to appear in the global minimum solution is first predicted by determining how effective each decap type is toward satisfying certain critical impedance points. This estimation is used to inform the generation of initial solutions in order to put the initial search space nearer the global minimum and ensure certain solution characteristics appear. GA search using this improved population generation is found to be an improvement over a Canonical GA implementation, by finding solutions where the latter could not, or finding a solution using fewer decaps.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"186-198"},"PeriodicalIF":0.0,"publicationDate":"2024-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-29DOI: 10.1109/TSIPI.2024.3487539
Chaofeng Li;Xiao-Ding Cai;Manish K. Mathew;Junyong Park;Mehdi Mousavi;Shameem Ahmed;Bidyut Sen;DongHyun Kim
A high-speed via model considering equivalent high-order-mode inductance for frequencies above 70 GHz is proposed in this article. The proposed via model, which considers the equivalent high-order-mode inductance, is a high-accuracy and high-bandwidth via model, improved from the previously proposed mode-decomposition-based equivalent via (MEV) model. The equivalent high-order-mode inductance is an inductance produced by the magnetic fields of high-order modes in the via domain. By including the empirical equivalent high-order-mode inductance, the proposed via model accurately predicts the insertion and return losses of the via with a large antipad size up to the frequency of 150 GHz, which expands the application range of the previously proposed MEV model. In this article, the limitation of the previously proposed MEV model is analyzed by comparing the input impedance extracted from the MEV model and the full-wave simulation. An empirical closed-form formula is proposed to calculate the equivalent high-order-mode inductance at high frequencies to improve the accuracy of the previously proposed model. In addition, the proposed single high-speed via model was expanded to a differential via pair model. The proposed high-speed via model was verified using simulation and measurement results.
{"title":"Effective High-Speed via Model Considering Equivalent High-Order-Mode Inductance","authors":"Chaofeng Li;Xiao-Ding Cai;Manish K. Mathew;Junyong Park;Mehdi Mousavi;Shameem Ahmed;Bidyut Sen;DongHyun Kim","doi":"10.1109/TSIPI.2024.3487539","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3487539","url":null,"abstract":"A high-speed via model considering equivalent high-order-mode inductance for frequencies above 70 GHz is proposed in this article. The proposed via model, which considers the equivalent high-order-mode inductance, is a high-accuracy and high-bandwidth via model, improved from the previously proposed mode-decomposition-based equivalent via (MEV) model. The equivalent high-order-mode inductance is an inductance produced by the magnetic fields of high-order modes in the via domain. By including the empirical equivalent high-order-mode inductance, the proposed via model accurately predicts the insertion and return losses of the via with a large antipad size up to the frequency of 150 GHz, which expands the application range of the previously proposed MEV model. In this article, the limitation of the previously proposed MEV model is analyzed by comparing the input impedance extracted from the MEV model and the full-wave simulation. An empirical closed-form formula is proposed to calculate the equivalent high-order-mode inductance at high frequencies to improve the accuracy of the previously proposed model. In addition, the proposed single high-speed via model was expanded to a differential via pair model. The proposed high-speed via model was verified using simulation and measurement results.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"169-177"},"PeriodicalIF":0.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142671987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-29DOI: 10.1109/TSIPI.2024.3487547
Kuei-Ju Lin;Chien-Min Lin;Ruey-Beei Wu
As high-speed digital systems require faster transmission and computing speed, the impact of complex interconnects in a limited space on the electrical performance of the channel-link system becomes more and more serious. This article aims to optimize the interconnection links between the enhanced second-generation high-bandwidth memory modules and systems on chip (CPU or GPU) for achieving the optimized signal and power integrity. Since the signal lines are susceptible to crosstalk, an improved diagonal-staggering wiring scheme is proposed to reduce the coupling coefficient between the signal lines by at least five times. The contour map for the mismatched systems with the peak distortion analysis is then applied to quickly find the optimal impedance design of lines for the best eye diagram. At a data rate of 6.4 Gb/s with a rise time of 15 ps, the eye height is optimized to be 4.6 times that in the original layout. Finally, the power supply and grounds are interleaved to increase the capacitance and alleviate the power noise through the power delivery network (PDN) in the construction of the four-element voltage regulator module along with the on-chip capacitor and the specific power–ground layers. Modifying the layout scheme in the PDN with reasonable decoupling capacitance can lead to an additional 1.4 times improvement in the eye height over the original design.
{"title":"Optimized Signal and Power Integrity of Silicon Interposer for HBM2E in CoWoS Packaging","authors":"Kuei-Ju Lin;Chien-Min Lin;Ruey-Beei Wu","doi":"10.1109/TSIPI.2024.3487547","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3487547","url":null,"abstract":"As high-speed digital systems require faster transmission and computing speed, the impact of complex interconnects in a limited space on the electrical performance of the channel-link system becomes more and more serious. This article aims to optimize the interconnection links between the enhanced second-generation high-bandwidth memory modules and systems on chip (CPU or GPU) for achieving the optimized signal and power integrity. Since the signal lines are susceptible to crosstalk, an improved diagonal-staggering wiring scheme is proposed to reduce the coupling coefficient between the signal lines by at least five times. The contour map for the mismatched systems with the peak distortion analysis is then applied to quickly find the optimal impedance design of lines for the best eye diagram. At a data rate of 6.4 Gb/s with a rise time of 15 ps, the eye height is optimized to be 4.6 times that in the original layout. Finally, the power supply and grounds are interleaved to increase the capacitance and alleviate the power noise through the power delivery network (PDN) in the construction of the four-element voltage regulator module along with the on-chip capacitor and the specific power–ground layers. Modifying the layout scheme in the PDN with reasonable decoupling capacitance can lead to an additional 1.4 times improvement in the eye height over the original design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"159-168"},"PeriodicalIF":0.0,"publicationDate":"2024-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142645479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Routing density is becoming in big challenge in die-to-die interconnects. In this article, we propose use of the dual-stripline configuration for routing signals in high-density interconnects. The scheme can improve the routing density by up to 33% when compared with the conventionally used stripline configuration. To address the challenges of crosstalk due to the proximity between vertically adjacent signal lines, half-pitch offset between lines on vertically adjacent layers has been proposed. The proposed routing scheme has been validated using 3-D full-wave electromagnetic simulations. The simulations show that the scheme can be used for increasing the routing density in the bunch-of-wires interface by 25%, while meeting all the bunch-of-wires channel specifications, which include eye-opening value above 68% unit interval at a bit error rate of $10^{-15}$ , with data rates of 16 Gbps per wire.
{"title":"Dual-Stripline Configuration for High-Density Routing in Chiplet Interconnects","authors":"Shekar Geedimatla;Jayaprakash Balachandran;Midhun Vysakham;Srinivas Venkataraman;Shalabh Gupta","doi":"10.1109/TSIPI.2024.3471470","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3471470","url":null,"abstract":"Routing density is becoming in big challenge in die-to-die interconnects. In this article, we propose use of the dual-stripline configuration for routing signals in high-density interconnects. The scheme can improve the routing density by up to 33% when compared with the conventionally used stripline configuration. To address the challenges of crosstalk due to the proximity between vertically adjacent signal lines, half-pitch offset between lines on vertically adjacent layers has been proposed. The proposed routing scheme has been validated using 3-D full-wave electromagnetic simulations. The simulations show that the scheme can be used for increasing the routing density in the bunch-of-wires interface by 25%, while meeting all the bunch-of-wires channel specifications, which include eye-opening value above 68% unit interval at a bit error rate of \u0000<inline-formula><tex-math>$10^{-15}$</tex-math></inline-formula>\u0000, with data rates of 16 Gbps per wire.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"151-158"},"PeriodicalIF":0.0,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142452683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-08-14DOI: 10.1109/TSIPI.2024.3442986
Yingfeng Ding;Mu-Shui Zhang;Yufang Xu;Haopeng Feng;Zixin Wang
For most board-level digital systems, the power-noise interference covers a wide frequency range from near dc to several GHz. Current power-noise suppression methods can only selectively suppress low-frequency or high-frequency band-limited power noise. In this article, a novel plane pair embedded with lossy capacitors, each of which is formed by a conventional capacitor in series with a large resistor, is developed for ultrawideband power-noise suppression in high-speed digital systems, ranging from 10 kHz to several GHz. The noise suppression mechanism of the proposed structure is keeping the quality factor ( Q -factor) of a plane pair to a very low level, say Q <4,>Q -factor of a unit cell of the plane pair and adjusted by changing the physical parameters, such as series resistance, dielectric thickness, and period. The measured results show that the proposed plane pair embedded with lossy capacitors can achieve ultrawide −30-dB stopband, from 10 kHz to above 5 GHz.
{"title":"Ultrawideband Power-Noise Suppression Based on Lossy Capacitors With Low-Frequency Stopband Enhancement for Digital Systems","authors":"Yingfeng Ding;Mu-Shui Zhang;Yufang Xu;Haopeng Feng;Zixin Wang","doi":"10.1109/TSIPI.2024.3442986","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3442986","url":null,"abstract":"For most board-level digital systems, the power-noise interference covers a wide frequency range from near dc to several GHz. Current power-noise suppression methods can only selectively suppress low-frequency or high-frequency band-limited power noise. In this article, a novel plane pair embedded with lossy capacitors, each of which is formed by a conventional capacitor in series with a large resistor, is developed for ultrawideband power-noise suppression in high-speed digital systems, ranging from 10 kHz to several GHz. The noise suppression mechanism of the proposed structure is keeping the quality factor (\u0000<italic>Q</i>\u0000-factor) of a plane pair to a very low level, say \u0000<italic>Q</i>\u0000<4,>Q</i>\u0000-factor of a unit cell of the plane pair and adjusted by changing the physical parameters, such as series resistance, dielectric thickness, and period. The measured results show that the proposed plane pair embedded with lossy capacitors can achieve ultrawide −30-dB stopband, from 10 kHz to above 5 GHz.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"126-139"},"PeriodicalIF":0.0,"publicationDate":"2024-08-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142077616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-06-19DOI: 10.1109/TSIPI.2024.3416088
Junho Joo;Daniel L. Commerou;Hayden Huang;Chun-Yi Yeh;Jiaming Kang;Hank Lin;Bin-Chyi Tseng;Chulsoon Hwang
This article analyzes different methods for modeling a buck regulator among the variety of voltage regulator modules from the perspective of power integrity and assesses the accuracy of power supply induced jitter (PSIJ) predictions for each buck regulator model. To compare the buck regulator modeling approaches, methods for conventional passive component modeling and behavior modeling are introduced. Four different buck regulator models are compared with measurements in terms of time-domain voltage ripple and nonlinearity. Then, each model is applied to a simulation-based system-level PSIJ prediction setup to quantify the accuracy of the buck regulator models from the perspective of PSIJ. A printed circuit board with an inverter chain powered by an external buck regulator is selected as the device under test. In the presence of power supply fluctuations due to load current injection on the buck regulator, the time interval error of the inverter is measured. The measured peak-to-peak jitter is then reproduced by various simulation setups with the different buck regulator modeling methods. Finally, the PSIJ simulation accuracy is investigated for each buck regulator model.
{"title":"Modeling of a Voltage Regulator Module for Power Integrity: Power Supply Induced Jitter","authors":"Junho Joo;Daniel L. Commerou;Hayden Huang;Chun-Yi Yeh;Jiaming Kang;Hank Lin;Bin-Chyi Tseng;Chulsoon Hwang","doi":"10.1109/TSIPI.2024.3416088","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3416088","url":null,"abstract":"This article analyzes different methods for modeling a buck regulator among the variety of voltage regulator modules from the perspective of power integrity and assesses the accuracy of power supply induced jitter (PSIJ) predictions for each buck regulator model. To compare the buck regulator modeling approaches, methods for conventional passive component modeling and behavior modeling are introduced. Four different buck regulator models are compared with measurements in terms of time-domain voltage ripple and nonlinearity. Then, each model is applied to a simulation-based system-level PSIJ prediction setup to quantify the accuracy of the buck regulator models from the perspective of PSIJ. A printed circuit board with an inverter chain powered by an external buck regulator is selected as the device under test. In the presence of power supply fluctuations due to load current injection on the buck regulator, the time interval error of the inverter is measured. The measured peak-to-peak jitter is then reproduced by various simulation setups with the different buck regulator modeling methods. Finally, the PSIJ simulation accuracy is investigated for each buck regulator model.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"110-125"},"PeriodicalIF":0.0,"publicationDate":"2024-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141494828","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-19DOI: 10.1109/TSIPI.2024.3391210
Junyong Park;Chaofeng Li;Eddie Mok;Joe Dickson;Joan Tourné;Aritharan Thurairajaratnam;DongHyun Kim
This article proposes a new vertical conductive structure (VeCS) to replace the general via structure for signal connection on printed circuit boards (PCBs). Vias have been widely used as interconnects for in-between layers in PCBs. However, vias have limitations due to their discontinuous characteristic impedance. The VeCS consists of a conductive structure shielded vertically by a metal structure, which provides impedance control. Thus, the VeCS has the constant characteristic impedance that can get better signal integrity for the high-speed channel than the general via structure. This article also proposes a scalable 3-D electromagnetic simulation model of the VeCS for signal integrity analysis. Simulated annealing and linear regression revealed that the scalable model accurately represents the VeCS. The electrical performances of a VeCS and a via were compared up to 70 GHz. The measured insertion losses at 70 GHz for the VeCS and the via were 35 dB and 70 dB, respectively, because PCB vias exhibit significant reflection loss above 10 GHz. In conclusion, this article proposes a novel vertical interconnection for PCBs.
{"title":"A Novel Vertical Conductive Structure for Printed Circuit Boards and its Scalable Model","authors":"Junyong Park;Chaofeng Li;Eddie Mok;Joe Dickson;Joan Tourné;Aritharan Thurairajaratnam;DongHyun Kim","doi":"10.1109/TSIPI.2024.3391210","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3391210","url":null,"abstract":"This article proposes a new vertical conductive structure (VeCS) to replace the general via structure for signal connection on printed circuit boards (PCBs). Vias have been widely used as interconnects for in-between layers in PCBs. However, vias have limitations due to their discontinuous characteristic impedance. The VeCS consists of a conductive structure shielded vertically by a metal structure, which provides impedance control. Thus, the VeCS has the constant characteristic impedance that can get better signal integrity for the high-speed channel than the general via structure. This article also proposes a scalable 3-D electromagnetic simulation model of the VeCS for signal integrity analysis. Simulated annealing and linear regression revealed that the scalable model accurately represents the VeCS. The electrical performances of a VeCS and a via were compared up to 70 GHz. The measured insertion losses at 70 GHz for the VeCS and the via were 35 dB and 70 dB, respectively, because PCB vias exhibit significant reflection loss above 10 GHz. In conclusion, this article proposes a novel vertical interconnection for PCBs.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"67-74"},"PeriodicalIF":0.0,"publicationDate":"2024-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140880769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-04-19DOI: 10.1109/TSIPI.2024.3391212
Fayu Wan;Hongchuan Jia;Blaise Ravelo
An unfamiliar negative group delay (NGD) analysis of folded printed circuit board (PCB) trace constituted by coupled line (CL) is investigated. The PCB trace parameters are identified by defining the modified CL named li-topology, which behaves as a bandpass (BP) NGD function. The main specifications of the BP-NGD function from the S-parameter model are described. The theoretical equations of li-topology parameters are formulated. Then, proofs-of-concept (POC) of folded li-trace with different angles between “l” and “i” transmission line (TL) designed in microstrip technology are presented. Good agreement simulation and measurement results of folded li-POC enable conjecture on the variation of NGD value, NGD center frequency, reflection, and transmission coefficients are discussed. A new behavior characterized by the NGD effect is revealed in the function of the geometrical angle between the “l” and “i” TLs constituting the PCB trace POCs.
研究了由耦合线（CL）构成的折叠印刷电路板（PCB）迹线的陌生负群延迟（NGD）分析。通过定义名为 li-topology 的改良 CL 来确定 PCB 线路参数，该 PCB 线路表现为带通 (BP) NGD 函数。从 S 参数模型描述了 BP-NGD 函数的主要规格。制定了 li 拓扑参数的理论方程。然后，介绍了采用微带技术设计的具有不同 "l "和 "i "传输线（TL）夹角的折叠 li-trace 概念验证（POC）。折叠 li-POC 的仿真和测量结果非常吻合，因此可以猜测 NGD 值、NGD 中心频率、反射和传输系数的变化。构成 PCB 跟踪 POC 的 "l "和 "i "TL 之间的几何角度的函数揭示了以 NGD 效应为特征的新行为。
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