Pub Date : 2023-10-25DOI: 10.1109/TSIPI.2023.3327233
Junho Joo;Hanyu Zhang;Hanfeng Wang;Zhigang Liang;Lihui Cao;Jan S. Rentmeister;Chulsoon Hwang
Accurate end-to-end power integrity simulations require models that include every component in the power distribution network, including voltage regulator modules (VRMs) and on-die capacitors. However, including VRMs in power integrity simulations has been challenging, because power electronic simulation tools are not compatible with typical power integrity simulation tools, and encrypted VRM models for SPICE tools are typically not sufficiently accurate to capture the non-linear behaviors under various load conditions. Herein, a SPICE-compatible behavior modeling method is proposed, which is applied and validated for a practical multiphase VRM in a mobile platform. The simulation model adequately captures the control loops of the VRM, such as single-voltage and multiple current feedback loops. By combining the parameter-based equations from the voltage and current feedback networks, the model reproduces pulse-width and pulse-frequency modulation-based VRM operations. For validation of the behavior model, the design parameters are determined through a two-step process. Finally, the proposed behavior modeling method is experimentally validated with an evaluation board with various load conditions.
{"title":"Method for Transient Behavior Modeling of a Multiphase Voltage Regulator Module for End-to-End Power Integrity Simulation","authors":"Junho Joo;Hanyu Zhang;Hanfeng Wang;Zhigang Liang;Lihui Cao;Jan S. Rentmeister;Chulsoon Hwang","doi":"10.1109/TSIPI.2023.3327233","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3327233","url":null,"abstract":"Accurate end-to-end power integrity simulations require models that include every component in the power distribution network, including voltage regulator modules (VRMs) and on-die capacitors. However, including VRMs in power integrity simulations has been challenging, because power electronic simulation tools are not compatible with typical power integrity simulation tools, and encrypted VRM models for SPICE tools are typically not sufficiently accurate to capture the non-linear behaviors under various load conditions. Herein, a SPICE-compatible behavior modeling method is proposed, which is applied and validated for a practical multiphase VRM in a mobile platform. The simulation model adequately captures the control loops of the VRM, such as single-voltage and multiple current feedback loops. By combining the parameter-based equations from the voltage and current feedback networks, the model reproduces pulse-width and pulse-frequency modulation-based VRM operations. For validation of the behavior model, the design parameters are determined through a two-step process. Finally, the proposed behavior modeling method is experimentally validated with an evaluation board with various load conditions.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"122-133"},"PeriodicalIF":0.0,"publicationDate":"2023-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"109157524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article addresses the optimization of the interface between the photodetector (PD) and the analog front-end in high-speed, high-density optical communication receivers. Specifically, the article focuses on optimizing design elements in the interface, including the interconnecting transmission line, the T-coil, the transimpedance amplifier (TIA), and digital equalization tap weights. To optimize the optical link, we use a combination of analytical models, electromagnetic simulations, and machine learning techniques to describe different interface elements as most appropriate for each. Finally, we use the genetic algorithm to obtain optimal design parameters. The proposed optimization approach leads to a quick design time and reveals insights into some of the best design practices. As an example, we use the proposed method to investigate the relationship between optimal transmission line width and the amount of equalization available on the receiver. These conclusions are further supported by measurements taken on an assembled prototype with various PD-to-TIA interconnect lengths.
{"title":"Optimizing the Photodetector/Analog Front-End Interface in Optical Communication Receivers","authors":"Bahaa Radi;Zonghao Li;Dhruv Patel;Anthony Chan Carusone","doi":"10.1109/TSIPI.2023.3307669","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3307669","url":null,"abstract":"This article addresses the optimization of the interface between the photodetector (PD) and the analog front-end in high-speed, high-density optical communication receivers. Specifically, the article focuses on optimizing design elements in the interface, including the interconnecting transmission line, the T-coil, the transimpedance amplifier (TIA), and digital equalization tap weights. To optimize the optical link, we use a combination of analytical models, electromagnetic simulations, and machine learning techniques to describe different interface elements as most appropriate for each. Finally, we use the genetic algorithm to obtain optimal design parameters. The proposed optimization approach leads to a quick design time and reveals insights into some of the best design practices. As an example, we use the proposed method to investigate the relationship between optimal transmission line width and the amount of equalization available on the receiver. These conclusions are further supported by measurements taken on an assembled prototype with various PD-to-TIA interconnect lengths.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"111-121"},"PeriodicalIF":0.0,"publicationDate":"2023-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/10040918/10227602.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-16DOI: 10.1109/TSIPI.2023.3274090
Siqi Bai;Samuel Connor;Wiren Dale Becker;Bruce Archambeault;Albert E. Ruehli
The inductance of the power/ground planes is an integral contributor to the input impedance of a power delivery network for high-speed printed circuit boards (PCBs) and packages. Conventionally, differential-equation (DE) circuit and cavity type models have been applied to compute the inductive behavior of the plane-to-plane inductance. However, these methods are not suitable for the case where the structures are perforated or involve other uneven structures. In this article, a new partial-element-equivalent-circuit (PEEC)-based method is presented to compute the inductance of parallel plate-like planes and other structures. Examples are given to show that the new method can efficiently compute inductances for multiple integrated circuit power vias, power/ground planes, and multiple decoupling capacitors. The proposed model is validated with both full-wave CEM simulations as well as with measurements. Further, the speed and the accuracy for real PCB and package designs are presented to validate the efficiency as well as the accuracy of the proposed approach. An important aspect of any approach is the limitations for solving real life problems. In this article, we consider important issues related of plane-pair PEEC to power distribution evaluations. Specifically, we show that large holes in planes can accurately be modeled. This is a difficult issue for DE methods. Another surprising practical issue is the accuracy obtained even if the planes are not of the same size. We also consider the speedup, which can be obtained in comparison to solutions for other approaches. This is due to the sparsity of the coupling for the rapid coupling decrease with distance. This short-distance coupling also increases the maximum frequency for which the method can be applied.
{"title":"Inductance Calculation for the Power Net Area Fill of Packages and PCBs Based on Plane-Pair PEEC","authors":"Siqi Bai;Samuel Connor;Wiren Dale Becker;Bruce Archambeault;Albert E. Ruehli","doi":"10.1109/TSIPI.2023.3274090","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3274090","url":null,"abstract":"The inductance of the power/ground planes is an integral contributor to the input impedance of a power delivery network for high-speed printed circuit boards (PCBs) and packages. Conventionally, differential-equation (DE) circuit and cavity type models have been applied to compute the inductive behavior of the plane-to-plane inductance. However, these methods are not suitable for the case where the structures are perforated or involve other uneven structures. In this article, a new partial-element-equivalent-circuit (PEEC)-based method is presented to compute the inductance of parallel plate-like planes and other structures. Examples are given to show that the new method can efficiently compute inductances for multiple integrated circuit power vias, power/ground planes, and multiple decoupling capacitors. The proposed model is validated with both full-wave CEM simulations as well as with measurements. Further, the speed and the accuracy for real PCB and package designs are presented to validate the efficiency as well as the accuracy of the proposed approach. An important aspect of any approach is the limitations for solving real life problems. In this article, we consider important issues related of plane-pair PEEC to power distribution evaluations. Specifically, we show that large holes in planes can accurately be modeled. This is a difficult issue for DE methods. Another surprising practical issue is the accuracy obtained even if the planes are not of the same size. We also consider the speedup, which can be obtained in comparison to solutions for other approaches. This is due to the sparsity of the coupling for the rapid coupling decrease with distance. This short-distance coupling also increases the maximum frequency for which the method can be applied.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"103-110"},"PeriodicalIF":0.0,"publicationDate":"2023-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-18DOI: 10.1109/TSIPI.2023.3268255
Chaofeng Li;Kevin Cai;Muqi Ouyang;Qian Gao;Bidyut Sen;DongHyun Kim
Via transitions in high-speed channels critically influence the signal integrity and power integrity of high-speed systems. In this article, a mode-decomposition-based equivalent model of a high-speed via that can be applied at frequencies up to 100 GHz is proposed for the first time. The equivalent model for modeling the via transition consists of upper and lower via-to-plate capacitances and equivalent parallel-plate impedances, owing to the fundamental mode and higher order modes for parallel-plate, all of which can be calculated from physical geometrical parameters. The via-to-plate capacitances are calculated by using the domain decomposition method in the antipad domain and via domain. The parallel-plate impedances representing via and parallel-plate coupling are calculated with the mode decomposition method for different parallel-plate modes (fundamental and higher order modes) in the parallel-plate domain. The proposed equivalent via model provides more accurate results in the high-frequency range than previously proposed methods. Because the impact of higher order modes on parallel-plate impedance is considered in the proposed mode-decomposition-based via model, and the effects of higher order modes are prominent at high frequencies for printed circuit board (PCB) vias with typical dimensions. The proposed model is validated with numerical examples, which show good correlation at frequencies as high as 100 GHz. The proposed model can be applied to high-speed via transitions in PCBs and packages.
{"title":"Mode-Decomposition-Based Equivalent Model of High-Speed Vias up to 100 GHz","authors":"Chaofeng Li;Kevin Cai;Muqi Ouyang;Qian Gao;Bidyut Sen;DongHyun Kim","doi":"10.1109/TSIPI.2023.3268255","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3268255","url":null,"abstract":"Via transitions in high-speed channels critically influence the signal integrity and power integrity of high-speed systems. In this article, a mode-decomposition-based equivalent model of a high-speed via that can be applied at frequencies up to 100 GHz is proposed for the first time. The equivalent model for modeling the via transition consists of upper and lower via-to-plate capacitances and equivalent parallel-plate impedances, owing to the fundamental mode and higher order modes for parallel-plate, all of which can be calculated from physical geometrical parameters. The via-to-plate capacitances are calculated by using the domain decomposition method in the antipad domain and via domain. The parallel-plate impedances representing via and parallel-plate coupling are calculated with the mode decomposition method for different parallel-plate modes (fundamental and higher order modes) in the parallel-plate domain. The proposed equivalent via model provides more accurate results in the high-frequency range than previously proposed methods. Because the impact of higher order modes on parallel-plate impedance is considered in the proposed mode-decomposition-based via model, and the effects of higher order modes are prominent at high frequencies for printed circuit board (PCB) vias with typical dimensions. The proposed model is validated with numerical examples, which show good correlation at frequencies as high as 100 GHz. The proposed model can be applied to high-speed via transitions in PCBs and packages.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"74-83"},"PeriodicalIF":0.0,"publicationDate":"2023-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-06DOI: 10.1109/TSIPI.2023.3264961
Vinod Kumar Verma;Jai Narayan Tripathi
With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g., jitter, cross-talk, electromagnetic interference, etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE-based simulator as well as doing the same with the experimental results using two different CMOS inverter integrated circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation. Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the SPICE-based simulator and the experiments.
{"title":"Analytical Modeling of Deterministic Jitter in CMOS Inverters","authors":"Vinod Kumar Verma;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2023.3264961","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3264961","url":null,"abstract":"With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g., jitter, cross-talk, electromagnetic interference, etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE-based simulator as well as doing the same with the experimental results using two different CMOS inverter integrated circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation. Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the SPICE-based simulator and the experiments.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"64-73"},"PeriodicalIF":0.0,"publicationDate":"2023-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-22DOI: 10.1109/TSIPI.2023.3278613
Yuanzhuo Liu;Siqi Bai;Chaofeng Li;Vanine Sabino De Moura;Bichen Chen;Srinivas Venkataraman;Xu Wang;DongHyun Kim
To understand the skew in twinax cables of separately extrusion and co-extrusion design, the impact of inhomogeneous dielectric in copper twinax cables is analyzed, with an emphasis on signal integrity performance. The inhomogeneity is treated as a perturbation to the RLGC parameters, and analytical equations for the calculation of scattering parameters from RLGC parameters are derived to analyze the effects of this perturbation on signal integrity. The inhomogeneity leads to a modulation behavior in the scattering parameters, which decreases asymmetry-induced skew at high frequencies and eliminates the resonance of skew in the differential insertion loss. Mathematical analysis, physical explanation, and various design cases are presented for validation.
{"title":"Inhomogeneous Dielectric Induced Skew Modeling of Twinax Cables","authors":"Yuanzhuo Liu;Siqi Bai;Chaofeng Li;Vanine Sabino De Moura;Bichen Chen;Srinivas Venkataraman;Xu Wang;DongHyun Kim","doi":"10.1109/TSIPI.2023.3278613","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3278613","url":null,"abstract":"To understand the skew in twinax cables of separately extrusion and co-extrusion design, the impact of inhomogeneous dielectric in copper twinax cables is analyzed, with an emphasis on signal integrity performance. The inhomogeneity is treated as a perturbation to the RLGC parameters, and analytical equations for the calculation of scattering parameters from RLGC parameters are derived to analyze the effects of this perturbation on signal integrity. The inhomogeneity leads to a modulation behavior in the scattering parameters, which decreases asymmetry-induced skew at high frequencies and eliminates the resonance of skew in the differential insertion loss. Mathematical analysis, physical explanation, and various design cases are presented for validation.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"94-102"},"PeriodicalIF":0.0,"publicationDate":"2023-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Via is a commonly used interconnect structure for vertically connecting signal traces or power or ground planes in packages and boards. As the speed of data transfer increases, the electrical properties of via structure becomes more and more important for getting better signal quality. Modeling a via structure typically involves complex computation. In this article, authors use partial element method to model the structure as coupled inductor array. It first proves that the loop inductance of a single-ended via transition is minimized through perturbation analysis. On the other hand, the differential-mode loop inductance of a via pair surrounded by 2, 4, 6, and 8 ground vias, respectively, is also derived. The full-wave simulation results all show good agreement with the ones predicted by formulae. Thus, with these formulae, the optimization of ground-via placement could be quickly found.
{"title":"Optimization of Ground-via Patterns for via Transitions by Minimizing Loop Inductance","authors":"Pei-Yang Weng;Chun-Lin Liao;Bhyrav Mutnury;Tzong-Lin Wu","doi":"10.1109/TSIPI.2023.3256969","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3256969","url":null,"abstract":"Via is a commonly used interconnect structure for vertically connecting signal traces or power or ground planes in packages and boards. As the speed of data transfer increases, the electrical properties of via structure becomes more and more important for getting better signal quality. Modeling a via structure typically involves complex computation. In this article, authors use partial element method to model the structure as coupled inductor array. It first proves that the loop inductance of a single-ended via transition is minimized through perturbation analysis. On the other hand, the differential-mode loop inductance of a via pair surrounded by 2, 4, 6, and 8 ground vias, respectively, is also derived. The full-wave simulation results all show good agreement with the ones predicted by formulae. Thus, with these formulae, the optimization of ground-via placement could be quickly found.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"43-52"},"PeriodicalIF":0.0,"publicationDate":"2023-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The performances of Ensemble non return-to-zero (ENRZ) under the interferences of crosstalk, along with non-return-to-zero (NRZ), pulse amplitude modulation of three-level (PAM3), and pulse amplitude modulation of four-level (PAM4) are investigated. Two scenarios, 0 dB and high loss, with varying levels of dual-side far-end crosstalk (FEXT) and near-end crosstalk applied, are studied. A detailed description of the ENRZ algorithm is provided. The reasons that lead to the performance edge of ENRZ in contrast to the rest three modulations are analyzed. The methodologies of injecting the crosstalk interferences into the differential/multiwire channels are discussed. A widely existing issue in computing FEXT is pointed out, with the recommended technique presented. A holistic channel simulation method called frequency domain matrix multiplication is employed in this study for its better handling of multiwire-based channels. The simulated eye diagrams obtained with the four modulation techniques are compared and analyzed. The study shows that ENRZ's inherence of insensitivity to channel loss makes it remain robust under the interferences of crosstalk in comparison with the other three types of modulations. Meanwhile, overall ENRZ and NRZ are more robust than PAM3 and PAM4 when the crosstalk level increases.
{"title":"Crosstalk Performance Analysis: ENRZ, NRZ, PAM3, and PAM4","authors":"Sherman Shan Chen;Zhifei Xu;Armin Tajalli;Brian Holden","doi":"10.1109/TSIPI.2023.3253461","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3253461","url":null,"abstract":"The performances of Ensemble non return-to-zero (ENRZ) under the interferences of crosstalk, along with non-return-to-zero (NRZ), pulse amplitude modulation of three-level (PAM3), and pulse amplitude modulation of four-level (PAM4) are investigated. Two scenarios, 0 dB and high loss, with varying levels of dual-side far-end crosstalk (FEXT) and near-end crosstalk applied, are studied. A detailed description of the ENRZ algorithm is provided. The reasons that lead to the performance edge of ENRZ in contrast to the rest three modulations are analyzed. The methodologies of injecting the crosstalk interferences into the differential/multiwire channels are discussed. A widely existing issue in computing FEXT is pointed out, with the recommended technique presented. A holistic channel simulation method called frequency domain matrix multiplication is employed in this study for its better handling of multiwire-based channels. The simulated eye diagrams obtained with the four modulation techniques are compared and analyzed. The study shows that ENRZ's inherence of insensitivity to channel loss makes it remain robust under the interferences of crosstalk in comparison with the other three types of modulations. Meanwhile, overall ENRZ and NRZ are more robust than PAM3 and PAM4 when the crosstalk level increases.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"53-63"},"PeriodicalIF":0.0,"publicationDate":"2023-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-11DOI: 10.1109/TSIPI.2023.3275124
Yan Li;Heyuan Yu;Erping Li
Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural networks, SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity (SI) problems in three-dimensional (3-D) packaging. In this article, the resistance–inductance–capacitance–conductance (RLGC) equivalent circuit of through-silicon vias (TSV) and redistribution layer (RDL) structure was modeled in 3-D packaging. Furthermore, the spike SI issues, such as reflection, delay, and loss of spike signals, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself and not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This article presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.
{"title":"Signal Integrity Analysis of Neuronal Spike Signal in 3-D Packaging","authors":"Yan Li;Heyuan Yu;Erping Li","doi":"10.1109/TSIPI.2023.3275124","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3275124","url":null,"abstract":"Prompted by the continual advancements in artificial intelligence, the neuromorphic chip based on a spiking neural network (SNN) has attracted considerable attention because of its beneficial architecture of memory computing integration. Unlike traditional artificial neural networks, SNNs process information based on discrete-time spikes. This unique spike signal tends to bring an entire new series of signal integrity (SI) problems in three-dimensional (3-D) packaging. In this article, the resistance–inductance–capacitance–conductance (RLGC) equivalent circuit of through-silicon vias (TSV) and redistribution layer (RDL) structure was modeled in 3-D packaging. Furthermore, the spike SI issues, such as reflection, delay, and loss of spike signals, were also analyzed in 3-D packaging. The results illustrated that the corners between RDL and TSV in 3-D packaging could lead to reflections on the spike signals, resulting in distorted waveforms and increased signal loss. The time delay of the spike signal is only related to the electrical characteristics of the transmission link itself and not to the input signal. In addition, the SI of the spike signal was simulated with possible internal voids as well as the open and short defects in the 3-D packaging. The findings also demonstrated that both open and short defects distort the spike signal's waveform, whereas internal voids almost do not affect the signal. This article presents the first systematic analysis of numerous SI issues of spike signals in 3-D packaging while providing a specific reference for designing neuromorphic chips.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"84-93"},"PeriodicalIF":0.0,"publicationDate":"2023-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898146","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-02-23DOI: 10.1109/TSIPI.2023.3248539
Jiayi He;Ling Zhang;Zurab Kiguradze;Arun Chada;Adam Klivans;Bhyrav Mutnury;Er-Ping Li;Jun Fan
This article presents a flexible and efficient methodology to optimize stack-up for multilayer printed circuit boards (PCBs) with enormous search space and various design constraints. PCB stack-up optimization is crucial in high-speed system design to achieve the desired electrical performance while reducing system costs. The stack-up optimization process is labor-intensive and time-consuming for a large number of layers. Moreover, after the optimization process, the electrical performance of a real design, such as the impedance and loss, may deviate from the target design due to manufacturing variations. Estimating the worst cases due to the manufacturing variations, referred to as “corner cases” in this article, is essential for a confident PCB design but challenging since the number of related parameters is large. In this article, PCB stack-up optimization and corner-case searching are addressed and greatly accelerated using the integer programming technique. All constraints are converted to mathematical equalities and inequalities that can be solved rapidly by an integer programming solver to obtain feasible stack-up solutions. After the cross sections of the transmission lines are optimized based on the stack-up design to achieve a target electrical performance, the upper and lower bound of impedance and loss are acquired using integer programming when the design parameters vary in a particular range. The proposed method is verified using multilayer PCB designs with practical constraints and demonstrates its effectiveness and high efficiency.
{"title":"Fast PCB Stack-Up Optimization Using Integer Programming","authors":"Jiayi He;Ling Zhang;Zurab Kiguradze;Arun Chada;Adam Klivans;Bhyrav Mutnury;Er-Ping Li;Jun Fan","doi":"10.1109/TSIPI.2023.3248539","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3248539","url":null,"abstract":"This article presents a flexible and efficient methodology to optimize stack-up for multilayer printed circuit boards (PCBs) with enormous search space and various design constraints. PCB stack-up optimization is crucial in high-speed system design to achieve the desired electrical performance while reducing system costs. The stack-up optimization process is labor-intensive and time-consuming for a large number of layers. Moreover, after the optimization process, the electrical performance of a real design, such as the impedance and loss, may deviate from the target design due to manufacturing variations. Estimating the worst cases due to the manufacturing variations, referred to as “corner cases” in this article, is essential for a confident PCB design but challenging since the number of related parameters is large. In this article, PCB stack-up optimization and corner-case searching are addressed and greatly accelerated using the integer programming technique. All constraints are converted to mathematical equalities and inequalities that can be solved rapidly by an integer programming solver to obtain feasible stack-up solutions. After the cross sections of the transmission lines are optimized based on the stack-up design to achieve a target electrical performance, the upper and lower bound of impedance and loss are acquired using integer programming when the design parameters vary in a particular range. The proposed method is verified using multilayer PCB designs with practical constraints and demonstrates its effectiveness and high efficiency.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"32-42"},"PeriodicalIF":0.0,"publicationDate":"2023-02-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896243","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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