Pub Date : 2023-12-21DOI: 10.1109/TSIPI.2023.3343021
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2023.3343021","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3343021","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10368591","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-12-05DOI: 10.1109/TSIPI.2023.3339445
Ze Sun;Jian Liu;Xiaoyan Xiong;DongHyun Kim;Daryl Beetner;Victor Khilkevich
Transmission lines with meshed return planes offer enhanced flexibility but can introduce signal integrity challenges. Characterizing such transmission lines using full-wave simulation is accurate but time and resource intensive. In response, an efficient modeling method using 2-D analysis is proposed in this article. First, cross sections of the transmission line are taken at multiple locations to create a sampled representation of the changing geometry. The per-unit-length (PUL) RLGC parameters of each segment are obtained using 2-D analysis. The value of the inductance obtained from the 2-D analysis is then modified to account for the position-dependent current direction on the return plane. Finally, the segments are cascaded together to obtain the $S$ -parameters of the transmission line. The results obtained using this method closely align with those from 3-D full-wave simulations, demonstrating the effectiveness and efficiency of the proposed approach.
{"title":"Characterization of a Microstrip Line Referenced to a Meshed Return Plane Using 2-D Analysis","authors":"Ze Sun;Jian Liu;Xiaoyan Xiong;DongHyun Kim;Daryl Beetner;Victor Khilkevich","doi":"10.1109/TSIPI.2023.3339445","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3339445","url":null,"abstract":"Transmission lines with meshed return planes offer enhanced flexibility but can introduce signal integrity challenges. Characterizing such transmission lines using full-wave simulation is accurate but time and resource intensive. In response, an efficient modeling method using 2-D analysis is proposed in this article. First, cross sections of the transmission line are taken at multiple locations to create a sampled representation of the changing geometry. The per-unit-length (PUL) RLGC parameters of each segment are obtained using 2-D analysis. The value of the inductance obtained from the 2-D analysis is then modified to account for the position-dependent current direction on the return plane. Finally, the segments are cascaded together to obtain the \u0000<inline-formula><tex-math>$S$</tex-math></inline-formula>\u0000-parameters of the transmission line. The results obtained using this method closely align with those from 3-D full-wave simulations, demonstrating the effectiveness and efficiency of the proposed approach.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"13-20"},"PeriodicalIF":0.0,"publicationDate":"2023-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139034232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-11-22DOI: 10.1109/TSIPI.2023.3335330
Joshua A. Rosenau;Aldo W. Morales;Sedig S. Agili;Truong X. Tran
Compared to differential signaling, single-ended signaling is significantly more susceptible to far-end crosstalk; however, single-ended communication is still the preferred data transfer method to use in high-density applications, such as in double data rate (DDR) systems. It has been shown that for loosely coupled single-ended transmission lines, far-end crosstalk (FEXT) on a victim line is proportional to a scaled negative derivative of the far-end signal on the aggressor line; thus, a variety of crosstalk derivative cancelation techniques have been developed. However, when channels are tightly coupled, the derivative cancelation method fails, thus preventing its use at higher data rates. In this article, we examine the derivative-based crosstalk-cancelation technique, and then provide reasons as to why it fails at higher data rates and develop a rule establishing when it can be used. We also propose the use of a time delay neural network crosstalk canceler (NNXC) to cancel FEXT. The proposed crosstalk canceler can operate at significantly higher data rates than cancelers using the derivative-based method. The NNXC can also be used in systems with multiple tightly spaced channels, which is not possible using the derivative method. Furthermore, when a clock signal is available, such as in DDR systems, it can be used as part of the network's training sequence–––significantly improving the performance of the NNXC in reducing far-end crosstalk. Several simulations are shown depicting the superior performance of the NNXC canceler, including in a realistic DDR5 channel with tightly coupled lines.
{"title":"Using Neural Networks for Far-End Crosstalk Compensation in High-Speed MIMO Channels","authors":"Joshua A. Rosenau;Aldo W. Morales;Sedig S. Agili;Truong X. Tran","doi":"10.1109/TSIPI.2023.3335330","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3335330","url":null,"abstract":"Compared to differential signaling, single-ended signaling is significantly more susceptible to far-end crosstalk; however, single-ended communication is still the preferred data transfer method to use in high-density applications, such as in double data rate (DDR) systems. It has been shown that for loosely coupled single-ended transmission lines, far-end crosstalk (FEXT) on a victim line is proportional to a scaled negative derivative of the far-end signal on the aggressor line; thus, a variety of crosstalk derivative cancelation techniques have been developed. However, when channels are tightly coupled, the derivative cancelation method fails, thus preventing its use at higher data rates. In this article, we examine the derivative-based crosstalk-cancelation technique, and then provide reasons as to why it fails at higher data rates and develop a rule establishing when it can be used. We also propose the use of a time delay neural network crosstalk canceler (NNXC) to cancel FEXT. The proposed crosstalk canceler can operate at significantly higher data rates than cancelers using the derivative-based method. The NNXC can also be used in systems with multiple tightly spaced channels, which is not possible using the derivative method. Furthermore, when a clock signal is available, such as in DDR systems, it can be used as part of the network's training sequence–––significantly improving the performance of the NNXC in reducing far-end crosstalk. Several simulations are shown depicting the superior performance of the NNXC canceler, including in a realistic DDR5 channel with tightly coupled lines.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2023-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138633934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-25DOI: 10.1109/TSIPI.2023.3327228
Li-Ching Huang;Tzong-Lin Wu
Recently, a novel power delivery network (PDN) noise absorber with low | S 21 | is proposed to match the radial port impedance of the incident cylindrical wave, thus preventing high-frequency power noise transmission and further avoiding the cavity resonances at the noise source end. Despite the excellent performance, no analytical formulas can quantify the improvements, and an optimized solution derived more scientifically to minimize power noises is expected. Therefore, this article dives into the cylindrical wave theory and constructs a contour-plot-based methodology for designing the optimized PDN noise absorbers. To validate the proposed method, parallel plates with a ring of optimized PDN noise absorbers are implemented, leading to 6.2% lower self impedance and up to 45.6% lower transfer impedance at 5.5 GHz when compared with the previous fully-matched absorbers’ case. All the measured results agree well with the theory and full-wave simulated results.
{"title":"Theory-Based Contour Plot Analysis for Optimized Power Delivery Network Noise Absorber","authors":"Li-Ching Huang;Tzong-Lin Wu","doi":"10.1109/TSIPI.2023.3327228","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3327228","url":null,"abstract":"Recently, a novel power delivery network (PDN) noise absorber with low |\u0000<italic>S</i>\u0000<sub>21</sub>\u0000| is proposed to match the radial port impedance of the incident cylindrical wave, thus preventing high-frequency power noise transmission and further avoiding the cavity resonances at the noise source end. Despite the excellent performance, no analytical formulas can quantify the improvements, and an optimized solution derived more scientifically to minimize power noises is expected. Therefore, this article dives into the cylindrical wave theory and constructs a contour-plot-based methodology for designing the optimized PDN noise absorbers. To validate the proposed method, parallel plates with a ring of optimized PDN noise absorbers are implemented, leading to 6.2% lower self impedance and up to 45.6% lower transfer impedance at 5.5 GHz when compared with the previous fully-matched absorbers’ case. All the measured results agree well with the theory and full-wave simulated results.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"134-144"},"PeriodicalIF":0.0,"publicationDate":"2023-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"109157517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-10-25DOI: 10.1109/TSIPI.2023.3327233
Junho Joo;Hanyu Zhang;Hanfeng Wang;Zhigang Liang;Lihui Cao;Jan S. Rentmeister;Chulsoon Hwang
Accurate end-to-end power integrity simulations require models that include every component in the power distribution network, including voltage regulator modules (VRMs) and on-die capacitors. However, including VRMs in power integrity simulations has been challenging, because power electronic simulation tools are not compatible with typical power integrity simulation tools, and encrypted VRM models for SPICE tools are typically not sufficiently accurate to capture the non-linear behaviors under various load conditions. Herein, a SPICE-compatible behavior modeling method is proposed, which is applied and validated for a practical multiphase VRM in a mobile platform. The simulation model adequately captures the control loops of the VRM, such as single-voltage and multiple current feedback loops. By combining the parameter-based equations from the voltage and current feedback networks, the model reproduces pulse-width and pulse-frequency modulation-based VRM operations. For validation of the behavior model, the design parameters are determined through a two-step process. Finally, the proposed behavior modeling method is experimentally validated with an evaluation board with various load conditions.
{"title":"Method for Transient Behavior Modeling of a Multiphase Voltage Regulator Module for End-to-End Power Integrity Simulation","authors":"Junho Joo;Hanyu Zhang;Hanfeng Wang;Zhigang Liang;Lihui Cao;Jan S. Rentmeister;Chulsoon Hwang","doi":"10.1109/TSIPI.2023.3327233","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3327233","url":null,"abstract":"Accurate end-to-end power integrity simulations require models that include every component in the power distribution network, including voltage regulator modules (VRMs) and on-die capacitors. However, including VRMs in power integrity simulations has been challenging, because power electronic simulation tools are not compatible with typical power integrity simulation tools, and encrypted VRM models for SPICE tools are typically not sufficiently accurate to capture the non-linear behaviors under various load conditions. Herein, a SPICE-compatible behavior modeling method is proposed, which is applied and validated for a practical multiphase VRM in a mobile platform. The simulation model adequately captures the control loops of the VRM, such as single-voltage and multiple current feedback loops. By combining the parameter-based equations from the voltage and current feedback networks, the model reproduces pulse-width and pulse-frequency modulation-based VRM operations. For validation of the behavior model, the design parameters are determined through a two-step process. Finally, the proposed behavior modeling method is experimentally validated with an evaluation board with various load conditions.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"122-133"},"PeriodicalIF":0.0,"publicationDate":"2023-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"109157524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This article addresses the optimization of the interface between the photodetector (PD) and the analog front-end in high-speed, high-density optical communication receivers. Specifically, the article focuses on optimizing design elements in the interface, including the interconnecting transmission line, the T-coil, the transimpedance amplifier (TIA), and digital equalization tap weights. To optimize the optical link, we use a combination of analytical models, electromagnetic simulations, and machine learning techniques to describe different interface elements as most appropriate for each. Finally, we use the genetic algorithm to obtain optimal design parameters. The proposed optimization approach leads to a quick design time and reveals insights into some of the best design practices. As an example, we use the proposed method to investigate the relationship between optimal transmission line width and the amount of equalization available on the receiver. These conclusions are further supported by measurements taken on an assembled prototype with various PD-to-TIA interconnect lengths.
{"title":"Optimizing the Photodetector/Analog Front-End Interface in Optical Communication Receivers","authors":"Bahaa Radi;Zonghao Li;Dhruv Patel;Anthony Chan Carusone","doi":"10.1109/TSIPI.2023.3307669","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3307669","url":null,"abstract":"This article addresses the optimization of the interface between the photodetector (PD) and the analog front-end in high-speed, high-density optical communication receivers. Specifically, the article focuses on optimizing design elements in the interface, including the interconnecting transmission line, the T-coil, the transimpedance amplifier (TIA), and digital equalization tap weights. To optimize the optical link, we use a combination of analytical models, electromagnetic simulations, and machine learning techniques to describe different interface elements as most appropriate for each. Finally, we use the genetic algorithm to obtain optimal design parameters. The proposed optimization approach leads to a quick design time and reveals insights into some of the best design practices. As an example, we use the proposed method to investigate the relationship between optimal transmission line width and the amount of equalization available on the receiver. These conclusions are further supported by measurements taken on an assembled prototype with various PD-to-TIA interconnect lengths.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"111-121"},"PeriodicalIF":0.0,"publicationDate":"2023-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/10040918/10227602.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-06-16DOI: 10.1109/TSIPI.2023.3274090
Siqi Bai;Samuel Connor;Wiren Dale Becker;Bruce Archambeault;Albert E. Ruehli
The inductance of the power/ground planes is an integral contributor to the input impedance of a power delivery network for high-speed printed circuit boards (PCBs) and packages. Conventionally, differential-equation (DE) circuit and cavity type models have been applied to compute the inductive behavior of the plane-to-plane inductance. However, these methods are not suitable for the case where the structures are perforated or involve other uneven structures. In this article, a new partial-element-equivalent-circuit (PEEC)-based method is presented to compute the inductance of parallel plate-like planes and other structures. Examples are given to show that the new method can efficiently compute inductances for multiple integrated circuit power vias, power/ground planes, and multiple decoupling capacitors. The proposed model is validated with both full-wave CEM simulations as well as with measurements. Further, the speed and the accuracy for real PCB and package designs are presented to validate the efficiency as well as the accuracy of the proposed approach. An important aspect of any approach is the limitations for solving real life problems. In this article, we consider important issues related of plane-pair PEEC to power distribution evaluations. Specifically, we show that large holes in planes can accurately be modeled. This is a difficult issue for DE methods. Another surprising practical issue is the accuracy obtained even if the planes are not of the same size. We also consider the speedup, which can be obtained in comparison to solutions for other approaches. This is due to the sparsity of the coupling for the rapid coupling decrease with distance. This short-distance coupling also increases the maximum frequency for which the method can be applied.
{"title":"Inductance Calculation for the Power Net Area Fill of Packages and PCBs Based on Plane-Pair PEEC","authors":"Siqi Bai;Samuel Connor;Wiren Dale Becker;Bruce Archambeault;Albert E. Ruehli","doi":"10.1109/TSIPI.2023.3274090","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3274090","url":null,"abstract":"The inductance of the power/ground planes is an integral contributor to the input impedance of a power delivery network for high-speed printed circuit boards (PCBs) and packages. Conventionally, differential-equation (DE) circuit and cavity type models have been applied to compute the inductive behavior of the plane-to-plane inductance. However, these methods are not suitable for the case where the structures are perforated or involve other uneven structures. In this article, a new partial-element-equivalent-circuit (PEEC)-based method is presented to compute the inductance of parallel plate-like planes and other structures. Examples are given to show that the new method can efficiently compute inductances for multiple integrated circuit power vias, power/ground planes, and multiple decoupling capacitors. The proposed model is validated with both full-wave CEM simulations as well as with measurements. Further, the speed and the accuracy for real PCB and package designs are presented to validate the efficiency as well as the accuracy of the proposed approach. An important aspect of any approach is the limitations for solving real life problems. In this article, we consider important issues related of plane-pair PEEC to power distribution evaluations. Specifically, we show that large holes in planes can accurately be modeled. This is a difficult issue for DE methods. Another surprising practical issue is the accuracy obtained even if the planes are not of the same size. We also consider the speedup, which can be obtained in comparison to solutions for other approaches. This is due to the sparsity of the coupling for the rapid coupling decrease with distance. This short-distance coupling also increases the maximum frequency for which the method can be applied.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"103-110"},"PeriodicalIF":0.0,"publicationDate":"2023-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67896249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-18DOI: 10.1109/TSIPI.2023.3268255
Chaofeng Li;Kevin Cai;Muqi Ouyang;Qian Gao;Bidyut Sen;DongHyun Kim
Via transitions in high-speed channels critically influence the signal integrity and power integrity of high-speed systems. In this article, a mode-decomposition-based equivalent model of a high-speed via that can be applied at frequencies up to 100 GHz is proposed for the first time. The equivalent model for modeling the via transition consists of upper and lower via-to-plate capacitances and equivalent parallel-plate impedances, owing to the fundamental mode and higher order modes for parallel-plate, all of which can be calculated from physical geometrical parameters. The via-to-plate capacitances are calculated by using the domain decomposition method in the antipad domain and via domain. The parallel-plate impedances representing via and parallel-plate coupling are calculated with the mode decomposition method for different parallel-plate modes (fundamental and higher order modes) in the parallel-plate domain. The proposed equivalent via model provides more accurate results in the high-frequency range than previously proposed methods. Because the impact of higher order modes on parallel-plate impedance is considered in the proposed mode-decomposition-based via model, and the effects of higher order modes are prominent at high frequencies for printed circuit board (PCB) vias with typical dimensions. The proposed model is validated with numerical examples, which show good correlation at frequencies as high as 100 GHz. The proposed model can be applied to high-speed via transitions in PCBs and packages.
{"title":"Mode-Decomposition-Based Equivalent Model of High-Speed Vias up to 100 GHz","authors":"Chaofeng Li;Kevin Cai;Muqi Ouyang;Qian Gao;Bidyut Sen;DongHyun Kim","doi":"10.1109/TSIPI.2023.3268255","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3268255","url":null,"abstract":"Via transitions in high-speed channels critically influence the signal integrity and power integrity of high-speed systems. In this article, a mode-decomposition-based equivalent model of a high-speed via that can be applied at frequencies up to 100 GHz is proposed for the first time. The equivalent model for modeling the via transition consists of upper and lower via-to-plate capacitances and equivalent parallel-plate impedances, owing to the fundamental mode and higher order modes for parallel-plate, all of which can be calculated from physical geometrical parameters. The via-to-plate capacitances are calculated by using the domain decomposition method in the antipad domain and via domain. The parallel-plate impedances representing via and parallel-plate coupling are calculated with the mode decomposition method for different parallel-plate modes (fundamental and higher order modes) in the parallel-plate domain. The proposed equivalent via model provides more accurate results in the high-frequency range than previously proposed methods. Because the impact of higher order modes on parallel-plate impedance is considered in the proposed mode-decomposition-based via model, and the effects of higher order modes are prominent at high frequencies for printed circuit board (PCB) vias with typical dimensions. The proposed model is validated with numerical examples, which show good correlation at frequencies as high as 100 GHz. The proposed model can be applied to high-speed via transitions in PCBs and packages.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"74-83"},"PeriodicalIF":0.0,"publicationDate":"2023-04-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-04-06DOI: 10.1109/TSIPI.2023.3264961
Vinod Kumar Verma;Jai Narayan Tripathi
With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g., jitter, cross-talk, electromagnetic interference, etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE-based simulator as well as doing the same with the experimental results using two different CMOS inverter integrated circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation. Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the SPICE-based simulator and the experiments.
{"title":"Analytical Modeling of Deterministic Jitter in CMOS Inverters","authors":"Vinod Kumar Verma;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2023.3264961","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3264961","url":null,"abstract":"With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g., jitter, cross-talk, electromagnetic interference, etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE-based simulator as well as doing the same with the experimental results using two different CMOS inverter integrated circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation. Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the SPICE-based simulator and the experiments.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"64-73"},"PeriodicalIF":0.0,"publicationDate":"2023-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-03-22DOI: 10.1109/TSIPI.2023.3278613
Yuanzhuo Liu;Siqi Bai;Chaofeng Li;Vanine Sabino De Moura;Bichen Chen;Srinivas Venkataraman;Xu Wang;DongHyun Kim
To understand the skew in twinax cables of separately extrusion and co-extrusion design, the impact of inhomogeneous dielectric in copper twinax cables is analyzed, with an emphasis on signal integrity performance. The inhomogeneity is treated as a perturbation to the RLGC parameters, and analytical equations for the calculation of scattering parameters from RLGC parameters are derived to analyze the effects of this perturbation on signal integrity. The inhomogeneity leads to a modulation behavior in the scattering parameters, which decreases asymmetry-induced skew at high frequencies and eliminates the resonance of skew in the differential insertion loss. Mathematical analysis, physical explanation, and various design cases are presented for validation.
{"title":"Inhomogeneous Dielectric Induced Skew Modeling of Twinax Cables","authors":"Yuanzhuo Liu;Siqi Bai;Chaofeng Li;Vanine Sabino De Moura;Bichen Chen;Srinivas Venkataraman;Xu Wang;DongHyun Kim","doi":"10.1109/TSIPI.2023.3278613","DOIUrl":"https://doi.org/10.1109/TSIPI.2023.3278613","url":null,"abstract":"To understand the skew in twinax cables of separately extrusion and co-extrusion design, the impact of inhomogeneous dielectric in copper twinax cables is analyzed, with an emphasis on signal integrity performance. The inhomogeneity is treated as a perturbation to the RLGC parameters, and analytical equations for the calculation of scattering parameters from RLGC parameters are derived to analyze the effects of this perturbation on signal integrity. The inhomogeneity leads to a modulation behavior in the scattering parameters, which decreases asymmetry-induced skew at high frequencies and eliminates the resonance of skew in the differential insertion loss. Mathematical analysis, physical explanation, and various design cases are presented for validation.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"2 ","pages":"94-102"},"PeriodicalIF":0.0,"publicationDate":"2023-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67898147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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