Pub Date : 2022-11-16DOI: 10.1109/TSIPI.2022.3222747
Yuanzhuo Liu;Yuandong Guo;Chaofeng Li;Siqi Bai;Bichen Chen;Srinivas Venkataraman;Xu Wang;Jun Fan;DongHyun Kim
Phase noise represents signal instabilities in the frequency domain and is assessed through power measurements at various offsets from the carrier frequency. Herein, the phase noise of a clock generator is analyzed and modeled. Sources for the phase noise of the clock output at the resonance frequency are identified, including the power supply, the heatsink, and the external crystal. Low-frequency resonance is detected and validated to be caused by the external crystal grounding design. Solutions to decrease crystal-related noise are proposed and validated. In addition, the sensitivity based on the signal-to-noise ratio is proposed and verified with measurements to numerically analyze the effects of power supply noise on clock phase noise. The proposed phase noise sensitivity is extracted from the measured phase noise results and can be used to estimate the phase noise and jitter of different power supply noises. The extraction and prediction methods are validated with different buffer types, including low-voltage differential signal, high-speed current steering logic, low-voltage positive emitter-coupled logic, and low-voltage complementary metal–oxide–semiconductor, in a device under test with the given design.
{"title":"Phase Noise Analysis of Clock Generator by Using Phase Noise Sensitivity","authors":"Yuanzhuo Liu;Yuandong Guo;Chaofeng Li;Siqi Bai;Bichen Chen;Srinivas Venkataraman;Xu Wang;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2022.3222747","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3222747","url":null,"abstract":"Phase noise represents signal instabilities in the frequency domain and is assessed through power measurements at various offsets from the carrier frequency. Herein, the phase noise of a clock generator is analyzed and modeled. Sources for the phase noise of the clock output at the resonance frequency are identified, including the power supply, the heatsink, and the external crystal. Low-frequency resonance is detected and validated to be caused by the external crystal grounding design. Solutions to decrease crystal-related noise are proposed and validated. In addition, the sensitivity based on the signal-to-noise ratio is proposed and verified with measurements to numerically analyze the effects of power supply noise on clock phase noise. The proposed phase noise sensitivity is extracted from the measured phase noise results and can be used to estimate the phase noise and jitter of different power supply noises. The extraction and prediction methods are validated with different buffer types, including low-voltage differential signal, high-speed current steering logic, low-voltage positive emitter-coupled logic, and low-voltage complementary metal–oxide–semiconductor, in a device under test with the given design.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"150-159"},"PeriodicalIF":0.0,"publicationDate":"2022-11-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842405","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-25DOI: 10.1109/TSIPI.2022.3217109
Heman Vaghasiya;Akash Jain;Jai Narayan Tripathi
The design and optimization of power delivery networks (PDNs) in very large scale integration systems are becoming very challenging with the increasing complexity of such systems. Decoupling capacitors are the key elements used in a PDN to minimize power supply noise and to maintain low impedance of the PDN to avoid system failure. In this article, a novel approach using surrogate-assisted swarm intelligence is presented for efficient and fast optimization of PDNs. For generating the surrogate models, a standard radial basis function network is used. Using the proposed approach, the decoupling capacitors are selected and placed optimally, eventually reducing the cumulative impedance of the PDN below the target impedance. The performance comparison between the conventional and the surrogate-assisted approach is presented. Three case studies are presented on a practical system to demonstrate the competence of the proposed approach. The results obtained by the proposed approach are also compared with the same obtained by the state-of-the-art approaches. For the proposed approach, the runtime is drastically reduced compared to the state-of-the-art approaches for the optimization problem without having any effect on the performance. The consistency of results in all of the case studies confirms the validity of the proposed approach.
{"title":"A Radial Basis Function Network-Based Surrogate-Assisted Swarm Intelligence Approach for Fast Optimization of Power Delivery Networks","authors":"Heman Vaghasiya;Akash Jain;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2022.3217109","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3217109","url":null,"abstract":"The design and optimization of power delivery networks (PDNs) in very large scale integration systems are becoming very challenging with the increasing complexity of such systems. Decoupling capacitors are the key elements used in a PDN to minimize power supply noise and to maintain low impedance of the PDN to avoid system failure. In this article, a novel approach using surrogate-assisted swarm intelligence is presented for efficient and fast optimization of PDNs. For generating the surrogate models, a standard radial basis function network is used. Using the proposed approach, the decoupling capacitors are selected and placed optimally, eventually reducing the cumulative impedance of the PDN below the target impedance. The performance comparison between the conventional and the surrogate-assisted approach is presented. Three case studies are presented on a practical system to demonstrate the competence of the proposed approach. The results obtained by the proposed approach are also compared with the same obtained by the state-of-the-art approaches. For the proposed approach, the runtime is drastically reduced compared to the state-of-the-art approaches for the optimization problem without having any effect on the performance. The consistency of results in all of the case studies confirms the validity of the proposed approach.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"140-149"},"PeriodicalIF":0.0,"publicationDate":"2022-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-12DOI: 10.1109/TSIPI.2022.3214172
Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;Victor Khilkevich;DongHyun Kim
The difference in the dielectric permittivity of the different dielectric layers (including air) surrounding the microstrip is one of the major contributors to the far-end crosstalk (FEXT) in microstrip lines. The dielectric of the microstrip in printed circuit boards (PCBs) fabrication usually consists of two layers: the solder mask layer and the substrate layer. The characterization of the relative permittivity ( ${boldsymbol{varepsilon }}_{boldsymbol{r}}$ ) and dielectric dissipation factor (tan δ ) for the dielectric layers of the microstrip are important parameters for board-level electronic system designs. In addition, the foil surface roughness cannot be ignored for the conductor loss modeling. In this work, an extraction method with high accuracy is proposed to characterize the dielectric material and foil surface roughness properties from the measured S-parameters with known cross-sectional geometry up to 20 GHz. With the extracted properties, the FEXT and insertion loss of the microstrip can be estimated more accurately, providing design guidelines for PCB design and the material selection of the microstrip.
{"title":"An Empirical Modeling of Far-End Crosstalk and Insertion Loss in Microstrip Lines","authors":"Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;Victor Khilkevich;DongHyun Kim","doi":"10.1109/TSIPI.2022.3214172","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3214172","url":null,"abstract":"The difference in the dielectric permittivity of the different dielectric layers (including air) surrounding the microstrip is one of the major contributors to the far-end crosstalk (FEXT) in microstrip lines. The dielectric of the microstrip in printed circuit boards (PCBs) fabrication usually consists of two layers: the solder mask layer and the substrate layer. The characterization of the relative permittivity (\u0000<inline-formula><tex-math>${boldsymbol{varepsilon }}_{boldsymbol{r}}$</tex-math></inline-formula>\u0000) and dielectric dissipation factor (tan\u0000<italic>δ</i>\u0000) for the dielectric layers of the microstrip are important parameters for board-level electronic system designs. In addition, the foil surface roughness cannot be ignored for the conductor loss modeling. In this work, an extraction method with high accuracy is proposed to characterize the dielectric material and foil surface roughness properties from the measured S-parameters with known cross-sectional geometry up to 20 GHz. With the extracted properties, the FEXT and insertion loss of the microstrip can be estimated more accurately, providing design guidelines for PCB design and the material selection of the microstrip.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"130-139"},"PeriodicalIF":0.0,"publicationDate":"2022-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-09-28DOI: 10.1109/TSIPI.2022.3209138
Siqi Bai;Yuanzhuo Liu;Jongjoo Lee;Bichen Chen;Srinivas Venkataraman;Xu Wang;Bo Pu;Jun Fan;DongHyun Kim
Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced.
{"title":"Analysis of Power-via-Induced Quasi-Quarter-Wavelength Resonance to Reduce Crosstalk","authors":"Siqi Bai;Yuanzhuo Liu;Jongjoo Lee;Bichen Chen;Srinivas Venkataraman;Xu Wang;Bo Pu;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2022.3209138","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3209138","url":null,"abstract":"Currently, power pins are increasingly used in package design to serve a dual purpose: to support crosstalk isolation between high-speed signals and to provide power delivery to serializer/deserializer input/output. This approach can reduce the overall pin count and subsequently limit the package body size to remain within a ball grid array form factor. However, for printed circuit boards (PCBs) in which power vias are adjacent to signal vias, increased far-end crosstalk (FEXT) and resonance in insertion loss can be observed, due to the quasi-quarter-wavelength resonance of the power via stub. Using an analytical model and 3-D full-wave simulation models, a physical explanation for this unexpected resonance in differential signal pairs is proposed. Considering the difficulty in changing the pin map of the IC package, several PCB layouts are proposed to eliminate the power-via-induced quasi-quarter-wavelength resonance without the need to change the package pin map. Upon application of the proposed methods, the resonance is eliminated, and the FEXT is reduced.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"121-129"},"PeriodicalIF":0.0,"publicationDate":"2022-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-31DOI: 10.1109/TSIPI.2022.3203031
Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;DongHyun Kim
Far-end crosstalk (FEXT) is a critical factor that limits signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCBs). The dielectric of the stripline is manufactured with multiple inhomogeneous dielectric layers (IDLs) of various resin and glass fiber bundles. A marginal difference in the dielectric permittivity of the IDLs can lead to a significant change FEXT level. In this article, a practical FEXT modeling methodology for striplines is proposed by introducing the extraction method for ${{boldsymbol{varepsilon }}}_{boldsymbol{r}}$ of IDLs. The new stripline model is constructed with three IDLs comprised of core, prepreg, and resin pocket, to improve the model accuracy. With the cross-sectional geometry and measured S-parameters of the coupled striplines, ${{boldsymbol{varepsilon }}}_{boldsymbol{r}}$ of IDLs can be extracted. In addition, an analytical model to predict the FEXT polarity and magnitude of the stripline caused by the inhomogeneity is proposed targeted for prelayout application. The proposed models have been verified using measurement. The proposed models can provide useful analysis methodology and design guidelines to mitigate the FEXT level in high-speed systems, especially for high-volume PCB tests in the prelayout and postlayout stages.
{"title":"Far-End Crosstalk Modeling and Prediction for Stripline With Inhomogeneous Dielectric Layers (IDLs)","authors":"Yuanzhuo Liu;Shaohui Yong;Yuandong Guo;Jiayi He;Chaofeng Li;Xiaoning Ye;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2022.3203031","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3203031","url":null,"abstract":"Far-end crosstalk (FEXT) is a critical factor that limits signal integrity performance in high-speed systems. The FEXT level is sensitive to the dielectric inhomogeneity of the stripline in fabricated printed circuit boards (PCBs). The dielectric of the stripline is manufactured with multiple inhomogeneous dielectric layers (IDLs) of various resin and glass fiber bundles. A marginal difference in the dielectric permittivity of the IDLs can lead to a significant change FEXT level. In this article, a practical FEXT modeling methodology for striplines is proposed by introducing the extraction method for \u0000<inline-formula><tex-math>${{boldsymbol{varepsilon }}}_{boldsymbol{r}}$</tex-math></inline-formula>\u0000 of IDLs. The new stripline model is constructed with three IDLs comprised of core, prepreg, and resin pocket, to improve the model accuracy. With the cross-sectional geometry and measured S-parameters of the coupled striplines, \u0000<inline-formula><tex-math>${{boldsymbol{varepsilon }}}_{boldsymbol{r}}$</tex-math></inline-formula>\u0000 of IDLs can be extracted. In addition, an analytical model to predict the FEXT polarity and magnitude of the stripline caused by the inhomogeneity is proposed targeted for prelayout application. The proposed models have been verified using measurement. The proposed models can provide useful analysis methodology and design guidelines to mitigate the FEXT level in high-speed systems, especially for high-volume PCB tests in the prelayout and postlayout stages.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"93-103"},"PeriodicalIF":0.0,"publicationDate":"2022-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-29DOI: 10.1109/TSIPI.2022.3202150
Aksh Chordia;Jai Narayan Tripathi
This work aims to analyze the variability of integrated circuits and systems. An automated framework is presented for variability analysis that exploits the metaheuristic optimization techniques. The efficacy of the proposed approach is demonstrated by two case studies—one is the estimation of variability in phase noise in RF CMOS LC tank oscillators (frequency domain analysis) and the other is the estimation of variability in the differential output signal of a current mode driver (time-domain analysis). The proposed approach is investigated and validated by comparing the results from the traditional Monte Carlo simulations and the ordinary least-squares-based polynomial chaos expansion. A significant gain in the computational time is reported while maintaining accuracy in the results. The proposed methodology is not just limited to variability analysis applications but also can be used to solve the circuit optimization problems.
{"title":"An Automated Framework for Variability Analysis for Integrated Circuits Using Metaheuristics","authors":"Aksh Chordia;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2022.3202150","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3202150","url":null,"abstract":"This work aims to analyze the variability of integrated circuits and systems. An automated framework is presented for variability analysis that exploits the metaheuristic optimization techniques. The efficacy of the proposed approach is demonstrated by two case studies—one is the estimation of variability in phase noise in RF CMOS LC tank oscillators (frequency domain analysis) and the other is the estimation of variability in the differential output signal of a current mode driver (time-domain analysis). The proposed approach is investigated and validated by comparing the results from the traditional Monte Carlo simulations and the ordinary least-squares-based polynomial chaos expansion. A significant gain in the computational time is reported while maintaining accuracy in the results. The proposed methodology is not just limited to variability analysis applications but also can be used to solve the circuit optimization problems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"104-111"},"PeriodicalIF":0.0,"publicationDate":"2022-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-17DOI: 10.1109/TSIPI.2022.3199331
Francesco de Paulis;Muhammet Hilmi Nisanci
The use of metallic pins covering the lid of a metallic cavity has been shown to effectively suppress the coupling mechanisms based on the cavity resonances. However, no clear evidence is available on the effectiveness of this solution for the signal transmission over microstrip interconnects routed on substrates inside the cavity. A comprehensive analysis is carried out to fill this gap by analyzing the signal propagation on single-ended and differential microstrip, thus demonstrating that the pins help to minimize the detrimental impact of the resonating cavity within the bandgap limits. The effectiveness of the pinned cavity to suppress the coupling among microstrips routed on the same substrate is demonstrated. Experimental data based on a pinned cavity with different pin lengths are provided to confirm that the intended bandgap is properly achieved and that the quality of the transmitting signal is ensured within the bandgap.
{"title":"Signal Integrity Assessment of Interconnects Routed Within Bandgap Metallic Cavities","authors":"Francesco de Paulis;Muhammet Hilmi Nisanci","doi":"10.1109/TSIPI.2022.3199331","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3199331","url":null,"abstract":"The use of metallic pins covering the lid of a metallic cavity has been shown to effectively suppress the coupling mechanisms based on the cavity resonances. However, no clear evidence is available on the effectiveness of this solution for the signal transmission over microstrip interconnects routed on substrates inside the cavity. A comprehensive analysis is carried out to fill this gap by analyzing the signal propagation on single-ended and differential microstrip, thus demonstrating that the pins help to minimize the detrimental impact of the resonating cavity within the bandgap limits. The effectiveness of the pinned cavity to suppress the coupling among microstrips routed on the same substrate is demonstrated. Experimental data based on a pinned cavity with different pin lengths are provided to confirm that the intended bandgap is properly achieved and that the quality of the transmitting signal is ensured within the bandgap.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"83-92"},"PeriodicalIF":0.0,"publicationDate":"2022-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/iel7/9745882/9770004/09858329.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-17DOI: 10.1109/TSIPI.2022.3199178
Herbert Hackl;David J. Pommerenke;Martin Ibel;Bernhard Auinger
Batteries are a fundamental part of many modern electric systems. As a result, battery modeling is increasingly important for the prediction of signal and power integrity (SIPI) as well as electromagnetic compatibility (EMC). Conventional battery module modeling requires knowledge of the integrated cells first, which is usually obtained by measurement on single cells. However, if individual cells are not accessible, the single cell's impedance needs to be extracted from measurement of the complete module. This work describes two solutions to this problem, which are both based on 3D electromagnetic (EM) simulation of the battery module with surrogate cell models to obtain S-parameters, which describe coupling effects inherent to the modules' geometry. By either fitting of the simulated module impedance to the measured data on circuit schematic level, or by numerical multiport de-embedding, the single cell impedance is extracted. Considered frequencies range from 9 kHz to 1 GHz.
{"title":"Extraction of Single Cell Impedance From Battery Module Measurement by Simulation-Based De-Embedding","authors":"Herbert Hackl;David J. Pommerenke;Martin Ibel;Bernhard Auinger","doi":"10.1109/TSIPI.2022.3199178","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3199178","url":null,"abstract":"Batteries are a fundamental part of many modern electric systems. As a result, battery modeling is increasingly important for the prediction of signal and power integrity (SIPI) as well as electromagnetic compatibility (EMC). Conventional battery module modeling requires knowledge of the integrated cells first, which is usually obtained by measurement on single cells. However, if individual cells are not accessible, the single cell's impedance needs to be extracted from measurement of the complete module. This work describes two solutions to this problem, which are both based on 3D electromagnetic (EM) simulation of the battery module with surrogate cell models to obtain S-parameters, which describe coupling effects inherent to the modules' geometry. By either fitting of the simulated module impedance to the measured data on circuit schematic level, or by numerical multiport de-embedding, the single cell impedance is extracted. Considered frequencies range from 9 kHz to 1 GHz.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"112-120"},"PeriodicalIF":0.0,"publicationDate":"2022-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-08-08DOI: 10.1109/TSIPI.2022.3197110
Ihsan Erdin;Ramachandra Achar
A domain decomposition method is proposed to evaluate the effectiveness of decoupling capacitors in practical power delivery networks (PDNs). The proposed method is based on the separation of a PDN into its local and nonlocal domains. The local domain is constituted by circuit components with the highest impact on the impedance of a specified power pin on a planar PDN. The rest of the PDN makes up the nonlocal domain, which could be of any planar shape. The nonlocal domain is characterized as a distributed circuit, preferably using a numerical electromagnetic (EM) simulator. The self-impedance of the pin depends on the placement configuration of capacitors in its surroundings. Using the pin impedance as a figure of merit, the optimal placement configuration is then sought in the local domain. The impact of the stationary domain is included in calculations as an indefinite impedance and the optimal placement configuration of capacitors is computed using an iterative approach. The proposed method avoids the use of a computationally intensive EM simulation at each iteration step, which significantly speeds up the analysis process.
{"title":"A Domain Decomposition Approach for Assessment of Decoupling Capacitors in Practical PDNs","authors":"Ihsan Erdin;Ramachandra Achar","doi":"10.1109/TSIPI.2022.3197110","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3197110","url":null,"abstract":"A domain decomposition method is proposed to evaluate the effectiveness of decoupling capacitors in practical power delivery networks (PDNs). The proposed method is based on the separation of a PDN into its local and nonlocal domains. The local domain is constituted by circuit components with the highest impact on the impedance of a specified power pin on a planar PDN. The rest of the PDN makes up the nonlocal domain, which could be of any planar shape. The nonlocal domain is characterized as a distributed circuit, preferably using a numerical electromagnetic (EM) simulator. The self-impedance of the pin depends on the placement configuration of capacitors in its surroundings. Using the pin impedance as a figure of merit, the optimal placement configuration is then sought in the local domain. The impact of the stationary domain is included in calculations as an indefinite impedance and the optimal placement configuration of capacitors is computed using an iterative approach. The proposed method avoids the use of a computationally intensive EM simulation at each iteration step, which significantly speeds up the analysis process.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"55-64"},"PeriodicalIF":0.0,"publicationDate":"2022-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-07-27DOI: 10.1109/TSIPI.2022.3193871
Nobuo Kuwabara;Tohlu Matsushima;Yuki Fukumoto
Radiated emission from a differential-mode (DM) signal was calculated by using a chain parameter matrix for a shielded twisted pair (STP) cable. The series connection of the matrix represented the multiconductor transmission line inside the shield, and the common-mode current generated from the DM signal was obtained by solving the matrix equation. The matrix elements of the STP cable and the shield's transfer impedance were determined through both measurement and calculation, and these values were used to calculate the current outside the shield and the radiated electric field strength. The maximum current outside the shield and the maximum radiated electric field strength were then measured in the frequency range from 30 to 300 MHz, and these results were compared with the calculated values. The calculation results for the maximum current intensity agreed well with the measured values, and those for the maximum radiated electric field strength agreed fairly well with the measured values.
{"title":"Analysis of Differential-Mode Signal Emission From STP Cable by Using Chain Parameter Matrix","authors":"Nobuo Kuwabara;Tohlu Matsushima;Yuki Fukumoto","doi":"10.1109/TSIPI.2022.3193871","DOIUrl":"https://doi.org/10.1109/TSIPI.2022.3193871","url":null,"abstract":"Radiated emission from a differential-mode (DM) signal was calculated by using a chain parameter matrix for a shielded twisted pair (STP) cable. The series connection of the matrix represented the multiconductor transmission line inside the shield, and the common-mode current generated from the DM signal was obtained by solving the matrix equation. The matrix elements of the STP cable and the shield's transfer impedance were determined through both measurement and calculation, and these values were used to calculate the current outside the shield and the radiated electric field strength. The maximum current outside the shield and the maximum radiated electric field strength were then measured in the frequency range from 30 to 300 MHz, and these results were compared with the calculated values. The calculation results for the maximum current intensity agreed well with the measured values, and those for the maximum radiated electric field strength agreed fairly well with the measured values.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"1 ","pages":"74-82"},"PeriodicalIF":0.0,"publicationDate":"2022-07-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67842427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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