Pub Date : 2025-03-07DOI: 10.1109/TSIPI.2025.3548965
Ang Li;Pengyu Liu;Zizheng Dong;Jinhao Li;Jianfei Jiang;Weijia Zhu;Naifeng Jing;Qin Wang
With the escalating computing power demands in artificial intelligence-generated content and other applications, the three-dimensional (3-D) stacking technology has effectively broken through the bottleneck of Moore's law and become the primary choice for high-performance chip packaging technology. Especially in the logic-on-memory (LoM) scenario with strong industrial feasibility, the 3-D stacking process fully leverages its advantages of extremely high interconnection density and low communication delay, making it well-suited for addressing the bandwidth expansion challenges under the “memory wall” bottleneck. Nevertheless, the heightened integration level and reduced power consumption requirements of the LoM architecture have introduced significant challenges to the power supply of stacking chips. Current EDA tools lack the capability to rapidly and effectively explore the optimal design of LoM power distribution networks (PDNs), and existing SPICE-type 3-D PDN analysis models often encounter challenges with oversimplified modeling approach and idealized power analysis, rendering them unsuitable for LoM structures, such as near-memory computing and high-bandwidth processors in computing/memory stacking scenarios. In this work, we propose for the first time a fine-grained 3-D PDN analysis modeling approach designed for LoM stacking architecture. Our modeling method comprehensively accounts for the power supply characteristics within the stacking architectures, and implements fine-grained segmentation and modeling of the full-chip PDN based on the estimated area, power consumption, and backend-of-line dimensions, allowing for rapid and accurate evaluation of power integrity (PI) across different PDN design schemes before the physical design stage. Furthermore, we explore the optimal 3-D LoM PDN design across various physical design spaces, including multilayer PDN connection schemes, metal layer configuration, and through-silicon via placement density. The final analysis result is applied to guide the practical physical design of the LoM PDN, highlighting the significance of our modeling approach in 3-D chip PI analysis and 3-D PDN design optimization.
{"title":"Fine-Grained Modeling and Evaluation of 3-D Power Distribution Networks in Logic-on-Memory Stacking Architecture","authors":"Ang Li;Pengyu Liu;Zizheng Dong;Jinhao Li;Jianfei Jiang;Weijia Zhu;Naifeng Jing;Qin Wang","doi":"10.1109/TSIPI.2025.3548965","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3548965","url":null,"abstract":"With the escalating computing power demands in artificial intelligence-generated content and other applications, the three-dimensional (3-D) stacking technology has effectively broken through the bottleneck of Moore's law and become the primary choice for high-performance chip packaging technology. Especially in the logic-on-memory (LoM) scenario with strong industrial feasibility, the 3-D stacking process fully leverages its advantages of extremely high interconnection density and low communication delay, making it well-suited for addressing the bandwidth expansion challenges under the “memory wall” bottleneck. Nevertheless, the heightened integration level and reduced power consumption requirements of the LoM architecture have introduced significant challenges to the power supply of stacking chips. Current EDA tools lack the capability to rapidly and effectively explore the optimal design of LoM power distribution networks (PDNs), and existing SPICE-type 3-D PDN analysis models often encounter challenges with oversimplified modeling approach and idealized power analysis, rendering them unsuitable for LoM structures, such as near-memory computing and high-bandwidth processors in computing/memory stacking scenarios. In this work, we propose for the first time a fine-grained 3-D PDN analysis modeling approach designed for LoM stacking architecture. Our modeling method comprehensively accounts for the power supply characteristics within the stacking architectures, and implements fine-grained segmentation and modeling of the full-chip PDN based on the estimated area, power consumption, and backend-of-line dimensions, allowing for rapid and accurate evaluation of power integrity (PI) across different PDN design schemes before the physical design stage. Furthermore, we explore the optimal 3-D LoM PDN design across various physical design spaces, including multilayer PDN connection schemes, metal layer configuration, and through-silicon via placement density. The final analysis result is applied to guide the practical physical design of the LoM PDN, highlighting the significance of our modeling approach in 3-D chip PI analysis and 3-D PDN design optimization.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"65-80"},"PeriodicalIF":0.0,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-25DOI: 10.1109/TSIPI.2025.3545383
Anuj Kumar;Jai Narayan Tripathi
This work presents an analytical model for an eye diagram to estimate jitter. The contribution is embodied in the development of a specialised analytical model to accurately estimate jitter caused by ground-bounce noise in complementary metal-oxide-semiconductor inverter circuits. This work is highly relevant in the area of high-speed very large-scale integrated circuit design as it provides significant theoretical contributions for the estimation of jitter and assessment of signal quality using eye diagrams. The input–output relationship has been utilized to derive rising transition edges. Building upon this derivation, analytical equations have been developed to predict jitter for output transitions considering falling ramp inputs in the inverter. The eye diagram model is illustrated after integrating the rising transition edges concurrent with the falling transition edges. The robust analytical framework yields consistent results, aligning closely with simulated predictions and the physical measurements using HEX inverter ICs provide validation to the proposed modeling. The comprehensive study affirms notable accuracy in the comparison of analytical, simulated, and experimental findings.
{"title":"Analytical Modeling of Eye Diagram for Jitter Estimation in Presence of Ground Bounce","authors":"Anuj Kumar;Jai Narayan Tripathi","doi":"10.1109/TSIPI.2025.3545383","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3545383","url":null,"abstract":"This work presents an analytical model for an eye diagram to estimate jitter. The contribution is embodied in the development of a specialised analytical model to accurately estimate jitter caused by ground-bounce noise in complementary metal-oxide-semiconductor inverter circuits. This work is highly relevant in the area of high-speed very large-scale integrated circuit design as it provides significant theoretical contributions for the estimation of jitter and assessment of signal quality using eye diagrams. The input–output relationship has been utilized to derive rising transition edges. Building upon this derivation, analytical equations have been developed to predict jitter for output transitions considering falling ramp inputs in the inverter. The eye diagram model is illustrated after integrating the rising transition edges concurrent with the falling transition edges. The robust analytical framework yields consistent results, aligning closely with simulated predictions and the physical measurements using HEX inverter ICs provide validation to the proposed modeling. The comprehensive study affirms notable accuracy in the comparison of analytical, simulated, and experimental findings.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"24-32"},"PeriodicalIF":0.0,"publicationDate":"2025-02-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143667626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-27DOI: 10.1109/TSIPI.2025.3533060
{"title":"IEEE Electromagnetic Compatibility Society Information","authors":"","doi":"10.1109/TSIPI.2025.3533060","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3533060","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854552","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-27DOI: 10.1109/TSIPI.2025.3534910
{"title":"2024 Index IEEE Transactions on Signal and Power Integrity Vol. 3","authors":"","doi":"10.1109/TSIPI.2025.3534910","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3534910","url":null,"abstract":"","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2025-01-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10854991","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1109/TSIPI.2025.3531840
Junyong Park;Yuandong Guo;Hongseok Kim;Jun Fan;DongHyun Kim
An accurate and broadband modeling methodology for a typical permanent magnet synchronous motor (PMSM) in a vehicular three-phase braking system is proposed for the first time to improve the accuracy of induced electromagnetic interference (EMI) in three-phase motor systems. The proposed model is verified by measurement from dc to 120 MHz both in common- and differential-mode current measurement of the three-phase motor under study. The proposed model can be used in analysis and prediction of the electromagnetic noise of the motor-drive braking system. The model can also be incorporated into frequency- and time-domain simulations. The modeling approach is based on the vector fitting technique of measured three-phase motor impedance and S-parameter, where the three-phase PMSM is modeled as a multiport device. In addition, the proposed modeling method for the PMSM can be used for different types of three-phase motors for EMI simulations and analysis.
{"title":"Accurate and Broadband Three-Phase Motor Modeling Methodology Based on Vector Fitting","authors":"Junyong Park;Yuandong Guo;Hongseok Kim;Jun Fan;DongHyun Kim","doi":"10.1109/TSIPI.2025.3531840","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3531840","url":null,"abstract":"An accurate and broadband modeling methodology for a typical permanent magnet synchronous motor (PMSM) in a vehicular three-phase braking system is proposed for the first time to improve the accuracy of induced electromagnetic interference (EMI) in three-phase motor systems. The proposed model is verified by measurement from dc to 120 MHz both in common- and differential-mode current measurement of the three-phase motor under study. The proposed model can be used in analysis and prediction of the electromagnetic noise of the motor-drive braking system. The model can also be incorporated into frequency- and time-domain simulations. The modeling approach is based on the vector fitting technique of measured three-phase motor impedance and <italic>S</i>-parameter, where the three-phase PMSM is modeled as a multiport device. In addition, the proposed modeling method for the PMSM can be used for different types of three-phase motors for EMI simulations and analysis.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"81-87"},"PeriodicalIF":0.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143792935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TSIPI.2025.3527436
Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai
The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, Z-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.
{"title":"System-Level Application of the Z-Directed Component (ZDC) for Power Integrity","authors":"Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai","doi":"10.1109/TSIPI.2025.3527436","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3527436","url":null,"abstract":"The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, <italic>Z</i>-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"10-18"},"PeriodicalIF":0.0,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-08DOI: 10.1109/TSIPI.2025.3527437
Yifan Ding;Jianmin Zhang;Ming-Feng Xue;Xin Hua;Benjamin Leung;Eric A. MacIntosh;Chulsoon Hwang
In this article, a multiphysics modeling methodology is presented for predicting the acoustic noise induced by a multilayer ceramic capacitor (MLCC) in mobile electronic devices. The modeling process involves using a prescribed methodology to extract the equivalent source at the resonance frequencies of a printed circuit board (PCB) and then deriving the broadband source multiphysics electrical input mechanical output (EIMO) model. Subsequently, the obtained EIMO model is integrated into PCB vibration simulations, and the resulting vibration data are used for acoustic simulations. The predicted A-weighted sound pressure level excited by the MLCC EIMO model accurately represented the acoustic noise generated by a tested MLCC, achieving a correlation with measurements of 2 dB difference at resonant modes. This approach offers insights into mitigating MLCC-induced acoustic noise in electronic systems and facilitates more effective design strategies.
{"title":"Multilayer Ceramic Capacitor Source Model Application in Acoustic Noise Prediction","authors":"Yifan Ding;Jianmin Zhang;Ming-Feng Xue;Xin Hua;Benjamin Leung;Eric A. MacIntosh;Chulsoon Hwang","doi":"10.1109/TSIPI.2025.3527437","DOIUrl":"https://doi.org/10.1109/TSIPI.2025.3527437","url":null,"abstract":"In this article, a multiphysics modeling methodology is presented for predicting the acoustic noise induced by a multilayer ceramic capacitor (MLCC) in mobile electronic devices. The modeling process involves using a prescribed methodology to extract the equivalent source at the resonance frequencies of a printed circuit board (PCB) and then deriving the broadband source multiphysics electrical input mechanical output (EIMO) model. Subsequently, the obtained EIMO model is integrated into PCB vibration simulations, and the resulting vibration data are used for acoustic simulations. The predicted A-weighted sound pressure level excited by the MLCC EIMO model accurately represented the acoustic noise generated by a tested MLCC, achieving a correlation with measurements of 2 dB difference at resonant modes. This approach offers insights into mitigating MLCC-induced acoustic noise in electronic systems and facilitates more effective design strategies.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"4 ","pages":"19-23"},"PeriodicalIF":0.0,"publicationDate":"2025-01-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143106789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-23DOI: 10.1109/TSIPI.2024.3507712
Kai Li;Chiu-Chih Chou;Wei-Da Kuo;Hao-Hsiang Chuang;Hsin-Chan Hsieh;Ruey-Beei Wu
Double data rate (DDR) memory interface is used in an increasing number of electronic products to increase the efficiency of memory access. Factors such as signal propagation delay, reflection, and crosstalk need to be considered for signal integrity design. This study derives the transfer function of a single transmission line under mismatched boundary conditions and extends it to multiple coupled transmission lines. By utilizing inverse Fourier transform, the pulse responses are obtained and, based on peak distortion analysis, the worst-case eye height and eye width are quickly extracted, saving time in the simulation and achieving high accuracy for the design of high-speed DDR memory interface.
{"title":"Analytic Method of Fast Eye-Diagram Index for Multiple Coupled Lines in DDR","authors":"Kai Li;Chiu-Chih Chou;Wei-Da Kuo;Hao-Hsiang Chuang;Hsin-Chan Hsieh;Ruey-Beei Wu","doi":"10.1109/TSIPI.2024.3507712","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3507712","url":null,"abstract":"Double data rate (DDR) memory interface is used in an increasing number of electronic products to increase the efficiency of memory access. Factors such as signal propagation delay, reflection, and crosstalk need to be considered for signal integrity design. This study derives the transfer function of a single transmission line under mismatched boundary conditions and extends it to multiple coupled transmission lines. By utilizing inverse Fourier transform, the pulse responses are obtained and, based on peak distortion analysis, the worst-case eye height and eye width are quickly extracted, saving time in the simulation and achieving high accuracy for the design of high-speed DDR memory interface.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"226-234"},"PeriodicalIF":0.0,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142875128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this article, a novel planar balanced full-passband linear-phase dual-port absorptive filter is presented for the application of signal integrity in balanced systems. To absorb out-of-band reflected wave energy to prevent it from damaging the performance of neighboring active nonlinear circuits, the reflectionless characteristic of the dual-port absorptive filter is realized by loading absorptive networks at both the input and output ports. Negative group delay (NGD) equalized circuits are employed to compensate for salient group delay on both the edges of the passband achieving full-passband linear-phase characteristics. In order to solve the impedance mismatch problem caused by absorption networks and NGD equalized circuits, a quarter-wavelength impedance transformer is introduced to provide good matching characteristics. To verify the design concept, a conventional two-order balanced filter is improved into a full-passband linear-phase dual-port absorptive prototype, which is manufactured and measured with a center frequency of 2.45 GHz.
{"title":"Planar Balanced Full-Passband Linear-Phase Dual-Port Absorptive Filter Based on Negative Group Delay Equalized Compensation","authors":"Shipeng Zhao;Zhongbao Wang;Hongmei Liu;Shaojun Fang","doi":"10.1109/TSIPI.2024.3511497","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3511497","url":null,"abstract":"In this article, a novel planar balanced full-passband linear-phase dual-port absorptive filter is presented for the application of signal integrity in balanced systems. To absorb out-of-band reflected wave energy to prevent it from damaging the performance of neighboring active nonlinear circuits, the reflectionless characteristic of the dual-port absorptive filter is realized by loading absorptive networks at both the input and output ports. Negative group delay (NGD) equalized circuits are employed to compensate for salient group delay on both the edges of the passband achieving full-passband linear-phase characteristics. In order to solve the impedance mismatch problem caused by absorption networks and NGD equalized circuits, a quarter-wavelength impedance transformer is introduced to provide good matching characteristics. To verify the design concept, a conventional two-order balanced filter is improved into a full-passband linear-phase dual-port absorptive prototype, which is manufactured and measured with a center frequency of 2.45 GHz.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"219-225"},"PeriodicalIF":0.0,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-02DOI: 10.1109/TSIPI.2024.3509800
Yingcong Zhang;Guoan Wang
This article proposes a novel structure of coupled line with embedded metasurface aimed at mitigating far-end crosstalk (FEXT) in high-speed data transmission. The square loop metasurface structure is implemented under the coupled line to increase the mutual capacitance between signal traces, thereby mitigating FEXT in the coupled line. The capacitance and the inductance matrices of both conventional coupled line and the proposed metasurface-embedded structure are extracted with numerical equations from the simulations and applied to the equivalent circuit model to comprehensively analyze and accurately evaluate the proposed structure. To validate the design efficacy of the proposed concept, prototypes of conventional and the proposed coupled line structure are implemented on a FR-4 printed circuit board, and their performance in both frequency domain and time domain are measured and compared. Compared to conventional coupled line, experimental results demonstrate that the proposed metasurface embedded coupled line structure significantly enhances the FEXT performance while ensuring robust high-speed signal propagation along the signal traces. Specifically, FEXT is reduced by 8.2 dB within the frequency range of 1–12 GHz, and with the largest improvement of 42.84 dB at 10.9 GHz. This superior FEXT performance coupled with ultra-low latency underscores the significant potential of the proposed metasurface embedded coupled line structure for application in miniaturized high-speed systems.
{"title":"High Signal Integrity Interconnects Embedded With Metasurface for Far-End Crosstalk Reduction and High-Speed Data Transfer","authors":"Yingcong Zhang;Guoan Wang","doi":"10.1109/TSIPI.2024.3509800","DOIUrl":"https://doi.org/10.1109/TSIPI.2024.3509800","url":null,"abstract":"This article proposes a novel structure of coupled line with embedded metasurface aimed at mitigating far-end crosstalk (FEXT) in high-speed data transmission. The square loop metasurface structure is implemented under the coupled line to increase the mutual capacitance between signal traces, thereby mitigating FEXT in the coupled line. The capacitance and the inductance matrices of both conventional coupled line and the proposed metasurface-embedded structure are extracted with numerical equations from the simulations and applied to the equivalent circuit model to comprehensively analyze and accurately evaluate the proposed structure. To validate the design efficacy of the proposed concept, prototypes of conventional and the proposed coupled line structure are implemented on a FR-4 printed circuit board, and their performance in both frequency domain and time domain are measured and compared. Compared to conventional coupled line, experimental results demonstrate that the proposed metasurface embedded coupled line structure significantly enhances the FEXT performance while ensuring robust high-speed signal propagation along the signal traces. Specifically, FEXT is reduced by 8.2 dB within the frequency range of 1–12 GHz, and with the largest improvement of 42.84 dB at 10.9 GHz. This superior FEXT performance coupled with ultra-low latency underscores the significant potential of the proposed metasurface embedded coupled line structure for application in miniaturized high-speed systems.","PeriodicalId":100646,"journal":{"name":"IEEE Transactions on Signal and Power Integrity","volume":"3 ","pages":"212-218"},"PeriodicalIF":0.0,"publicationDate":"2024-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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