Memories - Materials, Devices, Circuits and Systems最新文献

This study pioneers the tailored application of Convolutional Neural Networks (CNNs) for addressing the challenge of unbalanced data in software engineering, a relatively unexplored domain for CNN utilization. Unlike conventional methods, our framework demonstrates a significant precision uplift of up to 15% in software classification tasks, specifically enhancing minority class sample accuracy. This research not only delineates a novel CNN-based approach that outperforms traditional data balancing techniques but also underscores the strategic integration of AI to bolster software engineering processes. By pinpointing the ethical implications, our findings advocate for a conscientious adoption of AI, ensuring software development advances equitably and efficiently.

In the recent HBM2E IO design, clock is transmitted differentially to the external DRAM and duty cycle distortion (DCD) could add to the differential clock due to traversing multiple stages in DRAM. At higher data rates, the DCD from the differential clock imposes restrictions on the timing margins. In the current work, Tx clock path is added with DCC feature to compensate for any DCD errors introduced by the clock network in the external DRAM. Linearity of the DCC is critical metric when the clock is differential and running at high speed. A new programmable delay line with inherent DCC design with good linearity is presented in this paper.

Here a novel ultra-thin meta-material structure is proposed, including periodic arrays of graphene rings, disks, and ribbons and SiO₂ dielectric as spacer between graphene patterns layers at the terahertz (THz) range. The introduced device can couple electromagnetic waves by considering reflection and transmission channels as outputs. Electromagnetic wave coupling depends on the parameters design and the device thickness. The proposed structure can couple electromagnetic waves in multi-band and close frequencies including 2 THz, 4 THz, 6 THz, 7.5 THz, and 9.5 THz. By considering the impedance matching concept, an equivalent circuit model (ECM) is developed for the proposed meta-material. Also, the device stability is investigated in various physical coefficients, geometrical parameters, and incident wave angles to ensure optical applications such as sensors, indoor communications, security, and medical imaging.

Recent experimental studies have shown lanthanum-doped hafnium oxide (La:HfO₂) possessing ferroelectric properties. This material is of special interest since it is based on lead-free, simple binary oxide of HfO₂, and has excellent endurance property (1 × 10⁹ field cycles without fatigue. There exists substantial information about the material aspects of La:HfO₂ but it lacks proven application potential for CMOS-compatible low-power memory design. In this work, 10 % La metal cation fraction of HfO₂ (La:HfO₂) is proposed as the gate stack material in tunnel FET (TFET) for its potential as a memory device. 2D device simulations are carried out to show that the proposed ferroelectric TFET (FeTFET) provides the largest memory window (MW) as compared to present perovskite ferroelectric materials such as PZT, SBT (SrBi₂Ta₂O₉) and silicon doped (4.6 % Si in HfO₂) hafnium oxide (Si:HfO₂). The larger window is attributed to greater polarization, and the calculation of MW is quantified by the shift in threshold voltage (V_th). The simulations carried out in this work suggest that La:HfO₂ can be adopted as a potential ferroelectric material to target low-power FeTFET design at significantly reduced ferroelectric layer thickness.

In this paper, firstly, reports on use of various nature originated polysaccharides as gate dielectric candidates for organic field effect transistors (OFETs) to achieve eco-friendliness and eventual biodegradability in devices, are summarized. To emphasize the same, the performance of flexible OFETs fabricated with cyanoethyl cellulose (CEC), a synthetically modified cellulose as gate dielectric is comprehensively investigated. A widely studied TIPS-pentacene: PS blend is used to form the active layer in these devices, showing a p-channel transistor operation at a low voltage of −5 V. Along with high performance, these devices exhibited excellent repeatability and shelf life up to 10 months in ambient conditions. Effect of repeatability, bias-stress, and bending stability were investigated to confirm the decent electrical and bending stability. The device can sustain the transistor performance even after application of 200 bending cycles. Moreover, the effect of annealing temperature on transistor performance was studied to observe their suitability in real applications. These findings suggest that polysaccharides can be suitable gate dielectric for eco-sustainable electronics.

Recently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significant interest because of its exceptional error correction capabilities. Over the last decades, there has been much research on BCH decoder design to meet the demand for reduced hardware complexities, minimized delay performance, and lower power dissipation to enable BCH decoders and their VLSI implementations to facilitate different code lengths and rates of code. This paper surveys the trends and challenges associated with BCH decoder in NAND flash memory devices, the possible solutions for overcoming of time and area overhead in architecture of BCH decoder block and an examination of the extent to which present architectures will respond to the escalating requirements on data transfer rate, bit error rate (BER) performance, power consumption, and silicon area that will be essential for the extensive acceptance of BCH code in applications that will emerge in the near future. To demonstrate the need for such solutions, we present rigorous experimental data on BCH error correction codes on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several area-delay efficient techniques, including three low-latency decoding strategies for implementing the BCH decoder: pipeline method, re-encoding scheme, and parallelization method, and various hardware optimization strategies for the BCH decoder, such as three area-efficient syndrome block architectures, four error locator polynomial detection algorithms, and four error position identification algorithms using the Chien search method. We investigate the increase in reliability that each of these methods brings. We also briefly address future directions that these methods and flash memory techniques could evolve into the future.

High-quality copper oxide (CuO) thin films were deposited on the silicon (Si) substrate at the room temperature using the physical vapour deposition (PVD) technique named radio frequency (RF) sputtering. The copper-oxide thin-films were single crystalline and of uniform thickness. Subsequently, the influence of growth pressure (low gas pressure - 3 mTorr and high gas pressure - 100 mTorr) and post growth annealing at different temperatures (300 °C to 700 °C) were investigated to understand the microstructural and morphological changes of the thin film. With the influence of growth pressure and post thermal annealing temperature, significant changes in crystallinity, surface roughness, and surface oxidation rate of the CuO thin film were detected, which were adequately analyzed via several characterization techniques. X-ray diffraction (XRD) patterns revealed the phase formation with good crystallinity of the film, which is substantiated by Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) characterization. Atomic force microscopy (AFM) images disclosed that the surface roughness of the film and grain size. By gaining insights into the structural and surface properties of CuO/Si thin films, this research presents new prospects for tuning of CuO phases, structures, and compositions for multifunctional applications.

To enhance the efficiency of exposure in greenhouses during specific cultivation periods, it is essential to design a meta-face that effectively filters the green part of visible light. This targeted filtering function will enable optimal control of the light spectrum, resulting in better cultivation conditions and increased productivity. Leveraging innovative concepts and advanced methods, a highly efficient meta-surface design aimed at filtering the green portion of the visible light spectrum is proposed. The proposed structure comprises periodic arrays of graphene disks and rings strategically positioned on both sides of a silicon oxide substrate. This straightforward coated layer configuration offers a practical solution for greenhouses and controlled agriculture applications, facilitating improved light management and tailored growth conditions. Through two separate simulation paths, the validity and accuracy of our proposed approach were investigated. Both theoretical analysis and simulation results demonstrate that the proposed structure attenuates the green part of visible light. Filtered output waves prove to be highly beneficial for indoor cultivation, during the flowering period, offering improved control over light conditions. The design methodology relies on an equivalent circuit model and impedance matching criteria. Additionally, full-wave simulation is performed to verify the effectiveness of the employed modeling. According to the simulation results, the proposed meta-surface effectively filters the green part of visible light, while allowing the transmission of the red spectrum.

This article reports an improvement in the low-frequency noise characteristics in hafnium oxide-based (${\mathrm{HfO}}_2$) field-effect transistors by different precursor materials at ALD process. The Hafniumoxide on the devices were fabricated once with organic precursor materials and once with chloridic precursor materials. The investigation shows an improvement in the noise behavior when using chloridic precursor materials. Regarding the main noise source, which are divided into fluctuation of the number of carriers ($\Delta N$) and fluctuation of the effective transistor mobility ($\Delta \mu$), the results show that the devices fabricated with organic precursor materials show typical behavior of $\Delta N$ noise, where the devices fabricated with chloridic precursor materials show typical behavior of $\Delta \mu$ noise.

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.