Memories - Materials, Devices, Circuits and Systems最新文献

Recently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significant interest because of its exceptional error correction capabilities. Over the last decades, there has been much research on BCH decoder design to meet the demand for reduced hardware complexities, minimized delay performance, and lower power dissipation to enable BCH decoders and their VLSI implementations to facilitate different code lengths and rates of code. This paper surveys the trends and challenges associated with BCH decoder in NAND flash memory devices, the possible solutions for overcoming of time and area overhead in architecture of BCH decoder block and an examination of the extent to which present architectures will respond to the escalating requirements on data transfer rate, bit error rate (BER) performance, power consumption, and silicon area that will be essential for the extensive acceptance of BCH code in applications that will emerge in the near future. To demonstrate the need for such solutions, we present rigorous experimental data on BCH error correction codes on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several area-delay efficient techniques, including three low-latency decoding strategies for implementing the BCH decoder: pipeline method, re-encoding scheme, and parallelization method, and various hardware optimization strategies for the BCH decoder, such as three area-efficient syndrome block architectures, four error locator polynomial detection algorithms, and four error position identification algorithms using the Chien search method. We investigate the increase in reliability that each of these methods brings. We also briefly address future directions that these methods and flash memory techniques could evolve into the future.

High-quality copper oxide (CuO) thin films were deposited on the silicon (Si) substrate at the room temperature using the physical vapour deposition (PVD) technique named radio frequency (RF) sputtering. The copper-oxide thin-films were single crystalline and of uniform thickness. Subsequently, the influence of growth pressure (low gas pressure - 3 mTorr and high gas pressure - 100 mTorr) and post growth annealing at different temperatures (300 °C to 700 °C) were investigated to understand the microstructural and morphological changes of the thin film. With the influence of growth pressure and post thermal annealing temperature, significant changes in crystallinity, surface roughness, and surface oxidation rate of the CuO thin film were detected, which were adequately analyzed via several characterization techniques. X-ray diffraction (XRD) patterns revealed the phase formation with good crystallinity of the film, which is substantiated by Raman spectroscopy and X-ray photoelectron spectroscopy (XPS) characterization. Atomic force microscopy (AFM) images disclosed that the surface roughness of the film and grain size. By gaining insights into the structural and surface properties of CuO/Si thin films, this research presents new prospects for tuning of CuO phases, structures, and compositions for multifunctional applications.

To enhance the efficiency of exposure in greenhouses during specific cultivation periods, it is essential to design a meta-face that effectively filters the green part of visible light. This targeted filtering function will enable optimal control of the light spectrum, resulting in better cultivation conditions and increased productivity. Leveraging innovative concepts and advanced methods, a highly efficient meta-surface design aimed at filtering the green portion of the visible light spectrum is proposed. The proposed structure comprises periodic arrays of graphene disks and rings strategically positioned on both sides of a silicon oxide substrate. This straightforward coated layer configuration offers a practical solution for greenhouses and controlled agriculture applications, facilitating improved light management and tailored growth conditions. Through two separate simulation paths, the validity and accuracy of our proposed approach were investigated. Both theoretical analysis and simulation results demonstrate that the proposed structure attenuates the green part of visible light. Filtered output waves prove to be highly beneficial for indoor cultivation, during the flowering period, offering improved control over light conditions. The design methodology relies on an equivalent circuit model and impedance matching criteria. Additionally, full-wave simulation is performed to verify the effectiveness of the employed modeling. According to the simulation results, the proposed meta-surface effectively filters the green part of visible light, while allowing the transmission of the red spectrum.

This article reports an improvement in the low-frequency noise characteristics in hafnium oxide-based (${\mathrm{HfO}}_2$) field-effect transistors by different precursor materials at ALD process. The Hafniumoxide on the devices were fabricated once with organic precursor materials and once with chloridic precursor materials. The investigation shows an improvement in the noise behavior when using chloridic precursor materials. Regarding the main noise source, which are divided into fluctuation of the number of carriers ($\Delta N$) and fluctuation of the effective transistor mobility ($\Delta \mu$), the results show that the devices fabricated with organic precursor materials show typical behavior of $\Delta N$ noise, where the devices fabricated with chloridic precursor materials show typical behavior of $\Delta \mu$ noise.

Using a control variable, the functionality of Polymorphic circuits can be modified, making them adaptable and useful for reconfiguring circuit behavior — all the way from gate level to system level. State-of-the art polymorphic circuits are based on custom non-linear circuit design or emerging devices such as ambipolar FET, configurable magnetic devices etc. While some of these approaches are inefficient in performance, others involve exotic devices. The Crosstalk computing based polymorphic circuits offer a fresh perspective. In Crosstalk, the interconnect interference between nanoscale metal lines is intentionally engineered to exhibit the programmable Boolean logic behavior. This approach relies on the coupling between metal lines and not on the transistors for computing, resulting in better scalability, security by obscurity, and fault tolerance by reconfiguration. Our novel approach is backed by the mathematical formulation that conveys the rationale to generalize and achieve a wide variety of polymorphic circuits. Our experiments, including design, simulation, and Power Performance Area (PPA) characterization results indicate that crosstalk circuits provide significant improvement in transistor count (about 3x), switching energy (2x), and speed (1.5x) for polymorphic logic circuits. In the best-case scenario, the transistor count reduction is 5x. This paper presents Crosstalk computing’s fundamentals, polymorphism and the scalability aspects to compete/co-exist with CMOS for digital logic implementations below 10 nm. Our scalability study uses Open Source 7 nm PDK, considers all process variation aspects and accommodates worst-case scenarios. The study results for various benchmark circuits show that the Crosstalk technology is a viable alternative to CMOS for digital logic implementations below 10 nm, having 48% density, 57% power, and 10% performance gains over equivalent CMOS counterparts. Finally, we compare Crosstalk Polymorphic Circuit design technique with similar approaches described in related works and discuss its features and constraints.

This study investigates the influence of heavy ion irradiation on thin film transistors (TFTs) based on an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. Through the use of Technology Computer-Aided Design (TCAD) simulations, we analyze the impact on device performance. We examine the ambipolar device characteristics by varying the thickness of the active layer (Poly-Si) and studying the corresponding physics. Our results reveal that reducing the active layer thickness from 140 to 80 nm decreases the magnitude of the threshold voltage (|VT|) for both nMOS and pMOS operating voltages. Additionally, the subthreshold slope is reduced for both nMOS and pMOS as the active layer thickness is decreased from 140 to 80 nm.

Further, we investigated the transient response of the drain current to heavy ion irradiation in the sensitive regions across the Schottky barrier-based source and drain. We specifically analyze the phenomenon of bipolar amplification for various Linear Energy Transfer (LET) values, ranging from 0.1 MeV cm²/mg to 100 MeV cm²/mg. Our findings indicate that increasing the LET values from 0.1 MeV cm²/mg to 100 MeV cm²/mg results in amplified bipolar behavior and a drain current overshoot of over 10 % for both pMOS and nMOS operating voltages. To summarize, this work highlights the effects of heavy ion irradiation on TFTs with an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. The study explores the influence of active layer thickness on device characteristics and demonstrates the transient response of drain current under different LET values. These findings contribute to a better understanding of the behavior and performance of TFTs subjected to heavy ion irradiation.

Metal-air batteries (MABs) have emerged as a promising contender in the quest for alternative energy storage technologies, rivalling the widespread utilization of lithium-ion batteries (LIBs). Their comparable theoretical energy density to gasoline, reaching ∼12,000 Wh/kg, has sparked great interest. However, the practical implementation of MABs has been hindered by limitations associated with metal anodes, including volume expansion and unwanted side reactions. Surprisingly, the exploration of metalloid-air batteries (MLAB) remains largely unexplored. This comprehensive review aims to shed light on the potential of MLABs as a novel alternative battery technology. This technology employs metalloids in their elemental form or as compounds/alloys. Elemental metalloids, such as Silicon and Germanium, when used as anodes in combination with alkaline or Ionic liquid electrolytes, have showcased remarkable performance, surpassing their metallic counterparts in energy density, corrosiveness, and discharge time, among other critical factors. Moreover, this review delves into the discussion of Borides and Silicides, compounds of elemental Boron and Silicon, respectively, as anode materials for air batteries. Furthermore, diverse metalloid composites and computational studies exploring innovative configurations have also been examined and discussed, paving the way for future advancements in MLABs.

In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.

Various charged particles in space, including alpha particles, neutrons, heavy ions, and photons, pose reliability and stability concerns for memory circuits. These particles also create an ion track in the memory chip, disrupting the storage bit. The standard 6T SRAM is particularly susceptible to these disturbances. Several researchers suggest employing radiation-hardened SRAM cells to solve this problem. Most studies examine the inclusion of redundant nodes in the memory cell to recover the lost bit. This paper shows a new SEUH-12T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed SEUH-12T memory cell performance is compared to that of reliable radiation-hardened memory cells such as Quatro-10T, We-Quatro-12T, QCCS-12T, STS-10T, RHMC-12T, and RHWC-12T. The proposed SEUH-12T cell protects against single and multiple node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed SEUH-12T exhibits 8.5$\times$/ 6.3$\times$/ 5.6$\times$/ 1.4$\times$/ 1.2$\times$/ 1.4$\times$/ 1.04$\times$ times greater read stability than existing 6T-SRAM/ Quatro-10T/ We-Quatro-12T/ QCCS-12T/ STS-10T/ RHMC-12T/ RHWC-12T memory cells.

This article introduces a novel design of a simulator for grounded lossless negative inductance by using an active element -single Operational Trans Resistance Amplifier (OTRA) and four passive components. Without interrupting the condition of realization of inductance, the value of the simulated inductance can be independently administered by a MOS based resistor. For validation of the analytical elucidation PSPICE simulation results are used. Moreover, sensitivity analysis, Monte-Carlo simulation, temperature analysis, and % of total harmonic distortion (%THD) are also investigated to verify the functionality of the proposed circuit. As an application claim of the projected configuration, an inductance nullification circuit is also implemented that exposes that the proposed negative inductance simulator may be used to cancel or reduce the effective inductance in a circuit. The Analog Design Environment tool of Cadence Virtuoso is employed for designing the layout of the OTRA.