Memories - Materials, Devices, Circuits and Systems最新文献

All real physical processes, including of the first-passage time, occur with a change in entropy. This circumstance is not taken into account when studying the first-passage time, but is illustrated in this article using the example of electron transfer through a metallic double dot. The statistics of the first-passage time of a random process N(t) for electrons transferred through a metallic double dot is considered. The expressions for the average first-passage time are compared with and without taking into account the change in entropy during this time. External influences on the average value of the first-passage time are considered for the case of DC bias voltage.

The work presents a proof-of-concept methodology for at edge visual data storage and processing-in-memory (PIM) as visual data preprocessing inspired from the biological visual system pipeline. This work proposes a methodology to improve the contrast of low-light low-contrast image by carefully modulating the conductance of memristive kind oxide-based resistive memory (RRAM)device. We present the level of contrast enhancement using conductance modulation of different non-filamentary RRAMs with different material stacks and also analyze the impact of RRAM variability on the contrast enhancement. For intelligent vision tasks, we implement artificial neural network (ANN) to perform the image classification and shows the best-case improvement of $\sim$ 1500 epochs ($\sim$ 74%) using RRAM based PIM. We also implement a large sized ANN “Efficient-Det Network” to perform object recognition on low-light low-contrast dataset ”Ex-Dark” to evaluate the proposed method using PIM layer. The result shows 8% higher mAP than network without a PIM layer. The present work is a step towards the development of efficient hybrid visual system for intelligent vision tasks at edge.

This work investigates and reports on the fabrication of a ZnO nanosheets/p-Si heterojunction energy harvester. The proposed nanostructure device exhibits two key functionalities: energy harvesting and memristive characteristics. This allows the device to perform multiple tasks. The ZnO nanostructure sheet was grown using a hydrothermal method. To minimize defect states at the electrode-substrate interface, an optimal phosphorus doping process was employed to achieve minimal substrate sheet resistance. Under an applied pushing force of 0.259 kgf, the energy harvester generated an output voltage and current of 0.5548 V and 44 μA, respectively. The proposed structure produces an output of 24.41 μW at 13 Hz for 2000 cycles. Investigation of the device's transfer characteristics revealed memristive behavior with an on/off ratio of 10⁷. These findings suggest that the multifunctional ZnO nanosheets/p-Si electronic device reported here has promising potential for applications in the Internet of Things (IoT).

In this study, the development of diverse antenna designs using additive manufacturing processes, specifically spanning from L-band to K-band is proposed. All designs are implemented on a flexible FR4 substrate to make them suitable for wearable sensors and biomedical applications. The fabrication process involves the utilization of aerosol jet printing with nanoparticle silver ink, followed by curing in a vacuum chamber. Additionally, screen printing with copper paste is employed as another method, with subsequent curing in a laminator. The reflection coefficient (S11) and radiation patterns for the simulated design and fabricated samples were found to align closely. The achieved return loss consistently reaching −10 dB across fairly large operating frequency range underscores the efficacy of the proposed antennas and their associated additive manufacturing mechanisms. The design and simulation were performed using Ansys high frequency structural simulator (HFSS), and the parameters under test for the fabricated antennas were validated using a vector network analyzer (VNA) to assess overall performance.

This study deals with a passive RF duplexer integrated with a two-notch band. To design the model, a band-pass filter is considered. Using micro-strip technology, the RF duplexer substation is simulated. It is a rectangular in parallel coupling with frequency bands of 1 and 5 GHz while existing three ports. Moreover, to enhance the impedance coefficient and decrease the admittance, the method of complementary paired resonators is taken into account. Furthermore, scattering parameters were used by the step impedance method to make an integrated monolayer substrate from signal branching in duplex mode. Thus, the band-pass filter making the frequency cut-off bands allows designing GSM-4G radars. The low cut-off microwave band is included in these bands at the 77 MHz central frequency and the second cut-off band for GSM-4G radars at the 437 MHz central frequency. The duplexer has the total dimensions of 14 mm × 99 mm and the presented RF duplexer is simulated in CST.

Ferroelectric (FE) hafnium zirconium oxide (HZO) is an excellent candidate for data storage applications. However, it has some reliability limitations such as imprint and retention. Herein, we explore Al doping of HZO to overcome these limitations. FE behavior is tuned by the aluminum (Al) concentrations in the films and by annealing temperature. A correlation is done between electrical behavior, crystallographic texture, and FE phases determined by grazing-incidence X-ray diffraction (GIXRD) measurements. Reduced coercive field (2E${}_c$) values and wake-up free HZO-based ferroelectrics are explored. We show the tunability of remanent polarization (2P${}_r$) and 2E${}_c$ with respect to Al-doping concentration and anneal temperature, hence crystallographic texture.

Shrinking of the thickness of silicon on insulator (SOI) has been proposed as a potential solution for scaling down the physical base length of symmetric lateral electrostatically doped bipolar transistors. An ultra-thin body device that utilizes the full SOI thickness has been presented and the performance of the same is investigated in detail. The device features two distinct doping techniques: work function-induced electrostatic doping (WED) and bias-induced electrostatic doping (BED). The proposed design approach leads to significant improvements in gain and cut-off frequency compared to previously reported designs. The resulting devices exhibit peak current gain $\beta$ values $>1100$, $f_t>500$ GHz, $f_{max}>1300$ GHz. Moreover, these improved device performance matrices get translated into better performance of universal gates with low rise and fall time of $\sim 1.3$ ns, and improved noise margin performance in static random access memory (SRAM) device of 0.43 and 0.41 for WED and BED based devices respectively. Furthermore, the study investigates the reliability of the device concerning breakdown voltage and its response to different temperature conditions. The findings reveal a decline in the $\beta$ value for WED-based devices when subjected to temperatures exceeding $340$ K. In contrast, BED-based devices demonstrate a comparatively smaller variation in $\beta$ at temperatures above $340$ K. These results show the potential of the proposed device for mixed-signal and digital circuit applications.

—Reversible Logic Gates have become very popular for their uninhibited merits like, low power consumption, low garbage output, decreasing the quantum cost, least propagation delay etc. Several circuits have been designed for reversible logic ICs using conventional CMOS technology. But, as the CMOS technology is suffering from scaling down problems, the researchers have moved themselves towards post CMOS devices for further fabrication of Reversible ICs. Among different post CMOS devices, in SET, electrons are tunnelling through the channel one by one, so it offers ultra-low power dissipation compared to the traditional CMOS though it has high speed, high gain like properties. So the hybridization of CMOS-SET can achieve a useful effect on VLSI design, and the new technology is known as Hybrid CMOS-SET (HCS). But as the Hybrid CMOS-SET requires two distinct software, the HCS macro model has become very useful, as it can be simulated by using a single software. In this present paper, the reversible logic gate has been designed using the HCS macro model and is also being simulated using a single software, MATLAB with SIMULINK, with low power consumption.

Leveraging two types of enhanced delay stages to form an oscillation loop, results in a highly reliable CMOS ring oscillator versus external interventions. The idea is investigated via symbolic delay calculations and the HSPICE circuit simulator while 0.18 μm CMOS is exploited. Based on two described inverters, three-ring oscillators are presented. The two ones use only one type of delay stage while the third is combined using two basic inverters and a single current-starved inverter. The basic type inverter is the fastest while is sensitive to power supply and temperature variations. On the other hand, the sensitivity of the current starved inverter is acceptable but this delay stage shows a large delay time, reducing oscillation frequency. This work tries to address this tradeoff between speed and sensitivity by proposing an oscillation loop. The delay times analysis and simulation results verify the robust performance of the proposed oscillator.