This paper presents a novel approach to implementing artificial neural networks (ANNs) using analog circuits with counter circuits for storing and updating the weights and biases. The counter circuits, which are sequential logic circuits, provide a more precise and stable method for storing and updating the network parameters, compared to memristors. The paper also discusses the design of a multiplier circuit and a hyperbolic function activation circuit used in the neural network. The neural network model based on the XNOR logic function was simulated using a simulation program with integrated circuit emphasis (SPICE), demonstrating its learning capability as the error decreased for each epoch of training. The proposed methodology offers significant advantages for neuromorphic computing, especially in the domain of Internet of Things (IoT), where near-sensor data analysis and edge computation are essential.
{"title":"Development of an analog topology for a multi-layer neuronal network","authors":"Luã da Porciuncula Estrela , Marlon Soares Sigales , Elmer A. Gamboa Peñaloza , Marcelo Lemos Rossi , Mateus Beck Fonseca","doi":"10.1016/j.memori.2025.100125","DOIUrl":"10.1016/j.memori.2025.100125","url":null,"abstract":"<div><div>This paper presents a novel approach to implementing artificial neural networks (ANNs) using analog circuits with counter circuits for storing and updating the weights and biases. The counter circuits, which are sequential logic circuits, provide a more precise and stable method for storing and updating the network parameters, compared to memristors. The paper also discusses the design of a multiplier circuit and a hyperbolic function activation circuit used in the neural network. The neural network model based on the XNOR logic function was simulated using a simulation program with integrated circuit emphasis (SPICE), demonstrating its learning capability as the error decreased for each epoch of training. The proposed methodology offers significant advantages for neuromorphic computing, especially in the domain of Internet of Things (IoT), where near-sensor data analysis and edge computation are essential.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100125"},"PeriodicalIF":0.0,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143422695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-11DOI: 10.1016/j.memori.2025.100127
Amir Ali Mohammad Khani , Alireza Barati Haghverdi , Ilghar Rezaei , Farzane Soleimani Rudi , Toktam Aghaee
Periodic arrays of graphene disks are leveraged to form a toxic gas detector. The operational frequency range is the THz gap. The idea stems from the middle air gap which is surrounded by graphene-spacer layers while a fully reflecting metallic surface is placed underneath. The change in the refractive index of the air gap due to the presence of some toxic gases leads to absorption deviations. Interpreting the known deviations can define a detection protocol in the THz spectrum. This work proposes a three-layer wave absorber based on the graphene patterns, TOPAS spacer, and the golden surface. Each component is modeled by the passive circuit element and the total impedance of the structure is calculated. Additionally, the impedance matching concept is investigated to predict absorption response. Furthermore, full-wave simulation is performed to compare with the circuit model approach. Based on the simulation results, a multi-band absorption response experiences considerable frequency shifts when exposed to some toxic gases including SO2, N2, NO2, O3, and CO. More importantly, the capability of being tuned via external chemical potential makes the proposed absorber an ideal basic building block for healthcare-based optical systems.
{"title":"A graphene-based toxic detection approach","authors":"Amir Ali Mohammad Khani , Alireza Barati Haghverdi , Ilghar Rezaei , Farzane Soleimani Rudi , Toktam Aghaee","doi":"10.1016/j.memori.2025.100127","DOIUrl":"10.1016/j.memori.2025.100127","url":null,"abstract":"<div><div>Periodic arrays of graphene disks are leveraged to form a toxic gas detector. The operational frequency range is the THz gap. The idea stems from the middle air gap which is surrounded by graphene-spacer layers while a fully reflecting metallic surface is placed underneath. The change in the refractive index of the air gap due to the presence of some toxic gases leads to absorption deviations. Interpreting the known deviations can define a detection protocol in the THz spectrum. This work proposes a three-layer wave absorber based on the graphene patterns, TOPAS spacer, and the golden surface. Each component is modeled by the passive circuit element and the total impedance of the structure is calculated. Additionally, the impedance matching concept is investigated to predict absorption response. Furthermore, full-wave simulation is performed to compare with the circuit model approach. Based on the simulation results, a multi-band absorption response experiences considerable frequency shifts when exposed to some toxic gases including SO<sub>2</sub>, N<sub>2</sub>, NO<sub>2</sub>, O<sub>3,</sub> and CO. More importantly, the capability of being tuned via external chemical potential makes the proposed absorber an ideal basic building block for healthcare-based optical systems.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100127"},"PeriodicalIF":0.0,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143429438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-02-07DOI: 10.1016/j.memori.2025.100126
Mohammadreza Nehzati
This paper introduces a unique method for boosting the efficiency of deep learning algorithms in processing large amounts of virtual facts. This approach leverages evolutionary neural networks, integrating deep mastering algorithms with evolutionary algorithms to enhance the overall performance of convolutional neural networks (CNNs) and recurrent neural networks (RNNs). The proposed optimization technique employs evolutionary operators such as natural choice, version aggregate, and random weight mutations to discover massive and complicated seek areas. The innovation of this studies lies inside the use of evolutionary neural networks to enhance the accuracy, convergence speed, and generalization capabilities of deep mastering algorithms while managing big virtual datasets. Empirical findings imply that the proposed technique notably improves the effectiveness of deep mastering algorithms in coping with sizeable digital datasets.
{"title":"Optimization of deep learning algorithms for large digital data processing using evolutionary neural networks","authors":"Mohammadreza Nehzati","doi":"10.1016/j.memori.2025.100126","DOIUrl":"10.1016/j.memori.2025.100126","url":null,"abstract":"<div><div>This paper introduces a unique method for boosting the efficiency of deep learning algorithms in processing large amounts of virtual facts. This approach leverages evolutionary neural networks, integrating deep mastering algorithms with evolutionary algorithms to enhance the overall performance of convolutional neural networks (CNNs) and recurrent neural networks (RNNs). The proposed optimization technique employs evolutionary operators such as natural choice, version aggregate, and random weight mutations to discover massive and complicated seek areas. The innovation of this studies lies inside the use of evolutionary neural networks to enhance the accuracy, convergence speed, and generalization capabilities of deep mastering algorithms while managing big virtual datasets. Empirical findings imply that the proposed technique notably improves the effectiveness of deep mastering algorithms in coping with sizeable digital datasets.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100126"},"PeriodicalIF":0.0,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143403101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-20DOI: 10.1016/j.memori.2025.100124
Liu Jikang
With the development of advanced technologies, the importance of semiconductor packaging has been further highlighted. To meet the increasing complexity and performance requirements of semiconductor devices, many integrated circuit (IC) advanced packaging technologies have been developed, which including flip chip (FC), bumping, fan-in wafer level packaging (FIWLP), fan-out wafer level packaging (FOWLP), 2.5D packaging (interposer), CMOS image sensor through silicon via (CIS-TSV), fan-out panel level packaging (FOPLP) and so on. During the manufacturing process of those IC advanced packaging technologies, many organic materials including photoresist (PR), photosensitive polyimide (PSPI), underfill, epoxy molding compound (EMC), temporary bonding adhesive, high temperature bonding adhesive, dry film and printing ink have been applied. In this paper, we described the application of organic materials including PR, PSPI, underfill, EMC, temporary bonding adhesive, high temperature bonding adhesive, dry film and printing ink used in the IC advanced packaging.
{"title":"The application of organic materials used in IC advanced packaging:A review","authors":"Liu Jikang","doi":"10.1016/j.memori.2025.100124","DOIUrl":"10.1016/j.memori.2025.100124","url":null,"abstract":"<div><div>With the development of advanced technologies, the importance of semiconductor packaging has been further highlighted. To meet the increasing complexity and performance requirements of semiconductor devices, many integrated circuit (IC) advanced packaging technologies have been developed, which including flip chip (FC), bumping, fan-in wafer level packaging (FIWLP), fan-out wafer level packaging (FOWLP), 2.5D packaging (interposer), CMOS image sensor through silicon via (CIS-TSV), fan-out panel level packaging (FOPLP) and so on. During the manufacturing process of those IC advanced packaging technologies, many organic materials including photoresist (PR), photosensitive polyimide (PSPI), underfill, epoxy molding compound (EMC), temporary bonding adhesive, high temperature bonding adhesive, dry film and printing ink have been applied. In this paper, we described the application of organic materials including PR, PSPI, underfill, EMC, temporary bonding adhesive, high temperature bonding adhesive, dry film and printing ink used in the IC advanced packaging.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100124"},"PeriodicalIF":0.0,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.
{"title":"Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications","authors":"Venkata Sudhakar Chowdam , Suresh Babu Potladurty , Prasad Reddy karipireddy","doi":"10.1016/j.memori.2025.100123","DOIUrl":"10.1016/j.memori.2025.100123","url":null,"abstract":"<div><div>The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100123"},"PeriodicalIF":0.0,"publicationDate":"2025-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-10DOI: 10.1016/j.memori.2025.100121
Kanchan S. Tiwari
This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry.
{"title":"Design of generic vedic ALU using reversible logic","authors":"Kanchan S. Tiwari","doi":"10.1016/j.memori.2025.100121","DOIUrl":"10.1016/j.memori.2025.100121","url":null,"abstract":"<div><div>This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100121"},"PeriodicalIF":0.0,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-10DOI: 10.1016/j.memori.2025.100122
Farzane Soleimani Rudi, Mohammad Naser Hashemnia
This work proposes an active shunt filter design for grid-connected solar systems, utilizing the p-q instantaneous power theory technique to minimize grid harmonics and reduce reactive power. As a result, the total harmonic distortion (THD) is decreased, and the power quality of the network is improved. To optimize the efficiency of solar panels and generate the switching control signal of the boost converter, the Perturb and Observe (P&O) method and Pulse Width Modulation (PWM) technique are employed, respectively. The active shunt filter extracts the harmonic components of the load current using the p-q theory, which serves as a reference signal for compensation. A hysteresis method is used to control the filter current and produce the pulses for the filter switches. The designed filter reduces the harmonic distortion in the load current to approximately 29.91%. A comparison between the harmonic reference signal and the injected filter current to the three-phase grid confirms the correctness of the design. Moreover, the sinusoidal waveform of the three-phase grid currents demonstrates the effectiveness of the proposed controller. Simulation results in MATLAB validate the proposed filter, with the network current THD reduced to less than 5%, confirming the efficacy of the design.
{"title":"Compensation of active filter using p-q theory in photovoltaic systems","authors":"Farzane Soleimani Rudi, Mohammad Naser Hashemnia","doi":"10.1016/j.memori.2025.100122","DOIUrl":"10.1016/j.memori.2025.100122","url":null,"abstract":"<div><div>This work proposes an active shunt filter design for grid-connected solar systems, utilizing the p-q instantaneous power theory technique to minimize grid harmonics and reduce reactive power. As a result, the total harmonic distortion (THD) is decreased, and the power quality of the network is improved. To optimize the efficiency of solar panels and generate the switching control signal of the boost converter, the Perturb and Observe (P&O) method and Pulse Width Modulation (PWM) technique are employed, respectively. The active shunt filter extracts the harmonic components of the load current using the p-q theory, which serves as a reference signal for compensation. A hysteresis method is used to control the filter current and produce the pulses for the filter switches. The designed filter reduces the harmonic distortion in the load current to approximately 29.91%. A comparison between the harmonic reference signal and the injected filter current to the three-phase grid confirms the correctness of the design. Moreover, the sinusoidal waveform of the three-phase grid currents demonstrates the effectiveness of the proposed controller. Simulation results in MATLAB validate the proposed filter, with the network current THD reduced to less than 5%, confirming the efficacy of the design.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100122"},"PeriodicalIF":0.0,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140357","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-13DOI: 10.1016/j.memori.2024.100120
Rajkumar Mandal, Arka Mandal, Nayan Pandit, Rajib Nath, Biswanath Mukherjee
This study reports the synthesis of manganese dioxide (MnO2) nanowires via the hydrothermal method and the fabrication of high-performance memristor devices using solution-processed MnO2 nanowires. Microstructural characterizations, viz, XRD, SEM, EDAX and XPS of synthesized sample revealed highly crystalline structures of MnO2 nanowires. As synthesized MnO2 nanowires, mixed in different weight percentages with poly(methyl methacrylate) (PMMA) solution were deposited on Al electrode to form thin film memristor devices. Resistive switching with both analog and digital behaviors have been realized in Al/MnO2-PMMA/Al device by controlling the weight percentage (wt %) of MnO2 in the composite. When the MnO2 wt % in the composite was low (PMMA: MnO2 = 1:1), the device exhibited analog type switching, while, the higher concentration of MnO2 produced digital types of switching. The On/Off current ratio of the device increased gradually with increase in MnO2 wt %, reaching the highest switching ratio, ca. 106 and excellent endurance (>104 s) for PMMA:MnO2 = 1:8. Temperature dependent charge transport behavior and impedance spectroscopy was further carried out to explain the underlying resistive switching mechanism of the device.
{"title":"High performance memristor device from solution processed MnO2 nanowires: Tuning of resistive switching from analog to digital and underlying mechanism","authors":"Rajkumar Mandal, Arka Mandal, Nayan Pandit, Rajib Nath, Biswanath Mukherjee","doi":"10.1016/j.memori.2024.100120","DOIUrl":"10.1016/j.memori.2024.100120","url":null,"abstract":"<div><div>This study reports the synthesis of manganese dioxide (MnO<sub>2</sub>) nanowires via the hydrothermal method and the fabrication of high-performance memristor devices using solution-processed MnO<sub>2</sub> nanowires. Microstructural characterizations, <em>viz</em>, XRD, SEM, EDAX and XPS of synthesized sample revealed highly crystalline structures of MnO<sub>2</sub> nanowires. As synthesized MnO<sub>2</sub> nanowires, mixed in different weight percentages with poly(methyl methacrylate) (PMMA) solution were deposited on Al electrode to form thin film memristor devices. Resistive switching with both analog and digital behaviors have been realized in Al/MnO<sub>2</sub>-PMMA/Al device by controlling the weight percentage (wt %) of MnO<sub>2</sub> in the composite. When the MnO<sub>2</sub> wt % in the composite was low (PMMA: MnO<sub>2</sub> = 1:1), the device exhibited analog type switching, while, the higher concentration of MnO<sub>2</sub> produced digital types of switching. The On/Off current ratio of the device increased gradually with increase in MnO<sub>2</sub> wt %, reaching the highest switching ratio, <em>ca.</em> 10<sup>6</sup> and excellent endurance (>10<sup>4</sup> s) for PMMA:MnO<sub>2</sub> = 1:8. Temperature dependent charge transport behavior and impedance spectroscopy was further carried out to explain the underlying resistive switching mechanism of the device.</div></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"9 ","pages":"Article 100120"},"PeriodicalIF":0.0,"publicationDate":"2024-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143140409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols i.e. and . In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from https://github.com/Aggtur11/Ternary-Logic-Simulator. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.
{"title":"Design and Simulation of Balanced Ternary Priority Encoder","authors":"Aadarsh Ganesh Goenka , Shyamali Mitra , Harsh Maheshwari , Nibaran Das","doi":"10.1016/j.memori.2024.100118","DOIUrl":"10.1016/j.memori.2024.100118","url":null,"abstract":"<div><p>The priority encoder is a frequently used circuit in binary logic and is mostly used for interrupt handling and other priority resolving tasks. On the other hand, Ternary computing has tremendous potential for handling a wide variety of functions involving large range of numbers, whereas, the literature is confined to very basic functions. The proposed balanced priority encoder circuit that uses three logic symbols <em>i.e.</em> <span><math><mrow><mo>−</mo><mn>1</mn><mo>,</mo><mn>0</mn></mrow></math></span> and <span><math><mn>1</mn></math></span>. In this study, we develop the design and architecture of a Ternary Priority Encoder circuit with an estimation of its time complexity. The intricacy of the circuit under consideration is supposed to highlight the capabilities of the ternary logic system. The flexibility of the circuit lies in its implementation using simple binary counterparts. As there is no simulator available for Ternary Logic, we have developed a Balanced Ternary Logic Simulator which is freely available from <span><span>https://github.com/Aggtur11/Ternary-Logic-Simulator</span><svg><path></path></svg></span>. The logic behaviour of the proposed priority encoder circuits is verified using the developed simulator.</p></div>","PeriodicalId":100915,"journal":{"name":"Memories - Materials, Devices, Circuits and Systems","volume":"8 ","pages":"Article 100118"},"PeriodicalIF":0.0,"publicationDate":"2024-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S2773064624000215/pdfft?md5=0125d5dde1a559ad3c35ae9b6fcbac2c&pid=1-s2.0-S2773064624000215-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141846606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-07-02DOI: 10.1016/j.memori.2024.100117
Priyanka Agrwal, Ajay Kumar
In this work, a high-k In0.53Ga0.47As silicon-on-insulator FinFET (InGaAs–SOI–FinFET) is presented for high-switching and ultra-low power applications at 7 nm gate length. Indium Gallium Arsenide (InGaAs) is a compound semiconductor that has gained attention in the field of semiconductor devices, including FinFETs. The incorporation of InGaAs in proposed FinFETs introduces several advantages, making it an attractive material for certain applications. InGaAs–SOI–FinFET performance has been observed and found high electron mobility, improved On-Current performance (ION), drain current (IDS), transconductance (gm), energy bands, lower subthreshold swing (SS), electric field, surface potential, and better short-channel behaviour. All the results of InGaAs–SOI–FinFET have been simultaneously compared with SOI-FinFET and conventional FinFET (C-FinFET). Incorporating InGaAs in the channel with high-k gate material enhances the drain current by ⁓75% and ⁓77% in the proposed device compared to the other two counterparts. Owing to the higher drain current in the InGaAs–SOI–FinFET, other parameters have also been improved, which leads to higher performance applications.
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