Memories - Materials, Devices, Circuits and Systems最新文献

An ultra-thin microwave absorber with a 34 GHz bandwidth more than 90% absorption in the frequency range of 33.5 GHz - 67.5 GHz, and 50 GHz bandwidth, more than 80 % absorption is proposed. The functionality of the device was analyzed using an equivalent circuit model (ECM) by exploiting the impedance matching concept in the transmission line theory. By changing the chemical potential of the graphene, following manipulating characteristics of the graphene surface conductivity, can achieve several absorption responses in wideband range frequencies. Additionally, the proposed absorption is stable in a wide range of incident angles. These advantages make the proposed absorption attractive for several applications such as optical sensors and detectors.

Physically Unclonable Function (PUF) is an emerging modern approach to the security concerns of the physical systems which require the protection of sensitive data. PUF generates unique, reliable, and secure responses which can be utilized for cryptographic applications. In this paper, a fault-tolerant reversible logic gate-based RO PUF is proposed. We utilized a fault-tolerant reversible logic Double Feynman Gate in place of conventional inverters to design the ring oscillators (RO). The proposed RO PUF designs implemented and evaluated on the Basys-3 Artix-7 FPGA board. The PUF parameters such as uniqueness, reliability, and uniformity were analyzed based on the experimental results. The empirical results show that the proposed RO PUF has uniqueness and reliability of 0.49 and 85.95%, respectively. The inter-chip and intra-chip uniqueness for the proposed design is 23% and 25.5%, respectively higher than the conventional RO PUF design. This fault-tolerant reversible logic gate-based RO PUF design shows better uniqueness, reliability, and uniformity than other considered PUF designs.

Light emitting nano-scale materials have attracted a great interest in recent days. In view of this, a nanocrystal solid luminescent composite material was prepared using combustion processing technique and its identity was analyzed and further investigated. The precursor reagents were measured using the single pan analytical balance. A sample was synthesized and its functional group was identified using the FTIR spectroscopy and XRD studies as having similar properties to those in Batch No. JCPDS No. 77-1149 and in Base Code AMCSD 0008032. Its photoluminescence spectrum identified peaks located at 476 nm, 578 nm and 615 nm that were attributed to electronic transition from ⁴$F_{\mathrm{9/2}}$ to ⁶H${}_{\mathrm{15/2}}$, from ⁴$F_{\mathrm{9/2}}$ to ⁶H${}_{\mathrm{13/2}}$ and from ⁴$F_{\mathrm{9/2}}$ to ⁶H${}_{\mathrm{11/2}}$ respectively as the finger blue-prints of dysprosium [Dy${}^{3+}$] ion. Its crystalline sizes and strains were calculated using the Debay Scherrer’s equation and analyzed using the UDM model. The findings showed that the prepared sample had a superior homogeneity and further that the Dy${}^{3+}$ influenced its formation. The mellite sample was identified to be Ca₂MgSi₂O₇:Dy${}^{3+}$. Further analysis on the sample suggested that was a potential white light emitting luminescent material just like Ca₂MgSi₂O₇:Tb${}^{3+}$ phosphor and Sr₂MgSi₂O₇:Dy${}^{3+}$ phosphor.

Convolutional neural networks (CNNs) are widely implemented in modern facial recognition systems for image recognition applications. Runtime speed is a critical parameter for real-time systems. Traditional FPGA-based accelerations require either large on-chip memory or high bandwidth and high memory access time that slow down the network. The proposed work uses an algorithm and its subsequent hardware design for a quick CNN computation using an overlap-and-add-based technique in the time domain. In the algorithm, the input images are broken into tiles that can be processed independently without computing overhead in the frequency domain. This also allows for efficient concurrency of the convolution process, resulting in higher throughput and lower power consumption. At the same time, we maintain low on-chip memory requirements necessary for faster and cheaper processor designs. We implemented CNN VGG-16 and AlexNet models with our design on Xilinx Virtex-7 and Zynq boards. The performance analysis of our design provides 48% better throughput than the state-of-the-art AlexNet and uses 68.85% lesser multipliers and other resources than the state-of-the-art VGG-16.

There has been an increasing interest in the development of deep-learning models for the large data processing such as images, audio, or video. Image processing has made breakthroughs in addressing important problems such as genome-wide biological networks, map interactions of genes and proteins, network, etc. With the increase in sophistication of the system, and other areas such as internet of things, social media, web development, etc., the need for classification of image data has been felt more than ever before. It is more important to develop intelligent approaches that can take care of the sophistication of systems. Several researchers are working on the real-time images to solve the problems related to the classification of images. The algorithms to be developed will have to meet the large image datasets. In this paper, the generalized hierarchical fuzzy deep learning approach is discussed and developed to meet such demands. The objective is to design the algorithm for image classification so that it results in high accuracy. The approach is for real-life intelligent systems and the classification results have been shared for large image datasets such as the YaleB database. The accuracy of the algorithm has been obtained for various classes of images using image thresholding. The development of learning algorithms has been validated on corrupted and noisy data and results of various classes of images are presented.

In deep space exploration environment, electronic devices face severe tests. C4 solder joints and TSV, as the weak links of the three-dimensional packaging structure, have a significant impact on the reliability of the packaging structure. This work focuses on the typical three-dimensional packaging structure and utilizes finite element software to analyze the influence of extreme thermal cycling on the fatigue life of packaging structure. The results show that under the extreme temperature range of -100$\sim$120 °C, the maximum stress concentration of a typical 3D packaging structure occurs at the interface between the TSV and Si chip, and the TSV and C4 solder joints remote from the center bear greater stress and strain. The maximum stress of TSV appears at the end edge of TSV at the upper left corner. The maximum stress of the C4 welding spot appears on the second welding spot in the rightmost column. The most dangerous TSV fatigue life is 1.07 × 10⁷ cycles calculated by combining the finite element simulation results with the Coffin Manson model. The life of the most dangerous C4 solder joint is 2892 cycles. C4 solder joint is the failure-sensitive location of the three-dimensional packaging structure under extreme ambient temperature, and optimization design is required in the subsequent work to improve its reliable life.

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.

This work presents a novel 4-bit subranging nonuniform sampling (NUS) memristive neural network-based analog-to-digital converter (ADC) with improved performance trade-off among speed, power, area, and accuracy. The proposed design preserves the memristive neural network calibration and utilizes a trainable memristor weight to adapt to device mismatch and increase accuracy. Rather than conventional binary searching, we adopt quaternary searching in the ADC to realize subranging architecture’s coarse and fine bits determination. A level-crossing nonuniform sampling (NUS) is introduced to the proposed ADC to enhance the ENOB under the same resolutions, power, and area consumption. Area and power consumption are reduced through circuit sharing between different stages of bit determination. The proposed 4-bit ADC achieves a highest ENOB of 5.96 and 5.6 at cut-off frequency (128 $\mathrm{MHz}$) with power consumption of 0.515 $\mathrm{mW}$ and a figure of merit (FoM) of 82.95 $\mathrm{fJ/conv}$.

In this article, the flux-charge analysis method is applied to obtain the theoretical response of the voltage generated in a parallel Memristor–Capacitor (M–C) circuit excited by an input pulse generator with a 100 kHz frequency, 5 V amplitude and a 50 ohms output impedance. The theoretical solution of the nonlinear ordinary differential equation that results when applying the method is reached by a numerical method. As a memristive circuit, a previously reported floating memristor emulator was used. The response obtained is compared with the experimental response, generating evidence that the applied analysis method yields an acceptable margin of error with regards to the experimental results obtained, contrasting with other similar reports, where the analyzes are based on theoretical memristive models, and show simulation results only. Summary, the paper would contribute to the analysis and experimental verification of the parallel M–C circuit subjected to a real switched exciting source, using a memristance equation established in an emulator that is different from the equations commonly used in the literature.