Memories - Materials, Devices, Circuits and Systems最新文献

This research article discusses the challenges faced by the Network-on-Chip (NoC) architecture due to increased integration density and proposes a novel fault-tolerant multi-application mapping approach called ”FANC.” The approach is based on Machine Learning (ML) and can provide solutions for unseen graphs and topologies without prior training. The proposed technique uses an ML-based model to extract relevant information from the search data and incorporate it into the search process. This results in a more robust model with a higher convergence rate and solution quality. The approach is evaluated using a variety of simulation parameters, such as communication cost, network latency, throughput, and power usage. Static simulations are performed in a Python programming environment, while dynamic simulations are performed with a SystemC-based cycle-accurate NoC simulator and the Orion2.0 Power tool. The results show that FANC reduces communication costs by 266%. It also improves network latency by 9%, throughput by 1%, and power consumption by 7%. The approach also simplifies and minimizes the search area in the design exploration process and can be used as an auxiliary component for other optimization algorithms.

Resistive memory (ReRAM) or memristor devices offer the prospect of more efficient computing. While memristors have been used for a variety of computing systems, their usage has gained significant popularity in the domain of deep learning. Weight matrices in deep neural networks can be mapped to crossbar architectures with memristive junctions, generally resulting in superior performance and energy efficiency. However, the nascent nature of ReRAM technology is directly associated with the presence of inherent non-idealities in the ReRAM devices currently available. Deep neural networks have already been shown to be susceptible to adversarial attacks, often by targeting vulnerabilities in the networks’ internal representation of input data. In this paper, we explore the causal relationship between device-level non-idealities in ReRAM devices and the classification performance of memristor-based neural network accelerators. Specifically, our aim is to generate images which bypass adversarial defense mechanisms in software neural networks but trigger non-trivial performance discrepancies in ReRAM-based neural networks. To this end, we have proposed a framework to generate adversarial images in the hypervolume between the two decision boundaries, thereby leveraging non-ideal device behavior for performance detriment. We employ state-of-the-art tools in explainable artificial intelligence to characterize our adversarial image samples, and derive a new metric to quantify susceptibility to adversarial attacks at the pixel and device-levels.

The performance of a 3D IC is primarily reliant on the selection of an appropriate bump shape. The most prevalent bump shape (cylindrical) is experiencing substantial stress, power loss and crosstalk issues. TSV bump with a tapered structure have recently attracted considerable attention owing to its low volume fraction and coupling capacitance, that can substantially reduce the stress and crosstalk concerns. An impact of the redistribution layer (RDL), intermetal dielectric and high frequency skin effect are appropriately taken into account for the tapered TSV (T-TSV) with a cylindrical, barrel and tapered bump shape. A mathematical framework of the resistance–inductance–conductance–capacitance (RLGC) structure of the proposed T-TSV have been formulated by effectively considering the coupling, passivation and fringing capacitance of the RDL. In order to benchmark the proposed electrical equivalent circuit, the structural model of the T-TSV is validated against the fabrication based experimental results, and a subsequent analysis have been performed for the stress, crosstalk induced delay, and power loss. The proposed TSV structure is in good agreement with the experimental results with an average deviation of only 2.8%. Furthermore, irrespective of bump height, the tapered bump based T-TSV can effectively reduce the overall crosstalk induced delay, stress, power delay product (PDP), insertion and reflection losses with an average deviation of 20.22%, 22.30%, 23.55%, 8.01%, and 10.32%, respectively, when compared to the barrel and cylindrical bumps. In addition, it has been observed that the overall rate of change in PDP, power losses and crosstalk induced delay with considering RDL are 18.8%, 20.50%, and 25.22%, respectively independent of the bump shapes.

Smart computing on edge-devices has demonstrated huge potential for various application sectors such as personalized healthcare and smart robotics. These devices aim at bringing smart computing close to the source where the data is generated or stored, while coping with the stringent resource budget of the edge platforms. The conventional Von-Neumann architecture fails to meet these requirements due to various limitations e.g., the memory-processor data transfer bottleneck. Memristor-based Computation-In-Memory (CIM) has the potential to realize such smart edge computing for data-dominated Artificial Intelligence (AI) applications by exploiting both the inherent properties of the architecture and the physical characteristics of the memristors. This paper discusses different aspects of CIM, including classification, working principle, CIM potentials and CIM design-flow. The design-flow is illustrated through two case studies to demonstrate the huge potential of CIM in realizing orders of magnitude improvement in energy-efficiency as compared to the conventional architectures. Finally future challenges and research directions of CIM are covered.

As the shrinkage of devices accelerates and the vertical layers increase, beam angle spread of carbon ion implantation (C IIP) for the silicon selective epitaxial growth (Si-SEG) areas in V-NAND is one of the most critical parameters related with bin map defects. The roles of C IIP in Si-SEGs are that it can suppress channeling effect of boron IIP and diffusion limitation of boron dopants during subsequent annealing processes. In this study, beam angle spread was reduced by 36% and the center-to-edge beam angle skew of wafer was reduced to less than 1° by optimizing the specification of tracking magnet and the beam angle mean. After applying the improved process conditions and effective interlocks, the bin defective rate was controlled less than 0.5% successfully.

The core components of both traditional and contemporary control systems are the proportional–integral–derivative (PID) control systems, which have established themselves as standards for technical and industrial applications. Therefore, the tuning of the PID controllers is of high importance. Utilizing optimization algorithms to reduce the mean square error of the controller’s output is one approach of tuning PID controllers. In this paper, an appropriately modified metaheuristic optimization algorithm dubbed beetle antennae search (BAS) is employed for robust tuning of PID controllers. The findings of three simulated experiments on stabilizing feedback control systems show that BAS produces comparable or higher performance than three other well-known optimization algorithms while only consuming a tenth of their time.

This paper presents a capacitorless memory cell with bulk CMOS compatibility, consisting of a MOSFET with a virtual floating body formed by the trench. The name Key shape Floating Body Memory (KFBM) is derived from the resemblance of the structure to the shape of an antique key. The carrier concentration in the vertical device beneath the MOSFET results in over more than 5 orders of magnitude of the on–off cell current ratio with off-current less than 100pA/cell. The device achieves a retention time of about 1 s at 85C and over 10 s at 27C all the while maintaining high density and scalability. On the basis of TCAD simulation we have demonstrated high tolerance to disturbance (more than 1000 times with all types of signals), which has been an issue with DRAM memories. KFBM can incorporate both dynamic RAM and flash features.

In our work, we studied the effect of isotropic strain from −6% to 8% (compressive to tensile) on the Band gap, Elastic, Spin-polarization and Magnetic properties of Co₂TiGe heusler alloy. We found that the half-metallicity (100% Polarization) is maintained under uniform strain from −2% to 4% but for the strain −4% to −6% the Spin-polarization drops quickly from 94% to 5.363%. From the study of electronic band structure we found that the energy band gap decreases with the increase of tensile strain and increase with the increase of compressive strain. For strain free compound the calculated magnetic moment of the material is 2.00 $\mu$B. We have found that under −4% to 8% uniform strain the total magnetic moment of the compound remains constant. But for strain −6% it decreases to 1.91 $\mu$B. We have calculated the mechanical properties of the material under different uniform strain. So, from the computed values we found the Bulk modulus, Young modulus, Shear modulus, Pugh’s ratio and Poisson ratio decreases with the tensile strain and increases with the compressive strain. With the increase of tensile strain (up to 8%) brittle nature of the material increases but with the increase of compressive strain (up to −6%) ductile of the material increases.

Composite solders of $1\mu m$ Zn particles and Sn-0.3Ag-0.7Cu (SAC0307) with a particle size of $25\sim 38\mu m$ was used to achieve micro-joining of Cu/Cu under ultrasonic-assisted at 180 °C, and aging at 125 °C was used to strengthen Cu/Cu joints. The results showed that interface intermetallic compounds (IMCs) between Cu substrates and solder were mainly smooth Cu₅Zn₈, and the Zn–Sn–Cu phase was formed to complete interconnection between SAC0307 particles at 180 °C. With the increase of aging time, the shear strength of joints first increased and reached a peak value of 36.26MPa at 2h which was 21.8% higher than that of the as-received joints, then the shear strength decreased and tended to be stable at 24h which was increased by 10.0% compared with that of the as-received joints.

The paper proposes a novel nature-inspired optimization technique called Eagle Perching Optimizer (EPO). It is an addition to the family of swarm-based meta-heuristic algorithms. It mimics eagles’ perching nature to find prey (food). The EPO is based on the exploration and exploitation of an eagle when it descends from the height such that it formulates its trajectory in a way to get to the optimal solution (prey). The algorithm takes bigger chunks of search space and looks for the optimal solution. The optimal solution in that chunk becomes the search space for the next iteration, and this process is continuous until EPO converges to the optimal global solution. We performed the theoretical analysis of EPO, which shows that it converges to the optimal solution. The simulation includes three sets of problems, i.e., uni-model, multi-model, and constrained real-world problems. We employed EPO on the benchmark problems and compared the results with state-of-the-art meta-heuristic algorithms. For the real-world problems, we used a cantilever beam, three-bar truss, and gear train problems to test the robustness of EPO and later made the comparison. The comparison shows that EPO is comparable with other known meta-heuristic algorithms.