Memories - Materials, Devices, Circuits and Systems最新文献

For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 $nJ$ energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.

Timing design rule check (T-DRC) convergence follows an iterative procedure like physical design closure. On a medium-complex design, the conventional flow of T-DRC convergence requires about 14 h per iteration, which includes fill insertion, sign-off accurate standard parasitic extraction format generation, sign-off static timing analysis, engineering change order (ECO) list generation in the multi-corner multi-mode scenario, fill removal, and implementation of the ECO on the pre-fill design. The T-DRC values generated from the pre-fill stage auto-place and route tool often have a miscorrelation with the sign-off values obtained from the static timing analysis tool. Due to the correlation gap, designers prefer to wait for the ECO change list to be created by the sign-off tool at the end of each iteration rather than resolve it at the pre-fill stage in the construction tool. Hence, T-DRC convergence is a lengthy process. This paper discusses an automatic T-DRC convergence methodology driven by machine learning (ML) techniques. By anticipating the transition of the input pin of a cell and the capacitance of its output pin, the suggested methodology shortens the runtime of each iteration. Additionally, it forecasts the suitable buffer to correct the T-DRC violation in the case of buffer insertion. With almost accurate prediction of T-DRC values using the ML approach, the sign-off flow can now be bypassed for a few iterations during the timing convergence phase, resulting in fewer iterations in the T-DRC sign-off flow. The violation percentage and the desired buffer name are obtained from the ML prediction result for each violation. An automatic in-house T-DRC fixer flow is developed to correct the violating elements beforehand, saving around 12 h of runtime for each iteration. Since ML prediction can never be 100% accurate, the final timing sign-off should always be done with the sign-off tool and flow to ensure zero silicon bug. With the help of ML prediction and the T-DRC fixer methodology, T-DRC convergence is possible in fewer sign-off tool iterations, resulting in a left shift of about two weeks in the timing closure cycle on the actual project execution.

An enhanced three-stage CMOS transconductance amplifier attached to a novel frequency compensation network is proposed. Two differential stages are attached with Miller capacitors and the Miller effect is boosted accordingly. In this way, four negative loops intensify the Miller effect virtually. The structure is designed at the transistor level using 0.18 $\mu$m CMOS library and the SPICE simulator while a symbolical transfer function is extracted and analyzed to obtain circuit dynamics. Leveraging both concept and method, the proposed amplifier shows unconditional stability with acceptable accuracy regarding the symbolic description and simulation results. Ample sensitivity analysis is also provided to show the reliability of the amplifier. By simulation responses, the presented circuit expresses competitive merits against previous works. Simulation results show 120 dB as DC gain, 18 MHz as, GBW, and 54º as phase margin while the simulated amplifier consumes only $345\mu W$.

In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications. In this paper, an energy-efficient 10T SRAM-based IMC macro architecture is proposed to perform logic, arithmetic, and In-memory Dot Product (IMDP) operations. The average write margin and read margins of the proposed 10T SRAM are improved by 40% and 2.5%, respectively, compared to the 9T SRAM. The write energy and leakage power of the proposed 10T SRAM are reduced by 89% and 83.8%, respectively, with aproximatelly similar read energy compared to 9T SRAM. Additionally, a 4 Kb SRAM array based on 10T SRAM is implemented in 180-nm SCL technology to analyze the operation and performance of the proposed IMC macro architecture. The proposed IMC architecture achieves an energy efficiency of 5.3 TOPS/W for 1-bit logic, 4.1 TOPS/W for 1-bit addition, and 3.1 TOPS/W for IMDP operations at 1.8 V and 60 MHz. The area efficiency of 65.2% is achieved for a 136 × 32 array of proposed IMC macro architecture. Further, the proposed IMC macro is also tested for accelerating the IMDP operation of neural networks by importing linearity variation analysis in Tensorflow for image classification on MNIST and CIFAR datasets. According to Monte-Carlo simulations, the IMDP operation has a standard deviation of 0.07 percent in accumulation, equating to a classification accuracy of 97.02% on the MNIST dataset and 88.39% on the CIFAR dataset.

Sense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) for low power single ended SRAM for read operation. The sense amplifier performs dual task by charging the bit line during pre-charge phase and amplifying the bit line during evaluation phase. The proposed CSSA shows good improvement in sensing time and power at higher number of cells per bit line (CpBL). The proposed CSSA exhibits 53%, 48%, 24%, 23%, and 41% lower sensing time for 256 CpBL and 52%, 51%, 50%, 37%, and 47% lesser power consumption than the conventional domino sensing scheme (DSS), AC coupled sense amplifier (ACSA), non-strobed regenerative sense amplifier (NSRSA), switching PMOS sense amplifier (SPSA) and trip point bit line pre-charge sensing scheme (TBPSS). The proposed CSSA occupies 18%, 25%, 53%, 61%, and 37% lesser area compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA has 88%, 88%, 85%, 91%, and 87% lesser APDP (area power delay product) compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA sensing scheme is implemented and simulated in Cadence Virtuoso tool with 45 nm technology. The simulation results of CSSA prove that the proposed CSSA sense amplifier is suitable for high speed and low power SRAM architecture.

Zinc oxide ultra-thin films doping with aluminum (AZO) were produced through radio frequency (rf) sputtering at a fixed pressure of 10 mTorr while varying the rf power between 80 and 140 W. The crystal structure of hexagonal Wurtzite was consistent throughout, with improved crystallinity observed at higher rf powers due to optimal diffusivity of the sputtered particles during nucleation and growth. The size of the crystallite was increased from 10.37 to 16.58 nm with increasing the rf power from 80 to 140 W. The Raman spectra provided evidence of the formation of ultra-thin AZO films, with discernable changes in morphology due to the influence of rf power. The value of optical band gap fluctuated between 3.49 and 3.58 eV as a function of rf power, a basis of the Burstein–Moss effect. The resistivity of the ultra-thin AZO films declined while augmenting rf power. A bilayer structure of intrinsic ZnO (i-ZnO) and AZO was fabricated and exhibited good transmittance, well-crystalline morphology, and excellent electrical conductivity. The optimized window layer (i-ZnO and AZO) was used to produce flexible Cu(In,Ga)Se₂(CIGSe) solar cells with a photo conversion efficiency of 9.53%. Therefore, ultra-thin ZnO films exhibit potential as a favorable option for a window layer in the production of high-efficient flexible solar cells in cost effective way.

Leveraging both method and concept a two-layer THz absorber based on periodic arrays of graphene rings is proposed. The design methodology based on the equivalent circuit model is developed for the proposed absorber. The device is described as an impedance and also simulated by the FEM full-wave method to verify the circuit model accuracy. According to the simulation results, the proposed THz absorber can show perfect absorption from 0.5 THz to 3.5 THz while adjustability capability is obtained for different chemical potentials. Additionally, the sensitivity against geometrical parameters and different incident angels is investigated. Based on the provided results and the simplicity of the structure, the proposed absorber is an ideal candidate for several applications ranging from security to medical imaging.

This paper presents an inventive and extremely dependable radiation-hardened by-design (RHBD) 12T SRAM Cell with enhanced writing capability (RHWC-12T) for a space radiation environment. The Proposed RHWC-12T SRAM is designed on Cadence Virtuoso with quad-storage nodes and simulated in 45-nm CMOS technology with the supply voltage of 1.1 V and 27${}^{\circ }$C operating temperature. The proposed cell is tolerant to both 0 to 1 and 1 to 0 SEUs (Single event upsets). Also, it provides better speed and stability compared to the other considered SRAM cells such as 6T, 10T Dohar, Quatro, We-Quatro, QUCCE-12T, and NQuatro. According to simulation findings, the proposed SRAM cell provides 1.053$\times$ better writing stability than the 10T Dohar SRAM cell. In addition, the write access time improves by 3.56$\times$ with 1.36$\times$ area overhead than 10T Dohar SRAM cell.

Memristor-based crossbar architecture emerges as a promising candidate for 3-D memory and neuromorphic computing. However, the sneak current through the unselected cells becomes a fundamental roadblock to their development, resulting in misreading and high power consumption. In this regard, we theoretically investigate the Pt/Ti/NbO₂/Nb${}_2$O${}_{5-x}$/Pt-based self-selective memristor, which combines the inherent nonlinearity of the NbO₂ switching layer and the non-volatile operation of the Nb${}_2$O${}_{5-x}$ memory layer in a single device. The results show that the Pt/Ti/NbO₂/Nb${}_2$O${}_{5-x}$/Pt-based self-selective memristor offers the sneak current of 310 nA, selectivity of around 174, and on/off current ratio of 75, compared to the sneak current of approximately 70 $\mu$A, selectivity of about 4.02, and on/off current ratio of around 1.55 for the Pt/Ti/Nb${}_2$O${}_{5-x}$/Pt-based memristor device. Our self-selective memristor minimizes the sneak current, but a small on/off current ratio limits their readout margin and power efficiency for crossbar array size greater than 4KB. Further, we demonstrate that breaking down a large-scale crossbar array into smaller subarrays and separating them by transistor switches, called the split crossbar array, is a more efficient way of achieving a practical size crossbar array with improved readout margin and power efficiency. Our results shed light on the potential of the Pt/Ti/NbO₂/Nb${}_2$O${}_{5-x}$/Pt-based self-selective memristor and explore the split crossbar array architecture as a practical solution to augment readout margins and power efficiency in a large-scale crossbar array.

True random number generators (TRNGs) should ideally generate lengthy chains of non-repeating, uncorrelated bit-streams that are efficient in terms of both energy and area. Current TRNG designs include source of randomness such as CMOS or non-volatile memory based devices with additional circuitry to improve the quality of randomness leading to power and area overhead. This paper addresses these issues by improving the randomness of the Spin-Orbit Torque (SOT)-Magnetic Tunnel Junction cell. Motivated by the observation that free layer thickness of Magnetic Tunnel Junction (MTJ) can be scaled to design a low-barrier device, the paper proposes a novel source of randomness called $\Delta$SOT. This device is then used to design TRNG circuits that achieves high quality random telegraphic switching behavior without any additional circuitry making it suitable for ultra-low power applications. Evaluations show that $\Delta$SOT-TRNG has significant reduction in energy (51%) and area (66%) compared to state-of-the-art MTJ based TRNG design. Furthermore, the work shows that the improved switching speed of the reduced barrier junction can results in 65% increase in throughput compared to MTJ based TRNG design.