Memories - Materials, Devices, Circuits and Systems最新文献

In recent years, there has been significant progress in the development of high-$\kappa$ materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-$\kappa$ FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.

In this study, a floating-gate field-effect transistor (FGFET) structure is proposed and verified through simulations. Current memory devices often rely on the von Neumann architecture which suffers from von Neumann bottleneck. The proposed FGFET is not vulnerable to the von Neumann bottleneck because the memory cell and process unit do not function separately. FGFET is composed with Sensor FET(SFET) and Vertical FET(VFET), which can form a memory node with connection of each part. Moreover, the advantage of FGFET is that the conventional CMOS process can be used. In this regard, the developed FGFET using the existing CMOS process shows that the circuit size, power consumption, and operation delay are significantly reduced compared to a conventional logic circuit. Furthermore, various circuit simulations comprising the proposed FGFET, such as an inverter and NAND/NOR gate, are performed, highlighting the advantages of the proposed FGFET. This study lays the foundation for using a CMOS-based memory logic integrated device and architecture for alleviating the von Neumann bottleneck.

In the context of neuromorphic computing chip engineering, this review paper explores the area of bio-inspired artificial synapses with a focus on the incorporation of soft biomaterials. Soft biomaterials, including biocompatible hydrogels and organic polymers, have definite advantages in resembling the soft and dynamic properties of biological synapses. The article gives a general review of neuromorphic computing while emphasizing the shortcomings of traditional von Neumann architectures in terms of emulating the functions of the brain in computing. It highlights the artificial synaptic design concepts, including synaptic plasticity and energy efficiency. Spike-timing-dependent plasticity, synaptic weight modulation, and low-power operation can all be incorporated into these synapses thanks to the use of soft biomaterials. Inkjet printing, self-assembly methods, and electrochemical deposition are only a few of the technical techniques covered in this article for creating artificial synapses that are inspired by biological structures. These methods enable accurate biomaterial patterning and deposition, enabling the construction of complex neural networks on neuromorphic circuits. The research also emphasizes possible uses of bio-inspired artificial synapses in robotics, prosthetics, and cognitive computing. Soft biomaterials' capacity to mimic the synaptic activity of the brain creates new opportunities for effective and clever computing systems. In summary, this review paper succinctly outlines the incorporation of soft biomaterials into artificial synapses that are inspired by biological structures for neuromorphic computing chip fabrication. It analyzes production methods, highlights the value of synaptic plasticity and energy efficiency, and examines prospective applications. The development of new computing paradigms and the creation of extremely effective and brain-like computer systems are both significantly impacted by this research.

In particular, predicting the temperature and humidity information plays a crucial role in plantation, estimating rainfalls and climate change, and predicting air quality via specified geographical regions. The temperature and humidity forecasting information is occasionally presented with low accuracy due to uncertain techniques and vast methods that employ different sensors and models. For this reason, this work proposes an Internet of Things (IoT) temperature and humidity forecasting model based on an improved whale optimization algorithm with long short-term memory (IWOA-LSTM) technique. To increase the convergence speed processing time and overcome the local optimization problem, the IWOA is introduced. The number of hidden layers, learning rate momentum, and weight decay of the LSTM optimized using the IWOA. The actual temperature and humidity data are collected using DHT11 and ESP8266 NodeMCU practical model and processed using the ThingSpeak platform. The processing data stage depends on filling the missing data gaps using the rolling average technique (RAT). The performance evaluation of the proposed IWOA-LSTM forecasting model is assessed using some statistical functions, namely known as mean square error, mean absolute error, root mean square error, and mean absolute percentage error. The IWOA-LSTM techniques were also assessed using throughput, latency, and power consumption. The developed IWOA-LSTM model shows high accuracy, leading to better forecasting information than other forecasting models.

The melt quenching and thermal evaporation techniques were used to produce the chalcogenide glass Ge₁₈Bi₄Se₇₈ powder and thin film samples, respectively. The as-deposited and annealed thin films at (180, 200, 300, 320 °C) are characterized by X-ray diffractometer and scanning electron microscopy. The Urbach tail energy E_u and the optical energy gap E_op are investigated. As well, the Swanepoel method revealed that the refractive index exhibited normal dispersion behavior. In addition, the single oscillator, dispersion energies, the lattice dielectric constant, ${\epsilon }_L$, plasma frequency, ${\omega }_p$, and optical conductivity, ${\sigma }_{op}$ were all examined. The electrical conductivity and the activation energies for as-deposited and annealed thin films were calculated. Whereas the J-E properties of the as-deposited and annealed films indicated varied ranges of negative differential conductance NDC depending on the annealing temperatures.

This paper establishes a single Miller capacitor-based frequency compensation network for a three-stage amplifier. Nodal equations are solved symbolically and a linear transfer function is obtained. Poles and zeros formulations are extracted while circuit-level implementation is suggested and simulated using 0.18 μm CMOS technology. The compensation network shares the Miller capacitor at two negative loops simultaneously leading to improving frequency response. According to the simulation results, theoretical linear calculations are in acceptable agreement. The proposed amplifier shows 115 dB, 151 MHz, and 55 as DC gain, GBW, and PM respectively while consuming 320 μW as power dissipation.

In this paper, Junctionless Twin Gate Trench Channel (JL-TGTC) MOSFET with individual gate control is realized. The device gives full functionality of 2-input digital ‘AND’ and ‘NAND’ logics. The simulation depicts the results in the form of various parameters such as cutoff current, transfer characteristics, and potential profiles. All the simulations regarding device structure and functionality are done on TCAD. This new type of MOS device has improved applicability in low-voltage digital electronics such as sequential circuits etc.

In this article, a study of ZnO doping in poly-dimethyl-siloxane (PDMS) polymer, which is used as one tribo layer in tribo-electric energy harvesters (TEG) is corroborated to enhance the electrical properties, open circuit voltage (V_oc)and short circuit current (I_SC). A parallel plate device configuration of metal-to-dielectric approach is carried out making use of copper as metal and PDMS polymer with ZnO doping as a dielectric film. The double sided copper tape of 99.99 % purity and 60 μm thickness is used to realize the top tribo layer whiledielectric PDMS polymer film with ZnO doping of 8 wt%, 13 wt%, and 18 wt% is spin coated at 1000 rpm on single side copper coated FR4 substrate to make the bottom tribo-electic layer. The mechanical force is applied in tapping mode on top layer by Universal Testing Machine (UTM). The prototype device is characterized by Agilent DSO, which revealed peak output voltage of 15 V, 20 V, 30 V, and 41 V and peak-to-peak output voltage 38 V, 50 V, 60 V, and 69 V in pure PDMS, PDMS+8 % ZnO, PDMS+13 % ZnO, and PDMS+18 % ZnO respectively. The output peak current is obtained 9 nA, 20 nA, 30 nA, and 32 nA and peak-to-peak current 31 nA, 49 nA, 51 nA, and 60 nA respectively. The performance of ZnO doped PDMS TEG has increased adequately, up to 68.44 % Of V_oc and 71.87 % of I_sc.with respect to pure PDMS. A scanning electron microscope (SEM) is used to confirm polymer film morphology and ZnO doping percentage in PDMS is validatedby energy dispersive X-ray spectroscopy.

This paper suggests an analysis of SOI-based GaN FinFET that considers high-k gate oxide into account. The effect of using SOI substrate and a high-k dielectric layer on ON current, OFF current, electric field, electron mobility, conduction & valence band energy, and subthreshold swing is reported. All these parameters are analyzed and compared with bulk GaN FinFET and Si FinFET. We achieve better ON current, faster speed, and more minor subthreshold swing, reducing the short channel effects. A shallow OFF current is obtained because of bulk conduction in the GaN channel area, which the gate can deplete. Several RF/analog metrics are also noted, including transconductance (g_m), cut-off frequency (f_T), transconductance frequency product (TFP), and transconductance generation factor (TGF), and comparison with Bulk GaN FinFET and Si FinFET is presented. Finally, the linearity metrics like 2nd and 3rd-order voltage intercept points, IIP3, and 1-dB compression point is extracted. Compared to the other two structures, the suggested structure exhibits advantageous DC and RF/analog performances. A comparison of different Figures of Merits (FoMs) for the suggested device with previously published literature is also given.

The capabilities of artificial neural networks are rapidly evolving, so are the expectations for them to solve ever more challenging tasks in numerous everyday situations. Larger, more complex networks and the need to execute them efficiently on edge devices are the two counteracting requirements of this trend. Novel devices and computation techniques show promising characteristics to address this challenge. A huge design space covering different combinations of neural networks and hardware architectures using these technologies needs to be explored. An efficient design flow is, therefore, crucial for a good quality of service. This work reviews a wide range of simulation tools for novel memristive devices and analyzes their applicability for the design space exploration. A modular toolflow is proposed that shrinks down the large design space step-by-step using state-of-the-art optimization techniques and builds upon existing tools to find the best trade-offs between network accuracy and hardware requirements.