Memories - Materials, Devices, Circuits and Systems最新文献

This study investigates the influence of heavy ion irradiation on thin film transistors (TFTs) based on an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. Through the use of Technology Computer-Aided Design (TCAD) simulations, we analyze the impact on device performance. We examine the ambipolar device characteristics by varying the thickness of the active layer (Poly-Si) and studying the corresponding physics. Our results reveal that reducing the active layer thickness from 140 to 80 nm decreases the magnitude of the threshold voltage (|VT|) for both nMOS and pMOS operating voltages. Additionally, the subthreshold slope is reduced for both nMOS and pMOS as the active layer thickness is decreased from 140 to 80 nm.

Further, we investigated the transient response of the drain current to heavy ion irradiation in the sensitive regions across the Schottky barrier-based source and drain. We specifically analyze the phenomenon of bipolar amplification for various Linear Energy Transfer (LET) values, ranging from 0.1 MeV cm²/mg to 100 MeV cm²/mg. Our findings indicate that increasing the LET values from 0.1 MeV cm²/mg to 100 MeV cm²/mg results in amplified bipolar behavior and a drain current overshoot of over 10 % for both pMOS and nMOS operating voltages. To summarize, this work highlights the effects of heavy ion irradiation on TFTs with an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. The study explores the influence of active layer thickness on device characteristics and demonstrates the transient response of drain current under different LET values. These findings contribute to a better understanding of the behavior and performance of TFTs subjected to heavy ion irradiation.

Metal-air batteries (MABs) have emerged as a promising contender in the quest for alternative energy storage technologies, rivalling the widespread utilization of lithium-ion batteries (LIBs). Their comparable theoretical energy density to gasoline, reaching ∼12,000 Wh/kg, has sparked great interest. However, the practical implementation of MABs has been hindered by limitations associated with metal anodes, including volume expansion and unwanted side reactions. Surprisingly, the exploration of metalloid-air batteries (MLAB) remains largely unexplored. This comprehensive review aims to shed light on the potential of MLABs as a novel alternative battery technology. This technology employs metalloids in their elemental form or as compounds/alloys. Elemental metalloids, such as Silicon and Germanium, when used as anodes in combination with alkaline or Ionic liquid electrolytes, have showcased remarkable performance, surpassing their metallic counterparts in energy density, corrosiveness, and discharge time, among other critical factors. Moreover, this review delves into the discussion of Borides and Silicides, compounds of elemental Boron and Silicon, respectively, as anode materials for air batteries. Furthermore, diverse metalloid composites and computational studies exploring innovative configurations have also been examined and discussed, paving the way for future advancements in MLABs.

In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V. The first stage of the circuit utilizes a supper recycling folded cascode design, while the second stage employs a simple cascode amplifier. Additionally, we have utilized a small 1 pF Miller capacitor to stabilize the amplifier response. Based on simulation results, the proposed amplifier demonstrates a DC gain of 110 dB, GBW of 15 MHz, and power consumption of 359 μW. Finally, we conducted Monte Carlo simulations to verify the robustness of the proposed circuit against the process, temperature, supply voltage, and device dimension mismatch variations.

Various charged particles in space, including alpha particles, neutrons, heavy ions, and photons, pose reliability and stability concerns for memory circuits. These particles also create an ion track in the memory chip, disrupting the storage bit. The standard 6T SRAM is particularly susceptible to these disturbances. Several researchers suggest employing radiation-hardened SRAM cells to solve this problem. Most studies examine the inclusion of redundant nodes in the memory cell to recover the lost bit. This paper shows a new SEUH-12T SRAM memory cell with redundant nodes to deal with the soft error problem. The proposed SEUH-12T memory cell performance is compared to that of reliable radiation-hardened memory cells such as Quatro-10T, We-Quatro-12T, QCCS-12T, STS-10T, RHMC-12T, and RHWC-12T. The proposed SEUH-12T cell protects against single and multiple node disruptions by considering minimum sensitive nodes layout area separation concept. Furthermore, proposed SEUH-12T exhibits 8.5$\times$/ 6.3$\times$/ 5.6$\times$/ 1.4$\times$/ 1.2$\times$/ 1.4$\times$/ 1.04$\times$ times greater read stability than existing 6T-SRAM/ Quatro-10T/ We-Quatro-12T/ QCCS-12T/ STS-10T/ RHMC-12T/ RHWC-12T memory cells.

This article introduces a novel design of a simulator for grounded lossless negative inductance by using an active element -single Operational Trans Resistance Amplifier (OTRA) and four passive components. Without interrupting the condition of realization of inductance, the value of the simulated inductance can be independently administered by a MOS based resistor. For validation of the analytical elucidation PSPICE simulation results are used. Moreover, sensitivity analysis, Monte-Carlo simulation, temperature analysis, and % of total harmonic distortion (%THD) are also investigated to verify the functionality of the proposed circuit. As an application claim of the projected configuration, an inductance nullification circuit is also implemented that exposes that the proposed negative inductance simulator may be used to cancel or reduce the effective inductance in a circuit. The Analog Design Environment tool of Cadence Virtuoso is employed for designing the layout of the OTRA.

In recent years, there has been significant progress in the development of high-$\kappa$ materials in the semiconductor industry. Given that the contact between the channel and the electrode has a crucial impact on reliability, the selection of electrode materials and their deposition technology is an area that requires extensive research. Additionally, interface trap density has long played a critical role in determining the reliability of field-effect transistors (FETs). Therefore, this paper presents the results of interface trap density in high-$\kappa$ FETs obtained using 2-level and 3-level charge pumping methods. Measurements were conducted on a 10 nm oxide thickness n-doped silicon substrate using native k materials such as silicon and zirconium-doped hafnium oxide. The results demonstrate that chlorine-based HfO2 oxide with zirconium doping exhibits the lowest interface defects.

In this study, a floating-gate field-effect transistor (FGFET) structure is proposed and verified through simulations. Current memory devices often rely on the von Neumann architecture which suffers from von Neumann bottleneck. The proposed FGFET is not vulnerable to the von Neumann bottleneck because the memory cell and process unit do not function separately. FGFET is composed with Sensor FET(SFET) and Vertical FET(VFET), which can form a memory node with connection of each part. Moreover, the advantage of FGFET is that the conventional CMOS process can be used. In this regard, the developed FGFET using the existing CMOS process shows that the circuit size, power consumption, and operation delay are significantly reduced compared to a conventional logic circuit. Furthermore, various circuit simulations comprising the proposed FGFET, such as an inverter and NAND/NOR gate, are performed, highlighting the advantages of the proposed FGFET. This study lays the foundation for using a CMOS-based memory logic integrated device and architecture for alleviating the von Neumann bottleneck.

In the context of neuromorphic computing chip engineering, this review paper explores the area of bio-inspired artificial synapses with a focus on the incorporation of soft biomaterials. Soft biomaterials, including biocompatible hydrogels and organic polymers, have definite advantages in resembling the soft and dynamic properties of biological synapses. The article gives a general review of neuromorphic computing while emphasizing the shortcomings of traditional von Neumann architectures in terms of emulating the functions of the brain in computing. It highlights the artificial synaptic design concepts, including synaptic plasticity and energy efficiency. Spike-timing-dependent plasticity, synaptic weight modulation, and low-power operation can all be incorporated into these synapses thanks to the use of soft biomaterials. Inkjet printing, self-assembly methods, and electrochemical deposition are only a few of the technical techniques covered in this article for creating artificial synapses that are inspired by biological structures. These methods enable accurate biomaterial patterning and deposition, enabling the construction of complex neural networks on neuromorphic circuits. The research also emphasizes possible uses of bio-inspired artificial synapses in robotics, prosthetics, and cognitive computing. Soft biomaterials' capacity to mimic the synaptic activity of the brain creates new opportunities for effective and clever computing systems. In summary, this review paper succinctly outlines the incorporation of soft biomaterials into artificial synapses that are inspired by biological structures for neuromorphic computing chip fabrication. It analyzes production methods, highlights the value of synaptic plasticity and energy efficiency, and examines prospective applications. The development of new computing paradigms and the creation of extremely effective and brain-like computer systems are both significantly impacted by this research.

In particular, predicting the temperature and humidity information plays a crucial role in plantation, estimating rainfalls and climate change, and predicting air quality via specified geographical regions. The temperature and humidity forecasting information is occasionally presented with low accuracy due to uncertain techniques and vast methods that employ different sensors and models. For this reason, this work proposes an Internet of Things (IoT) temperature and humidity forecasting model based on an improved whale optimization algorithm with long short-term memory (IWOA-LSTM) technique. To increase the convergence speed processing time and overcome the local optimization problem, the IWOA is introduced. The number of hidden layers, learning rate momentum, and weight decay of the LSTM optimized using the IWOA. The actual temperature and humidity data are collected using DHT11 and ESP8266 NodeMCU practical model and processed using the ThingSpeak platform. The processing data stage depends on filling the missing data gaps using the rolling average technique (RAT). The performance evaluation of the proposed IWOA-LSTM forecasting model is assessed using some statistical functions, namely known as mean square error, mean absolute error, root mean square error, and mean absolute percentage error. The IWOA-LSTM techniques were also assessed using throughput, latency, and power consumption. The developed IWOA-LSTM model shows high accuracy, leading to better forecasting information than other forecasting models.

The melt quenching and thermal evaporation techniques were used to produce the chalcogenide glass Ge₁₈Bi₄Se₇₈ powder and thin film samples, respectively. The as-deposited and annealed thin films at (180, 200, 300, 320 °C) are characterized by X-ray diffractometer and scanning electron microscopy. The Urbach tail energy E_u and the optical energy gap E_op are investigated. As well, the Swanepoel method revealed that the refractive index exhibited normal dispersion behavior. In addition, the single oscillator, dispersion energies, the lattice dielectric constant, ${\epsilon }_L$, plasma frequency, ${\omega }_p$, and optical conductivity, ${\sigma }_{op}$ were all examined. The electrical conductivity and the activation energies for as-deposited and annealed thin films were calculated. Whereas the J-E properties of the as-deposited and annealed films indicated varied ranges of negative differential conductance NDC depending on the annealing temperatures.