Pub Date : 1988-04-12DOI: 10.1109/RELPHY.1988.23419
C. Duvvury, R. Rountree, O. Adams
V/sub DD/-V/sub SS/ protection design considerations to meet MIL-STD requirements are discussed. Internal chip electrostatic-discharge (ESD) damage due to direct stress applied between V/sub DD/ and V/sub SS/ pins is illustrated, and possible solutions are discussed. It is shown that induced current paths can exist when outputs/inputs are stressed with respect to V/sub DD/ or V/sub SS/ stress, and if the internal layout is not carefully considered, the overall protection level can degrade. An unusual internal ESD phenomenon that was observed for I/O pins stressed with respect to V/sub DD/ is reported. The results show that there exists a window of threshold voltages where the I/O protection is not effective due to interaction with the internal chip layout.<>
{"title":"Internal chip ESD phenomena beyond the protection circuit","authors":"C. Duvvury, R. Rountree, O. Adams","doi":"10.1109/RELPHY.1988.23419","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23419","url":null,"abstract":"V/sub DD/-V/sub SS/ protection design considerations to meet MIL-STD requirements are discussed. Internal chip electrostatic-discharge (ESD) damage due to direct stress applied between V/sub DD/ and V/sub SS/ pins is illustrated, and possible solutions are discussed. It is shown that induced current paths can exist when outputs/inputs are stressed with respect to V/sub DD/ or V/sub SS/ stress, and if the internal layout is not carefully considered, the overall protection level can degrade. An unusual internal ESD phenomenon that was observed for I/O pins stressed with respect to V/sub DD/ is reported. The results show that there exists a window of threshold voltages where the I/O protection is not effective due to interaction with the internal chip layout.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116506127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-12DOI: 10.1109/RELPHY.1988.23433
W. Anderson, A. Christou, F. Buot, J. Archer, G. Bechtel, H. Cooke, Y. Pao, M. Simons, E. Chase
Experimental and theoretical results of a reliability study of GaAs/AlGaAs MODFETs are presented and show a commonality of degradation modes under various accelerated stress conditions. The reliability of submicron-gate low-noise MODFETs was evaluated using high-temperature storage and DC operating life tests; significantly greater drain current degradation that occurred under DC bias is related to a field-assisted channel doping mechanism. Under pulsed electron irradiation long-term drain current transients were observed as well as persistent photoconductivity in some devices. Electrostatic-discharge experiments revealed that, unlike standard FETs, human body model (HBM) stressing of MODFETs results in loss of drain current, indicating deconfinement of the two-dimensional electron gas. The unified model of MODFET degradation is therefore related to field-assisted migration of alloy constituents and doping species.<>
{"title":"Reliability of discrete MODFETs: life testing, radiation effects, and ESD","authors":"W. Anderson, A. Christou, F. Buot, J. Archer, G. Bechtel, H. Cooke, Y. Pao, M. Simons, E. Chase","doi":"10.1109/RELPHY.1988.23433","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23433","url":null,"abstract":"Experimental and theoretical results of a reliability study of GaAs/AlGaAs MODFETs are presented and show a commonality of degradation modes under various accelerated stress conditions. The reliability of submicron-gate low-noise MODFETs was evaluated using high-temperature storage and DC operating life tests; significantly greater drain current degradation that occurred under DC bias is related to a field-assisted channel doping mechanism. Under pulsed electron irradiation long-term drain current transients were observed as well as persistent photoconductivity in some devices. Electrostatic-discharge experiments revealed that, unlike standard FETs, human body model (HBM) stressing of MODFETs results in loss of drain current, indicating deconfinement of the two-dimensional electron gas. The unified model of MODFET degradation is therefore related to field-assisted migration of alloy constituents and doping species.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122043768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-12DOI: 10.1109/RELPHY.1988.23455
E. Umemura, H. Onoda, S. Madokoro
Rapid thermal annealing technology has been applied to the sintering process for Al-Si alloy. Contact resistance was kept low by this technique, and low contact resistance was maintained even after postsintering heat treatment. The relationship between contact resistance and the number of Si nodules has been investigated. Si nodules and the Si at contact holes are considered to be precipitation nuclei for dissolved Si in Al-Si alloy. Precipitating Si is shared by Si nodules and contact holes after heat treatment. This model explains contact resistance change during heat treatments.<>
{"title":"High reliable Al-Si alloy/Si contacts by rapid thermal sintering","authors":"E. Umemura, H. Onoda, S. Madokoro","doi":"10.1109/RELPHY.1988.23455","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23455","url":null,"abstract":"Rapid thermal annealing technology has been applied to the sintering process for Al-Si alloy. Contact resistance was kept low by this technique, and low contact resistance was maintained even after postsintering heat treatment. The relationship between contact resistance and the number of Si nodules has been investigated. Si nodules and the Si at contact holes are considered to be precipitation nuclei for dissolved Si in Al-Si alloy. Precipitating Si is shared by Si nodules and contact holes after heat treatment. This model explains contact resistance change during heat treatments.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132337752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-12DOI: 10.1109/RELPHY.1988.23421
K. Cham, H. Fu, Y. Nishi
The hot carrier degradation of submicron n-channel FETs is characterized for various gate and drain pulse waveforms. The results are consistent with interface electron traps generated by hot holes. The results showed that inverters with small loads can degrade faster than inverters with large loads, due to AC degradation effects. Device lifetime in circuits cannot in general be projected by DC data. The AC effect was also found to be dependent on device structure.<>
{"title":"The dependence of hot carrier degradation on AC stress waveforms","authors":"K. Cham, H. Fu, Y. Nishi","doi":"10.1109/RELPHY.1988.23421","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23421","url":null,"abstract":"The hot carrier degradation of submicron n-channel FETs is characterized for various gate and drain pulse waveforms. The results are consistent with interface electron traps generated by hot holes. The results showed that inverters with small loads can degrade faster than inverters with large loads, due to AC degradation effects. Device lifetime in circuits cannot in general be projected by DC data. The AC effect was also found to be dependent on device structure.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"68 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125378924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-12DOI: 10.1109/RELPHY.1988.23437
A. Dallmann, D. Bollmann, G. Menzel
The EBIC/TCM (electron beam induced current/tunneling current microscopy) method was applied to gate oxide structures. Oxide defects could be localized exactly for further analyses by scanning or transmission electron microscopy. Passivated structures and trench capacitors were investigated. Semiautomatic measurements were carried out in order to obtain statistical results. In the case of degraded gate oxide before destructive breakdown, TCM was used. The best results were achieved in the depletion range. A lateral solution of about 200 nm and a step-resolution of 2 nm were attained. To avoid further radiation damage by the electron beam, laser-activated TCM was used. Both methods yielded comparable results.<>
{"title":"Investigation of the EBIC/TCM-method and application to VLSI-structures","authors":"A. Dallmann, D. Bollmann, G. Menzel","doi":"10.1109/RELPHY.1988.23437","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23437","url":null,"abstract":"The EBIC/TCM (electron beam induced current/tunneling current microscopy) method was applied to gate oxide structures. Oxide defects could be localized exactly for further analyses by scanning or transmission electron microscopy. Passivated structures and trench capacitors were investigated. Semiautomatic measurements were carried out in order to obtain statistical results. In the case of degraded gate oxide before destructive breakdown, TCM was used. The best results were achieved in the depletion range. A lateral solution of about 200 nm and a step-resolution of 2 nm were attained. To avoid further radiation damage by the electron beam, laser-activated TCM was used. Both methods yielded comparable results.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128827728","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1988-04-12DOI: 10.1109/RELPHY.1988.23441
S. Murakami, T. Kagami, Y. Sugawara
Stability of secondary passivation layers as RF plasma sputtered SiO/sub 2/ (Sp-SiO/sub 2/), P-SiO/sub 2/, and P-SiN in high-voltage integrated circuits under bias-temperature (BT) stress aging was investigated by using an MIS diode and a lateral pnpn thyristor. It was shown that the initial electrical properties were almost the same for each passivation layer system. However, variations in net number of charges by +or-BT stress aging were observed owing to different charge storage mechanisms, such as residual charges, interface trapped charges, and polarized charges. These instabilities are discussed in conjunction with variations in the device blocking characteristics.<>
{"title":"Investigation of instability in multi-layer dielectric structures","authors":"S. Murakami, T. Kagami, Y. Sugawara","doi":"10.1109/RELPHY.1988.23441","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23441","url":null,"abstract":"Stability of secondary passivation layers as RF plasma sputtered SiO/sub 2/ (Sp-SiO/sub 2/), P-SiO/sub 2/, and P-SiN in high-voltage integrated circuits under bias-temperature (BT) stress aging was investigated by using an MIS diode and a lateral pnpn thyristor. It was shown that the initial electrical properties were almost the same for each passivation layer system. However, variations in net number of charges by +or-BT stress aging were observed owing to different charge storage mechanisms, such as residual charges, interface trapped charges, and polarized charges. These instabilities are discussed in conjunction with variations in the device blocking characteristics.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133177171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1988.23420
A. Chatterjee, S. Aur, T. Niuya, P. Yang, J. Seitchik
The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is considered. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multigate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward-biases the source junctions causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures can occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed.<>
{"title":"Failure in CMOS circuits induced by hot carriers in multi-gate transistors","authors":"A. Chatterjee, S. Aur, T. Niuya, P. Yang, J. Seitchik","doi":"10.1109/RELPHY.1988.23420","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.23420","url":null,"abstract":"The problem of vertical isolation in circuits fabricated using shallow n-well epitaxial CMOS technology is considered. Unexpectedly high substrate current resulting in circuit failure has been observed during accelerated reliability tests. The substrate current is a result of enhanced hole injection from multigate p-channel transistors with interdigitated source and drain. The electron current generated from impact ionization near the drain forward-biases the source junctions causing hole injection to the substrate. The current is sensitive to the supply voltage and temperature. Consequently, unanticipated failures can occur at the high voltages and temperatures encountered during burn-in. Design and process solutions are discussed.<<ETX>>","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115809578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/RELPHY.1988.917817
E. Uemura, H. Onoda, S. Madokoro
As device size reduces, the Si in A1-Si alloy In conclusion, rapid thermal annealing technology causes serious problems on reliability. One of them is has been applied for sintering process. Low contact contact resistance increase due to Si precipitation at resistance has been maintained even afcer postcontact holes. It is difficult to solve this problem sintering heat treatments. A d e l t'mt explains chis by conventional furnace annealing process and a new effect with nmber of Si nodules was proposed. It is annealing technology is desired. Rapid thermal clarified that RTS is an effective technique for annealing technology has been applied for sintering metallization process. process (Rapid Thermal Sintering : RTS) and high reliable contact characteristics has been obtained. Contact resistance measurement samples were prepared using conventional VLSI fabrication processes. Surface carrier concentration for n+ Si and pt Si were 3~1O~~cm-3 and 2x1OZ0 cm-! respectively. Al-lYSi was used for metallization material. Contact resistance for lw@ contacts was measured by Kelvin's pattern. Samples for Si nodule observation were prepared as follows. BPSG film ( 3 O h ) was deposited on 6-inch Si(100) wafers. Al-lYSi ( 7 O O m ) was deposited by mgnetron sputtering method. After heat treatments, Si was delineated by phosphorus acid and Si nodules were observed by scanning electron microscope. In both evaluation, heat treatments were carried out by furnace or rapid thermal annealing equipnent. Furthemre, additional annealing considering post-sintering heat treatments were performed by furnace. Contact resistance of furnace-sintered (FS) samples increases with post-sintering heat treatment. On the other hand, RTS samples has no increase on contact resistance. In order to analyze this result, relationship between contact resistance and the nmber of Si nodules has been investigated. The nmber of Si nodules can be controlled easily by RTS. Si nodules formed by RTS is larger in nmber than those f o m d by FS. Si nodules formed by FS and WS has a drastic difference in nmber. Its tendency is kept even after post anneal. This phenomenon can be explained by the theory of classical homogeneous nucleation considering heat treatment time. Contact resistance is kept low in the region where the nmber of Si nodules is large. While, as the nmber of Si nodules decreases, contact resistance increases drastically. In order to explain this result, we propose a d e l here. The Si contained in A1-Si alloy continues dissolving and precipitating during heat treatments. The dissolved Si in A1-Si' precipitates to nuclei after heat treatment. Si nodules and the Si at contact holes are considered to be nuclei for precipitating Si. After all, the dissolved Si are shared by these nuclei. When the number of Si nodules existed around a contact hole is large, the amount of Si precipitated at the contact hole is small and the contact resistance is kept small. On the other hand, contact resis
随着器件尺寸的减小，A1-Si合金中的Si含量逐渐降低，因此，快速热退火技术在可靠性方面存在严重问题。其中一种已应用于烧结工艺。低接触接触电阻增加是由于硅在电阻处的沉淀，即使在接触孔后也保持不变。烧结热处理很难解决这一问题。本文用传统的炉内退火工艺解释了这一现象，并提出了一种与硅球数有关的新效应。这是退火技术所需要的。快速热澄清RTS是一种有效的技术，退火技术已应用于烧结金属化工艺。快速热烧结(RTS)工艺，获得了高可靠的接触特性。采用传统的VLSI制造工艺制备了接触电阻测量样品。n+ Si和pt Si的表面载流子浓度分别为3~ 10o ~~cm-3和2x10oz0 cm-3 !分别。Al-lYSi被用作金属化材料。lw@触点的接触电阻采用开尔文模式测量。硅结节观察样品的制备方法如下。BPSG薄膜(30h)沉积在6英寸Si(100)晶圆上。采用磁控溅射法制备了7 O O m的Al-lYSi。热处理后，磷酸对Si进行圈定，扫描电镜观察到Si结节。在这两个评价中，热处理都是通过炉或快速热退火设备进行的。此外，考虑到烧结后的热处理，在炉内进行了额外的退火。随着烧结后热处理，炉烧结试样的接触电阻增大。另一方面，RTS样品的接触电阻没有增加。为了分析这一结果，研究了接触电阻与硅结节数之间的关系。通过RTS可以很容易地控制Si结核的数量。RTS形成的Si结节数量大于FS形成的Si结节数量。FS和WS形成的Si结节在数量上有显著差异。即使经过后退火，其趋势仍保持不变。这种现象可以用考虑热处理时间的经典均形核理论来解释。在硅结节较多的区域，接触电阻保持较低。而随着硅结节数量的减少，接触电阻急剧增加。为了解释这一结果，我们在这里提出了一个方程。在热处理过程中，A1-Si合金中的Si继续溶解析出。热处理后，A1-Si中溶解的Si析出成核。硅结节和接触孔处的硅被认为是析出硅的核。毕竟，溶解的Si是由这些原子核共享的。当接触孔周围存在的Si结节数量较多时，接触孔处析出的Si量较少，接触电阻保持较小。另一方面，当接触孔周围存在的Si结节的n m k r较小时，接触电阻增大。RTS通过增加硅结节的数量来实现低接触电阻。
{"title":"High reliable Al-Si alloy/Si contacts by rapid thermal sintering","authors":"E. Uemura, H. Onoda, S. Madokoro","doi":"10.1109/RELPHY.1988.917817","DOIUrl":"https://doi.org/10.1109/RELPHY.1988.917817","url":null,"abstract":"As device size reduces, the Si in A1-Si alloy In conclusion, rapid thermal annealing technology causes serious problems on reliability. One of them is has been applied for sintering process. Low contact contact resistance increase due to Si precipitation at resistance has been maintained even afcer postcontact holes. It is difficult to solve this problem sintering heat treatments. A d e l t'mt explains chis by conventional furnace annealing process and a new effect with nmber of Si nodules was proposed. It is annealing technology is desired. Rapid thermal clarified that RTS is an effective technique for annealing technology has been applied for sintering metallization process. process (Rapid Thermal Sintering : RTS) and high reliable contact characteristics has been obtained. Contact resistance measurement samples were prepared using conventional VLSI fabrication processes. Surface carrier concentration for n+ Si and pt Si were 3~1O~~cm-3 and 2x1OZ0 cm-! respectively. Al-lYSi was used for metallization material. Contact resistance for lw@ contacts was measured by Kelvin's pattern. Samples for Si nodule observation were prepared as follows. BPSG film ( 3 O h ) was deposited on 6-inch Si(100) wafers. Al-lYSi ( 7 O O m ) was deposited by mgnetron sputtering method. After heat treatments, Si was delineated by phosphorus acid and Si nodules were observed by scanning electron microscope. In both evaluation, heat treatments were carried out by furnace or rapid thermal annealing equipnent. Furthemre, additional annealing considering post-sintering heat treatments were performed by furnace. Contact resistance of furnace-sintered (FS) samples increases with post-sintering heat treatment. On the other hand, RTS samples has no increase on contact resistance. In order to analyze this result, relationship between contact resistance and the nmber of Si nodules has been investigated. The nmber of Si nodules can be controlled easily by RTS. Si nodules formed by RTS is larger in nmber than those f o m d by FS. Si nodules formed by FS and WS has a drastic difference in nmber. Its tendency is kept even after post anneal. This phenomenon can be explained by the theory of classical homogeneous nucleation considering heat treatment time. Contact resistance is kept low in the region where the nmber of Si nodules is large. While, as the nmber of Si nodules decreases, contact resistance increases drastically. In order to explain this result, we propose a d e l here. The Si contained in A1-Si alloy continues dissolving and precipitating during heat treatments. The dissolved Si in A1-Si' precipitates to nuclei after heat treatment. Si nodules and the Si at contact holes are considered to be nuclei for precipitating Si. After all, the dissolved Si are shared by these nuclei. When the number of Si nodules existed around a contact hole is large, the amount of Si precipitated at the contact hole is small and the contact resistance is kept small. On the other hand, contact resis","PeriodicalId":102187,"journal":{"name":"26th Annual Proceedings Reliability Physics Symposium 1988","volume":"6 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129194731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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