Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119751
K. Muehlbauer, D. Gerling
In common applications electric drives mostly do not operate at full but at partial load. Concerning the energy efficiency of the electric drive not the maximum efficiency is essential but the efficiency at low load is relevant. In this paper a new method is presented which improves the efficiency of the power electronics of an electric drive at partial load. The method is based on a variation of the active transistor area. In case of an electric vehicle a power losses reduction of about 15% can be reached just in the power electronics in the driving cycle ARTEMIS ROAD.
{"title":"Improvement of energy efficiency in power electronics at partial load","authors":"K. Muehlbauer, D. Gerling","doi":"10.1109/IECON.2011.6119751","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119751","url":null,"abstract":"In common applications electric drives mostly do not operate at full but at partial load. Concerning the energy efficiency of the electric drive not the maximum efficiency is essential but the efficiency at low load is relevant. In this paper a new method is presented which improves the efficiency of the power electronics of an electric drive at partial load. The method is based on a variation of the active transistor area. In case of an electric vehicle a power losses reduction of about 15% can be reached just in the power electronics in the driving cycle ARTEMIS ROAD.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132382667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119619
H. de Sa, L. Morais, P. Donoso-Garcia, S. I. Seleme, P. Cortizo
The present paper deals with the study of the harmonic injection technique, with the objective of avoiding acoustics resonance, in high-pressure sodium lamps (HPS) of 70 W, when supplied by electronic ballast. A prototype of a three level full bridge PWM electronic ballast was developed which allows the injection of harmonics in the voltage supplied to the 70 W HPS lamp. The design procedure and results of the inverter used in ballast are then presented. The dimensioning of the resonant circuit for the lamp ignition, based on the voltage beating technique is made. These techniques allow the control of the current crest factor other than rejecting the AR.
本文研究了70w高压钠灯(HPS)在电子镇流器供电时的谐波注入技术，以避免声学谐振。开发了一种三电平全桥PWM电子镇流器的原型，该镇流器允许在70 W HPS灯的电压中注入谐波。然后介绍了用于镇流器的逆变器的设计过程和结果。基于电压跳动技术，确定了灯管点火谐振电路的尺寸。这些技术允许控制电流波峰因子而不是抑制AR。
{"title":"Harmonic current injection to avoid acoustic resonance in 70W HPS lamps","authors":"H. de Sa, L. Morais, P. Donoso-Garcia, S. I. Seleme, P. Cortizo","doi":"10.1109/IECON.2011.6119619","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119619","url":null,"abstract":"The present paper deals with the study of the harmonic injection technique, with the objective of avoiding acoustics resonance, in high-pressure sodium lamps (HPS) of 70 W, when supplied by electronic ballast. A prototype of a three level full bridge PWM electronic ballast was developed which allows the injection of harmonics in the voltage supplied to the 70 W HPS lamp. The design procedure and results of the inverter used in ballast are then presented. The dimensioning of the resonant circuit for the lamp ignition, based on the voltage beating technique is made. These techniques allow the control of the current crest factor other than rejecting the AR.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129979876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119780
M. F. da Silva, J. Fraytag, M. E. Schlittler, N. B. Chagas, T. Marchesan, M. D. Dalla Costa, Á. Seidel, J. M. Alonso, R. D. do Prado
In this paper a methodological study of an electronic ballast including design and development issues is presented. The ballast is intended to feed a 100 W electrodeless fluorescent lamp at 250 kHz. The proposed topology consists of a buck-boost converter, as power factor correction (PFC) stage, integrated with a resonant half-bridge inverter, used as lamp power control (PC) stage. The integration of both stages is proposed, in this work, in order to reduce the number of active switches, as well as to simplify the required driving and control circuitry for this application. The implemented topology achieved a high power factor (0.994) and a line current total harmonic distortion (THD) of 8.016%, while the measured efficiency was 85%.
{"title":"Analysis and design of a high-power-factor single-stage buck-boost half-bridge electronic ballast for electrodeless fluorescent lamps","authors":"M. F. da Silva, J. Fraytag, M. E. Schlittler, N. B. Chagas, T. Marchesan, M. D. Dalla Costa, Á. Seidel, J. M. Alonso, R. D. do Prado","doi":"10.1109/IECON.2011.6119780","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119780","url":null,"abstract":"In this paper a methodological study of an electronic ballast including design and development issues is presented. The ballast is intended to feed a 100 W electrodeless fluorescent lamp at 250 kHz. The proposed topology consists of a buck-boost converter, as power factor correction (PFC) stage, integrated with a resonant half-bridge inverter, used as lamp power control (PC) stage. The integration of both stages is proposed, in this work, in order to reduce the number of active switches, as well as to simplify the required driving and control circuitry for this application. The implemented topology achieved a high power factor (0.994) and a line current total harmonic distortion (THD) of 8.016%, while the measured efficiency was 85%.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134232959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119472
Sungjoon Cho, Kwanghwan Lee, M. Jeong, Jiyoon Yoo
This paper proposed a synchronous PWM method of parallel AC-DC converters. The parallel AC-DC converters of traction control system for high speed train require accurate PLL (Phase-Locked Logic) method and synchronous PWM algorithm with phase delay control to implement unit power factor and input current harmonic reduction. The phase delay control of parallel converters driven by individual controllers is difficult. The proposed hybrid PLL algorithm detects the input voltage phase angle more accurately and improves the performance of phase delay control. The hybrid PLL algorithm consists of two kinds of method which calculate simultaneously the phase angle of input voltage. The single-phase AC-DC converters are connected in parallel through main transformer. The first PLL algorithm calculates the phase angle of primary input voltage adopting the digital APF (All-Pass Filter) and it has robust characteristics against the disturbance of input signal compared with conventional zero-crossing detection method by hardware circuit. The estimated phase angle of this algorithm is used for unit power factor control and instantaneous input current control. The second PLL algorithm generates the common reference signal for synchronous PWM by measuring the amplitude of input voltage at the near zero-crossing point. This paper describes the implementation of hybrid PLL algorithm adopting two different kinds of PLL method in detail. The feasibility of this algorithm is proven by experimental study on parallel converters (1.25MW×4) for high speed train.
{"title":"A synchronous PWM method of parallel AC-DC converters using hybrid-PLL algorithm","authors":"Sungjoon Cho, Kwanghwan Lee, M. Jeong, Jiyoon Yoo","doi":"10.1109/IECON.2011.6119472","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119472","url":null,"abstract":"This paper proposed a synchronous PWM method of parallel AC-DC converters. The parallel AC-DC converters of traction control system for high speed train require accurate PLL (Phase-Locked Logic) method and synchronous PWM algorithm with phase delay control to implement unit power factor and input current harmonic reduction. The phase delay control of parallel converters driven by individual controllers is difficult. The proposed hybrid PLL algorithm detects the input voltage phase angle more accurately and improves the performance of phase delay control. The hybrid PLL algorithm consists of two kinds of method which calculate simultaneously the phase angle of input voltage. The single-phase AC-DC converters are connected in parallel through main transformer. The first PLL algorithm calculates the phase angle of primary input voltage adopting the digital APF (All-Pass Filter) and it has robust characteristics against the disturbance of input signal compared with conventional zero-crossing detection method by hardware circuit. The estimated phase angle of this algorithm is used for unit power factor control and instantaneous input current control. The second PLL algorithm generates the common reference signal for synchronous PWM by measuring the amplitude of input voltage at the near zero-crossing point. This paper describes the implementation of hybrid PLL algorithm adopting two different kinds of PLL method in detail. The feasibility of this algorithm is proven by experimental study on parallel converters (1.25MW×4) for high speed train.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131471030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119853
J. Schellekens, J. Duarte, H. Huisman, M. Hendrix
Switch blanking time, also referred to as dead-time, is one of the dominant sources of output current and voltage distortion in pulse width modulated amplifiers. Extensive studies are known on elimination, minimization, and compensation of the effect. Most techniques achieve a reduction but are not capable of completely removing it. This paper demonstrates that it is possible to fully eliminate dead-time effects by applying the socalled opposed current converter topology in combination with advanced feedforward techniques. The zero-crossing behavior of the opposed current converter is analyzed and compared to a conventional full-bridge converter with equivalently filtered output. Simulations and measurements on a full-bridge and an opposed current converter of 1.5 kW are included to demonstrate the effectiveness of the proposed ideas for high-precision applications.
{"title":"Elimination of zero-crossing distortion for high-precision amplifiers","authors":"J. Schellekens, J. Duarte, H. Huisman, M. Hendrix","doi":"10.1109/IECON.2011.6119853","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119853","url":null,"abstract":"Switch blanking time, also referred to as dead-time, is one of the dominant sources of output current and voltage distortion in pulse width modulated amplifiers. Extensive studies are known on elimination, minimization, and compensation of the effect. Most techniques achieve a reduction but are not capable of completely removing it. This paper demonstrates that it is possible to fully eliminate dead-time effects by applying the socalled opposed current converter topology in combination with advanced feedforward techniques. The zero-crossing behavior of the opposed current converter is analyzed and compared to a conventional full-bridge converter with equivalently filtered output. Simulations and measurements on a full-bridge and an opposed current converter of 1.5 kW are included to demonstrate the effectiveness of the proposed ideas for high-precision applications.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119757
Ó. Jiménez, L. A. Barragan, I. Urriza, Óscar Lucía, D. Navarro, J. I. Artigas
This paper presents a field programmable gate array (FPGA) implementation of a digital circuit that measures in real-time the first harmonic load impedance of medium-frequency (25 kHz – 75 kHz) induction-heating cooking appliances. The load impedance of these systems, which consist of a planar inductor coupled to a pan, depends on the pan material, temperature, and frequency. For this reason, real-time load measurement is desirable for a proper control of the inverter. For computing this impedance, a dual-phase lock-in algorithm is applied to the inverter output voltage and load current. The algorithm has been implemented using a hardware description language (HDL). The implemented circuit is simulated by means of mixed-signal simulation tool. From these simulations, the accuracy of the method is evaluated. Finally, the simulations are experimentally verified.
{"title":"FPGA-based real-time harmonic impedance measurement of series resonant loads by using lock-in algorithm","authors":"Ó. Jiménez, L. A. Barragan, I. Urriza, Óscar Lucía, D. Navarro, J. I. Artigas","doi":"10.1109/IECON.2011.6119757","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119757","url":null,"abstract":"This paper presents a field programmable gate array (FPGA) implementation of a digital circuit that measures in real-time the first harmonic load impedance of medium-frequency (25 kHz – 75 kHz) induction-heating cooking appliances. The load impedance of these systems, which consist of a planar inductor coupled to a pan, depends on the pan material, temperature, and frequency. For this reason, real-time load measurement is desirable for a proper control of the inverter. For computing this impedance, a dual-phase lock-in algorithm is applied to the inverter output voltage and load current. The algorithm has been implemented using a hardware description language (HDL). The implemented circuit is simulated by means of mixed-signal simulation tool. From these simulations, the accuracy of the method is evaluated. Finally, the simulations are experimentally verified.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132623685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119971
M. Pastre, M. Kayal, H. Schmid, P. Zwahlen, Yufeng Dong, A. Nguyen
This paper presents a MEMS-based 5th-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5th-order filter having a 2nd-order analog and a 3rd-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front-end is programmable. The developed ASIC comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit internally non-linear flash ADC. The latter drives a 3rd-order digital filter which can be configured for different sensor parameters in order to ensure overall loop stability and to optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300-Hz bandwidth.
{"title":"A navigation-grade MEMS accelerometer based on a versatile front end","authors":"M. Pastre, M. Kayal, H. Schmid, P. Zwahlen, Yufeng Dong, A. Nguyen","doi":"10.1109/IECON.2011.6119971","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119971","url":null,"abstract":"This paper presents a MEMS-based 5<sup>th</sup>-order ΔΣ capacitive accelerometer. The ΔΣ loop is implemented in mixed signal, the global 5<sup>th</sup>-order filter having a 2<sup>nd</sup>-order analog and a 3<sup>rd</sup>-order digital part. The system can be used with a wide range of sensors, because the mixed-signal front-end is programmable. The developed ASIC comprises a voltage-mode preamplifier, two parallel demodulators implementing CDS, and a 7-bit internally non-linear flash ADC. The latter drives a 3<sup>rd</sup>-order digital filter which can be configured for different sensor parameters in order to ensure overall loop stability and to optimize the noise performance. With a low-noise MEMS sensor, the system achieves a 19-bit DR and a 16-bit SNR, both over a 300-Hz bandwidth.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128921836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119471
F. Chimento, N. Mora, M. Bellini, I. Stevanovic, S. Tomarchio
The paper deals with the evaluation of a suitable model for power IGBTs targeted for use in power electronic modules. The main issue for the developed model is the possibility of creating a circuital based structure starting from the device physical equations. The model is implemented in a circuital simulation environment with the aim of evaluating the performance of high voltage, high current modules. In those a key factor is the possibility of having computation times fitting with the necessity of parasitic elements estimation. The implementation of the model is described together with the validation of it by comparison with experimental results.
{"title":"A simplified spice based IGBT model for power electronics modules evaluation","authors":"F. Chimento, N. Mora, M. Bellini, I. Stevanovic, S. Tomarchio","doi":"10.1109/IECON.2011.6119471","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119471","url":null,"abstract":"The paper deals with the evaluation of a suitable model for power IGBTs targeted for use in power electronic modules. The main issue for the developed model is the possibility of creating a circuital based structure starting from the device physical equations. The model is implemented in a circuital simulation environment with the aim of evaluating the performance of high voltage, high current modules. In those a key factor is the possibility of having computation times fitting with the necessity of parasitic elements estimation. The implementation of the model is described together with the validation of it by comparison with experimental results.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128945844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119738
F. Andrén, M. Stifter, T. Strasser, Daniel Burnier de Castro
A key aspect to the future development of Smart Grids is the cooperation between multiple grid components. If this cooperation is to be included into grid simulations however, the limit is often reached when only one tool can be used for the simulations. This paper describes a framework for the simulation of power networks and their components including DIgSILENT/PowerFactory and MathWorks MATLAB/Simulink. A detailed model of a vanadium redox flow battery developed in MATLAB/Simulink is combined with a grid simulation performed in PowerFactory. The communication between the tools is realized using OPC. To show the possibilities with this framework a simulation of a real distribution grid in Austria with connected loads, photovoltaic power plants and storage devices was performed.
{"title":"Framework for co-ordinated simulation of power networks and components in Smart Grids using common communication protocols","authors":"F. Andrén, M. Stifter, T. Strasser, Daniel Burnier de Castro","doi":"10.1109/IECON.2011.6119738","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119738","url":null,"abstract":"A key aspect to the future development of Smart Grids is the cooperation between multiple grid components. If this cooperation is to be included into grid simulations however, the limit is often reached when only one tool can be used for the simulations. This paper describes a framework for the simulation of power networks and their components including DIgSILENT/PowerFactory and MathWorks MATLAB/Simulink. A detailed model of a vanadium redox flow battery developed in MATLAB/Simulink is combined with a grid simulation performed in PowerFactory. The communication between the tools is realized using OPC. To show the possibilities with this framework a simulation of a real distribution grid in Austria with connected loads, photovoltaic power plants and storage devices was performed.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132814248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-11-01DOI: 10.1109/IECON.2011.6119871
A. Abdel-Khalik, S. Ahmed, A. Massoud
Multiphase winding structures provide induction machines with favorable fault tolerant characteristics. Medium voltage drives have also benefited from the favorable application characteristics of multiphase machines, as well as advances in semiconductor technology. Although high voltage and current device technology has advanced significantly, device switching losses remains as one of the main design limitations in medium voltage drives. This limits the converter's switching frequency, causing degradation in the connected machine's performance due to an increase in torque ripple. This paper investigates the performance of various multiphase induction machines when fed from a quasi-square wave inverter. The inverter topology switches at the fundamental frequency to limit inverter losses, a highly desirable feature in medium voltage applications. Four multiphase induction machines with three, five, seven and eleven phases are designed and used in the comparison study. Finite element analysis is used to determine their parameters. The investigation aims to provide a clear understanding of optimal machine-converter matching criteria based on minimum torque ripple and maximum torque gain.
{"title":"Comparative evaluation of four quasi-square wave fed multiphase induction machines","authors":"A. Abdel-Khalik, S. Ahmed, A. Massoud","doi":"10.1109/IECON.2011.6119871","DOIUrl":"https://doi.org/10.1109/IECON.2011.6119871","url":null,"abstract":"Multiphase winding structures provide induction machines with favorable fault tolerant characteristics. Medium voltage drives have also benefited from the favorable application characteristics of multiphase machines, as well as advances in semiconductor technology. Although high voltage and current device technology has advanced significantly, device switching losses remains as one of the main design limitations in medium voltage drives. This limits the converter's switching frequency, causing degradation in the connected machine's performance due to an increase in torque ripple. This paper investigates the performance of various multiphase induction machines when fed from a quasi-square wave inverter. The inverter topology switches at the fundamental frequency to limit inverter losses, a highly desirable feature in medium voltage applications. Four multiphase induction machines with three, five, seven and eleven phases are designed and used in the comparison study. Finite element analysis is used to determine their parameters. The investigation aims to provide a clear understanding of optimal machine-converter matching criteria based on minimum torque ripple and maximum torque gain.","PeriodicalId":105539,"journal":{"name":"IECON 2011 - 37th Annual Conference of the IEEE Industrial Electronics Society","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130875942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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