Diagnosis for systematic defects is very critical for yield learning in nanometer technology. This paper presents a bridging fault diagnosis which identifies a single layer of systematic defects (LSD), where more than expected numbers of bridging faults are located. The proposed technique is a layout-aware diagnosis which contains bridging pair extraction, structural analysis, and layer-oriented covering. Instead of treating each failing CUT independently, a statistical method (Z-test) is applied to diagnose all CUTs simultaneously. Experiments on six of seven large ISCAS’89 benchmark circuits successfully diagnose LSD for single bridging fault as well as multiple bridging faults.
{"title":"Bridging Fault Diagnosis to Identify the Layer of Systematic Defects","authors":"Po-Juei Chen, C. Li, Hsing Jasmine Chao","doi":"10.1109/ATS.2009.58","DOIUrl":"https://doi.org/10.1109/ATS.2009.58","url":null,"abstract":"Diagnosis for systematic defects is very critical for yield learning in nanometer technology. This paper presents a bridging fault diagnosis which identifies a single layer of systematic defects (LSD), where more than expected numbers of bridging faults are located. The proposed technique is a layout-aware diagnosis which contains bridging pair extraction, structural analysis, and layer-oriented covering. Instead of treating each failing CUT independently, a statistical method (Z-test) is applied to diagnose all CUTs simultaneously. Experiments on six of seven large ISCAS’89 benchmark circuits successfully diagnose LSD for single bridging fault as well as multiple bridging faults.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an efficient pseudorandom (PR) test method to characterize the performance of nonlinear analog and mixed-signal (AMS) circuits including those embedded in SoC devices. Previous applications of the PR test method to BIST have been limited to digital and linear analog circuits. In this paper, we extend the application of PR test to nonlinear AMS circuits. In doing so, we reduce the cost of testing nonlinear circuits, and increase the test coverage of embedded AMS circuits without incurring a large area overhead to accommodate a test stimulus generator. Our method maintains good test accuracy by using a Volterra series model to describe the behavior of the device under test (DUT). A PR sequence generated from a simple LFSR is used to excite the DUTs over a wide range of frequencies and estimate the parameters of the Volterra series, which are then used to predict the performance of DUTs. We present a method to reduce the test time by using a compressed cross-correlation method which reduces the complexity of the presented algorithm. The mathematical background and hardware measurement results are presented to validate our method.
{"title":"LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal Circuits","authors":"Joonsung Park, Jaeyong Chung, J. Abraham","doi":"10.1109/ATS.2009.66","DOIUrl":"https://doi.org/10.1109/ATS.2009.66","url":null,"abstract":"This paper presents an efficient pseudorandom (PR) test method to characterize the performance of nonlinear analog and mixed-signal (AMS) circuits including those embedded in SoC devices. Previous applications of the PR test method to BIST have been limited to digital and linear analog circuits. In this paper, we extend the application of PR test to nonlinear AMS circuits. In doing so, we reduce the cost of testing nonlinear circuits, and increase the test coverage of embedded AMS circuits without incurring a large area overhead to accommodate a test stimulus generator. Our method maintains good test accuracy by using a Volterra series model to describe the behavior of the device under test (DUT). A PR sequence generated from a simple LFSR is used to excite the DUTs over a wide range of frequencies and estimate the parameters of the Volterra series, which are then used to predict the performance of DUTs. We present a method to reduce the test time by using a compressed cross-correlation method which reduces the complexity of the presented algorithm. The mathematical background and hardware measurement results are presented to validate our method.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127121865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu
This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (Test Access Mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a Data-Synchronous-Comparator (DSC) is proposed for comparing the scan responses of the identical cores.
Godson-3微处理器是一种基于SMOC (scalable Mesh of Crossbar)片上网络的可扩展多核处理器，目标是高端应用，本文描述了扫描测试所面临的挑战和使用的技术。在有限的I/O资源和大规模晶体管的挑战下，采用先进的技术实现可扩展、低功耗和低成本的扫描架构。为了实现可伸缩和灵活的测试访问，实现了一个高度精细的TAM(测试访问机制)，支持多个测试指令和测试模式。利用处理器内嵌多核的优势，采用扫描分区来降低测试功耗和测试时间，采用10倍以上压缩比的测试压缩来缩短扫描链长度。为了进一步减少测试时间，提出了一种数据同步比较器(DSC)来比较相同内核的扫描响应。
{"title":"A Scalable Scan Architecture for Godson-3 Multicore Microprocessor","authors":"Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu","doi":"10.1109/ATS.2009.52","DOIUrl":"https://doi.org/10.1109/ATS.2009.52","url":null,"abstract":"This paper describes the scan test challenges and techniques used in the Godson-3 microprocessor, which is a scalable multicore processor based on the SMOC (Scalable Mesh of Crossbar) on-chip network and targets high-end applications. Advanced techniques are adopted to achieve the scalable, low-power and low-cost scan architecture at the challenge of limited I/O resources and large scale of transistors. To achieve a scalable and flexible test access, a highly elaborate TAM (Test Access Mechanism) is implemented with supporting multiple test instructions and test modes. Taking advantage of multiple cores embedding in the processor, scan partitions are employed to reduce test power and test time, and test compression with more than 10X compression ratio are utilized to decrease the scan chain length. To further decrease test time, a Data-Synchronous-Comparator (DSC) is proposed for comparing the scan responses of the identical cores.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127220321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.
{"title":"New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults","authors":"A. V. Goor, S. Hamdioui, G. Gaydadjiev, Z. Al-Ars","doi":"10.1109/ATS.2009.87","DOIUrl":"https://doi.org/10.1109/ATS.2009.87","url":null,"abstract":"Due to the rapid decrease of technology feature size speed related faults, such as Address Decoder Delay Faults (ADDFs), are becoming very important. In addition, increased leakage currents demand for improved tests for Bit Line Imbalance Faults (BLIFs)(caused by memory cell pass transistor leakage). This paper contributes to new and improved algorithms for detecting these faults. First it provides an improved version of existing GalPat algorithm and introduces two new algorithms to detect ADDFs; the paper also shines a new light on the use of the different stress combinations (counting methods, data-backgrounds) and their importance for the detection of ADDFs. Second, it provides an improved algorithm for detecting BLIFs; it increases the defect coverage by being able to detect lower leakage currents.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127271547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the technology scaling and increase in integration density, severe static (e.g., random dopant, subwavelength lithography, etc) and dynamic (e.g., voltage, temperature, etc) variations will rise. It is widely recognized that variability in device characteristics and its impact on the overall reliability of the system represent major challenges to scaling and integration for present and future nanotechnology generations. Moreover, the failure mechanism in the nano-era will be more dominated by transient faults (e.g., external perturbations, radiation, power fluctuations) and intermittent faults (e.g., timing faults, degradation of the component parameters) rather than permanent faults. This shift in failure mechanisms will impact the reliability in a sever way. It is becoming very hard to guarantee the reliability with today’s extensive, hence costly, traditional approaches (e.g., testing at extreme stresses, Burn-in, etc). Moreover, such approaches may reduce the lifetime of devices fabricated using nano technology nodes.
{"title":"Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?","authors":"S. Hamdioui","doi":"10.1109/ATS.2009.92","DOIUrl":"https://doi.org/10.1109/ATS.2009.92","url":null,"abstract":"With the technology scaling and increase in integration density, severe static (e.g., random dopant, subwavelength lithography, etc) and dynamic (e.g., voltage, temperature, etc) variations will rise. It is widely recognized that variability in device characteristics and its impact on the overall reliability of the system represent major challenges to scaling and integration for present and future nanotechnology generations. Moreover, the failure mechanism in the nano-era will be more dominated by transient faults (e.g., external perturbations, radiation, power fluctuations) and intermittent faults (e.g., timing faults, degradation of the component parameters) rather than permanent faults. This shift in failure mechanisms will impact the reliability in a sever way. It is becoming very hard to guarantee the reliability with today’s extensive, hence costly, traditional approaches (e.g., testing at extreme stresses, Burn-in, etc). Moreover, such approaches may reduce the lifetime of devices fabricated using nano technology nodes.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130969959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the changing face of the consumer driven semiconductor industry, there are new challenges facing the industry which need to be resolved. Minimizing Power dissipation is a significant and growing challenge with the growth of the wireless and portable device segments and with the need to be ‘green’. Even during manufacturing test, power is definitely among the top ten items needing attention and expertise. Since 90-nm there has been a recognition that power consumption during test can be a factor affecting product quality and yield. Excessive power consumption during manufacturing test affects the reliability of digital integrated circuits, leading to power-driven failures and higher infant mortality. These trends if continuing on their present course will force designers to adopt specific power management and low power design techniques for manufacturing test.
{"title":"Is Low Power Testing Necessary? What does the Test Industry Truly Need?","authors":"A. Uzzaman","doi":"10.1109/ATS.2009.91","DOIUrl":"https://doi.org/10.1109/ATS.2009.91","url":null,"abstract":"With the changing face of the consumer driven semiconductor industry, there are new challenges facing the industry which need to be resolved. Minimizing Power dissipation is a significant and growing challenge with the growth of the wireless and portable device segments and with the need to be ‘green’. Even during manufacturing test, power is definitely among the top ten items needing attention and expertise. Since 90-nm there has been a recognition that power consumption during test can be a factor affecting product quality and yield. Excessive power consumption during manufacturing test affects the reliability of digital integrated circuits, leading to power-driven failures and higher infant mortality. These trends if continuing on their present course will force designers to adopt specific power management and low power design techniques for manufacturing test.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125374973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan- or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external control is carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the design space of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.
{"title":"Transaction Level Modeling and Design Space Exploration for SOC Test Architectures","authors":"C. Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, A. Su","doi":"10.1109/ATS.2009.33","DOIUrl":"https://doi.org/10.1109/ATS.2009.33","url":null,"abstract":"Transaction level modeling (TLM) provides a feasible methodology to model an SOC at a high abstraction level such that system level design issues can be dealt with efficiently. One of the issues that have not been well discussed at the transaction level is SOC testing. In this paper we address the problem of how to construct transaction level test architectures for SOC designs. We model the components required for SOC testing including embedded processor, memory, system bus as well as the test access mechanism, test bus, test wrappers and scan- or BIST-based IP cores. A case study on integrating these components into a test platform that can execute test procedures with very little external control is carried out. Experimental results show that 3 to 4 orders of magnitude improvement on simulation speed can be achieved compared with the RTL models. We also explore the design space of the test platform and show that various test architectures can be easily constructed and analyzed with this TLM methodology.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduced using a SAT-based ATPG approach. In contrast to structural ATPG, SAT solvers work on a Boolean formula in Conjunctive Normal Form (CNF). This results in some disadvantages for SAT solvers when applied to ATPG, e.g. CNF transformation time and loss of structural knowledge. As a result, SAT-based ATPG algorithms are very robust for hard-to-test faults, but suffer from the overhead for easy-to-test faults. We propose the SAT technique Dynamic Clause Activation (DCA) in order to reduce the run time gap between structural and SAT-based ATPG algorithms and, at the same time, retain the high level of robustness. Using DCA, the SAT solver works on a partial formula of a logic circuit which is dynamically extended during the search process using structural knowledge. Furthermore, efficient dynamic learning techniques can be easily integrated within the proposed technique. The approach is evaluated on large industrial circuits.
{"title":"Speeding up SAT-Based ATPG Using Dynamic Clause Activation","authors":"Stephan Eggersglüß, Daniel Tille, R. Drechsler","doi":"10.1109/ATS.2009.26","DOIUrl":"https://doi.org/10.1109/ATS.2009.26","url":null,"abstract":"SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduced using a SAT-based ATPG approach. In contrast to structural ATPG, SAT solvers work on a Boolean formula in Conjunctive Normal Form (CNF). This results in some disadvantages for SAT solvers when applied to ATPG, e.g. CNF transformation time and loss of structural knowledge. As a result, SAT-based ATPG algorithms are very robust for hard-to-test faults, but suffer from the overhead for easy-to-test faults. We propose the SAT technique Dynamic Clause Activation (DCA) in order to reduce the run time gap between structural and SAT-based ATPG algorithms and, at the same time, retain the high level of robustness. Using DCA, the SAT solver works on a partial formula of a logic circuit which is dynamically extended during the search process using structural knowledge. Furthermore, efficient dynamic learning techniques can be easily integrated within the proposed technique. The approach is evaluated on large industrial circuits.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134594281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advances in the semiconductor manufacturing technologies have resulted in the defect distribution to both random defects and process weakness due to smaller geometry. The keep-increasing complexity of the designs makes the traditional failure analysis and yield learning techniques inadequate for finding the root cause.
{"title":"Yield Ramp up by Scan Chain Diagnosis","authors":"F. Kuo, Yuan-Shih Chen","doi":"10.1109/ATS.2009.70","DOIUrl":"https://doi.org/10.1109/ATS.2009.70","url":null,"abstract":"Advances in the semiconductor manufacturing technologies have resulted in the defect distribution to both random defects and process weakness due to smaller geometry. The keep-increasing complexity of the designs makes the traditional failure analysis and yield learning techniques inadequate for finding the root cause.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122175067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, J. Liou
Test integration for heterogeneous cores under test has been a challenging problem in a system-on-chip (SoC) design. To integrate heterogeneous cores under test, the test wrapper should be capable of dealing with multiple-clock domain problems, at-speed testing problems, test power problems, etc. In this paper, we propose an alternative wrapper architecture that supports multiple clock domains, and therefore test operations can run (test) at system speed. Since each CUT has very different requirements, the test wrapper unavoidably needs to be re-designed for a new CUT. In order to reduce the manual effort, we propose to automatically generate test wrappers and the corresponding test programs based on the given configuration and test description for each CUT. We adopted the IEEE 1450.6 standard, a.k.a. Core Test Language (CTL), as the test description language in this work. Through the process, circuits can be tested with low overheads, and minimal intervention from designers will be required. We have successfully integrated a test wrapper generated by using our tool into a test chip which includes a Memory BIST and a Logic BIST and tapped out the chip in TSMC 0.18$mu$m technology. The experiments showed that the area overhead of proposed architecture is only 0.02% of chip area in the chip.
{"title":"Multiple-Core under Test Architecture for HOY Wireless Testing Platform","authors":"Sung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, J. Liou","doi":"10.1109/ATS.2009.43","DOIUrl":"https://doi.org/10.1109/ATS.2009.43","url":null,"abstract":"Test integration for heterogeneous cores under test has been a challenging problem in a system-on-chip (SoC) design. To integrate heterogeneous cores under test, the test wrapper should be capable of dealing with multiple-clock domain problems, at-speed testing problems, test power problems, etc. In this paper, we propose an alternative wrapper architecture that supports multiple clock domains, and therefore test operations can run (test) at system speed. Since each CUT has very different requirements, the test wrapper unavoidably needs to be re-designed for a new CUT. In order to reduce the manual effort, we propose to automatically generate test wrappers and the corresponding test programs based on the given configuration and test description for each CUT. We adopted the IEEE 1450.6 standard, a.k.a. Core Test Language (CTL), as the test description language in this work. Through the process, circuits can be tested with low overheads, and minimal intervention from designers will be required. We have successfully integrated a test wrapper generated by using our tool into a test chip which includes a Memory BIST and a Logic BIST and tapped out the chip in TSMC 0.18$mu$m technology. The experiments showed that the area overhead of proposed architecture is only 0.02% of chip area in the chip.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129726219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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