K. Deepak, Robinson Reyna, Virendra Singh, A. Singh
Enhanced Scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial Enhanced Scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS’89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.
{"title":"Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing","authors":"K. Deepak, Robinson Reyna, Virendra Singh, A. Singh","doi":"10.1109/ATS.2009.78","DOIUrl":"https://doi.org/10.1109/ATS.2009.78","url":null,"abstract":"Enhanced Scan design can significantly improve the fault coverage for two pattern delay tests at the cost of exorbitantly high area overhead. The redundant flip-flops introduced in the scan chains have traditionally only been used to launch the two-pattern delay test inputs, not to capture tests results. This paper presents a new, much lower cost partial Enhanced Scan methodology with both improved controllability and observability. Facilitating observation of some hard to observe internal nodes by capturing their response in the already available and underutilized redundant flip-flops improves delay fault coverage with minimal or almost negligible cost. Experimental results on ISCAS’89 benchmark circuits show significant improvement in TDF fault coverage for this new partial enhance scan methodology.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132116287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, F. Kuo, Yuan-Shih Chen
In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis. Finally, several case studies and their PFA results are presented to validate the accuracy and effectiveness of the proposed algorithm.
{"title":"Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns","authors":"Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, F. Kuo, Yuan-Shih Chen","doi":"10.1109/ATS.2009.36","DOIUrl":"https://doi.org/10.1109/ATS.2009.36","url":null,"abstract":"In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper we first analyze the advantages and disadvantages of each category of the chain diagnosis algorithms. Next, an adaptive signal profiling algorithm that can use manufacturing ATPG scan patterns is proposed for scan chain diagnosis. Finally, several case studies and their PFA results are presented to validate the accuracy and effectiveness of the proposed algorithm.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"269 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131691760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator offset. Together with existing SC testing techniques, the leakage characterization technique helps better characterize SC circuits; its application to several popular SC circuits is demonstrated.
{"title":"An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits Testing","authors":"Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang","doi":"10.1109/ATS.2009.55","DOIUrl":"https://doi.org/10.1109/ATS.2009.55","url":null,"abstract":"This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator offset. Together with existing SC testing techniques, the leakage characterization technique helps better characterize SC circuits; its application to several popular SC circuits is demonstrated.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125018266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
To cope with increasing in-field failure rates for cost-sensitive electronic products, a low-overhead online checking methodology -- Time-Multiplexed Online Checking (TMOC) -- was proposed and demonstrated in [1]. In this paper, we study the area overhead required for employing TMOC in an embedded Field Programmable Gate Array (eFPGA) core. The overheads caused by the relatively low logic density of eFPGA and the interface routing between a design module and its TMOC checker are examined in detail. In a case study of an H.264 decoder design [2], TMOC is compared to a dedicated duplication-based online checking scheme [3], which typically incurs more than 100% area overhead. Experimental results show that TMOC provides significant chip area overhead reduction for online checkers. A reduction of 68% is achieved when one checker is shared by 62 design partitions, for example. TMOC can also help reduce dynamic power overhead of online checking by increasing the number of partitions, at the cost of increased fault detection latency in some partitions.
{"title":"Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 Decoder","authors":"Ming Gao, K. Cheng","doi":"10.1109/ATS.2009.24","DOIUrl":"https://doi.org/10.1109/ATS.2009.24","url":null,"abstract":"To cope with increasing in-field failure rates for cost-sensitive electronic products, a low-overhead online checking methodology -- Time-Multiplexed Online Checking (TMOC) -- was proposed and demonstrated in [1]. In this paper, we study the area overhead required for employing TMOC in an embedded Field Programmable Gate Array (eFPGA) core. The overheads caused by the relatively low logic density of eFPGA and the interface routing between a design module and its TMOC checker are examined in detail. In a case study of an H.264 decoder design [2], TMOC is compared to a dedicated duplication-based online checking scheme [3], which typically incurs more than 100% area overhead. Experimental results show that TMOC provides significant chip area overhead reduction for online checkers. A reduction of 68% is achieved when one checker is shared by 62 design partitions, for example. TMOC can also help reduce dynamic power overhead of online checking by increasing the number of partitions, at the cost of increased fault detection latency in some partitions.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123829927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Benabboud, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, Olivia Riewer
The importance of delay faults proportionally increases when entering in the nano-technology era, and logic diagnosis must localize delay faults as precisely as possible to speed-up yield ramp-up. This paper presents a logic diagnosis approach targeting delay faults. The proposed approach is based on the Single-Location-at-A-Time (SLAT) paradigm used to determine a set of suspects. It addresses the case of sequential circuits tested at-speed. The main advantages of this approach are that it can manage a comprehensive set of delay faults, and that it is independent on the size of the delay (induced by the fault). Experimental results show the effectiveness of the proposed approach in terms of absolute number of suspects.
{"title":"Delay Fault Diagnosis in Sequential Circuits","authors":"Y. Benabboud, A. Bosio, L. Dilillo, P. Girard, S. Pravossoudovitch, A. Virazel, Olivia Riewer","doi":"10.1109/ATS.2009.16","DOIUrl":"https://doi.org/10.1109/ATS.2009.16","url":null,"abstract":"The importance of delay faults proportionally increases when entering in the nano-technology era, and logic diagnosis must localize delay faults as precisely as possible to speed-up yield ramp-up. This paper presents a logic diagnosis approach targeting delay faults. The proposed approach is based on the Single-Location-at-A-Time (SLAT) paradigm used to determine a set of suspects. It addresses the case of sequential circuits tested at-speed. The main advantages of this approach are that it can manage a comprehensive set of delay faults, and that it is independent on the size of the delay (induced by the fault). Experimental results show the effectiveness of the proposed approach in terms of absolute number of suspects.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"86 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123289433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Manuel J. Barragan Asian, R. Fiorelli, D. Vázquez, A. Rueda, J. Huertas
This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.
{"title":"A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response Analysis","authors":"Manuel J. Barragan Asian, R. Fiorelli, D. Vázquez, A. Rueda, J. Huertas","doi":"10.1109/ATS.2009.14","DOIUrl":"https://doi.org/10.1109/ATS.2009.14","url":null,"abstract":"This paper presents a novel and low-cost methodology that can be used for testing RF blocks embedded in complex SoCs. It is based on the detection and spectral analysis of the two-tone response envelope of the block under test. The main non-linearity specifications of the block under test can be easily extracted from the envelope signal. The analytical basis of the proposed methodology is demonstrated, and a proposal for its implementation as a built-in test core is discussed. Finally, practical simulation examples show the feasibility of the approach.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129305871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A scheme that ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). After AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don’t care bits (x) as in test compression, and it is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT.
{"title":"New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology","authors":"Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, J. Rau","doi":"10.1109/ATS.2009.48","DOIUrl":"https://doi.org/10.1109/ATS.2009.48","url":null,"abstract":"A scheme that ATPG-based technique for reducing shift and capture power during scan testing is presented without any influence on fault coverage. This paper presents an X-filling approach called Adjacent Backtracing fill (AB-fill). After AB-fill approach for at-speed scan testing, all of test patterns have assigned as partially-specified values with a small number of don’t care bits (x) as in test compression, and it is integrated in the ATPG algorithm to reduce capture power while feeding the first test pattern into CUT.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"200 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sehun Kook, H. Choi, Vishwanath Natarajan, A. Chatterjee, A. Gomes, Shalabh Goyal, Le Jin
In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ΔΣ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent over-sampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodology.
{"title":"Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCs","authors":"Sehun Kook, H. Choi, Vishwanath Natarajan, A. Chatterjee, A. Gomes, Shalabh Goyal, Le Jin","doi":"10.1109/ATS.2009.76","DOIUrl":"https://doi.org/10.1109/ATS.2009.76","url":null,"abstract":"In this paper, a low-cost test methodology for dynamic specifications of high precision sigma-delta (ΔΣ) analog-to-digital converters (ADCs) is presented. Dynamic testing of ADCs requires an input test stimulus with total harmonic distortion (THD) and signal-to-noise ratio (SNR) about 10dB better than the ADC under test. ΔΣ ADCs are inherently high resolution converters with excellent THD and SNR due to their inherent over-sampling, averaging and noise shaping properties. In the proposed test methodology, the back end digital and decimation filters of such converters are turned off and the digital pulse sequence at the output of the sigma-delta modulator is made externally observable for test purposes. It is seen that ENOB, THD and SNR of the converter can be determined with significantly increased sensitivity to device nonlinearities and noise allowing the use of less than ideal input stimulus than otherwise or significantly reduced test time. The back-end filters are then tested using traditional digital test techniques. Simulation results show the usefulness of the proposed test methodology.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123251353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test (BIST), significantly influences the fault coverage and total test application time. This paper introduces a one-pass seed selection algorithm, for any known PRPG. Due to its single-pass nature, unlike the state-of-the-art exhaustive search methods, the proposed algorithm is more time and memory efficient. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits, and synthetic SoCs built out of the combinational benchmarks, show considerable reduction in test length within comparable fault efficiencies, almost 100%, with respect to the existing methods.
{"title":"A Novel Seed Selection Algorithm for Test Time Reduction in BIST","authors":"R. Chakraborty, D. R. Chowdhury","doi":"10.1109/ATS.2009.10","DOIUrl":"https://doi.org/10.1109/ATS.2009.10","url":null,"abstract":"The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test (BIST), significantly influences the fault coverage and total test application time. This paper introduces a one-pass seed selection algorithm, for any known PRPG. Due to its single-pass nature, unlike the state-of-the-art exhaustive search methods, the proposed algorithm is more time and memory efficient. Experimental results on ISCAS’85 and ISCAS’89 benchmark circuits, and synthetic SoCs built out of the combinational benchmarks, show considerable reduction in test length within comparable fault efficiencies, almost 100%, with respect to the existing methods.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126738459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For core-based System-on-Chip (SoC) testing, conventional power-constrained test scheduling methods do not guarantee a thermal-safe solution. Also, most of the test scheduling schemes make poor assumptions about power consumption. In deep submicron era, leakage power and wake-up power consumption can not be neglected. In this paper, we propose a partition based thermal-aware test scheduling algorithm with more realistic assumptions of recent SoCs. In our test scheduling algorithm, each test is partitioned and the earliest starting time of each partition is searched. To reduce the execution time of thermal simulation, we also exploit superposition principle to compute the power and thermal profile rapidly and accurately. We apply our test scheduling algorithm to ITC’02 SoC benchmarks and the results show improvements in the total test time over scheduling schemes without partitioning.
{"title":"Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron Technologies","authors":"Chunhua Yao, K. Saluja, P. Ramanathan","doi":"10.1109/ATS.2009.15","DOIUrl":"https://doi.org/10.1109/ATS.2009.15","url":null,"abstract":"For core-based System-on-Chip (SoC) testing, conventional power-constrained test scheduling methods do not guarantee a thermal-safe solution. Also, most of the test scheduling schemes make poor assumptions about power consumption. In deep submicron era, leakage power and wake-up power consumption can not be neglected. In this paper, we propose a partition based thermal-aware test scheduling algorithm with more realistic assumptions of recent SoCs. In our test scheduling algorithm, each test is partitioned and the earliest starting time of each partition is searched. To reduce the execution time of thermal simulation, we also exploit superposition principle to compute the power and thermal profile rapidly and accurately. We apply our test scheduling algorithm to ITC’02 SoC benchmarks and the results show improvements in the total test time over scheduling schemes without partitioning.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125801649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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