This paper reports synthesis of a built-in self-test logic for the cores integrated into an SoC. The test logic is developed around a nonlinear cellular automata (CA). The CA based scalable PRPG, synthesized in linear time (O(n)), enables the design of such a highly efficient test logic. The cascadable structure of the PRPG is utilized to construct the on-chip Test Pattern Generators (TPGs) for the SoC implementing multiple cores. It avoids the requirement of disparate test hardware for the SoC cores and thereby ensures drastic reduction in the cost of test logic. Extensive experimentation confirms the better efficiency of the proposed test structure than that of the conventional designs, developed around maximal length CA/LFSR.
{"title":"CA Based Built-In Self-Test Structure for SoC","authors":"Sukanta Das, B. Sikdar","doi":"10.1109/ATS.2009.71","DOIUrl":"https://doi.org/10.1109/ATS.2009.71","url":null,"abstract":"This paper reports synthesis of a built-in self-test logic for the cores integrated into an SoC. The test logic is developed around a nonlinear cellular automata (CA). The CA based scalable PRPG, synthesized in linear time (O(n)), enables the design of such a highly efficient test logic. The cascadable structure of the PRPG is utilized to construct the on-chip Test Pattern Generators (TPGs) for the SoC implementing multiple cores. It avoids the requirement of disparate test hardware for the SoC cores and thereby ensures drastic reduction in the cost of test logic. Extensive experimentation confirms the better efficiency of the proposed test structure than that of the conventional designs, developed around maximal length CA/LFSR.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127365074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Embedded scan test compression is used to enable high test quality and has become a standard practice on many designs. This paper describes power and timing experiences related to embedded compression technology. A commercial tool was used to implement EDT compression technology in three wireless designs. The case study and results demonstrate the effect of power reduction methods and timing closure considerations.
{"title":"Scan Compression Implementation in Industrial Design - Case Study","authors":"D. Hsu, R. Press","doi":"10.1109/ATS.2009.89","DOIUrl":"https://doi.org/10.1109/ATS.2009.89","url":null,"abstract":"Embedded scan test compression is used to enable high test quality and has become a standard practice on many designs. This paper describes power and timing experiences related to embedded compression technology. A commercial tool was used to implement EDT compression technology in three wireless designs. The case study and results demonstrate the effect of power reduction methods and timing closure considerations.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114616378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on industrial designs show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences.
{"title":"Test Generation for Designs with On-Chip Clock Generators","authors":"X. Lin, M. Kassab","doi":"10.1109/ATS.2009.46","DOIUrl":"https://doi.org/10.1109/ATS.2009.46","url":null,"abstract":"High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to facilitate the test generation process and it in turn creates additional constraints for the automatic test pattern generation (ATPG) tool. This paper describes an efficient and effective method to take the hardware restrictions originated from the on-chip clock generators into account in order to avoid generating clock sequences that cannot be produced by hardware. Experimental results on industrial designs show test pattern reduction and/or ATPG run time reduction when compared with the test generation method that enumerates valid clock sequences explicitly and restricts the test generation within enumerated test sequences.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114805225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As diagnostic testing for memory devices increasingly gains in importance, companies are looking for flexible, cost effective methods to perform diagnostics on their failing devices. This paper proposes the new concept of test primitives as a method to diagnose memory faults. Test primitives provide an easy-to-use, extensible, low-cost memory fault diagnosis method that is universally applicable, since it uses simple platform-independent test sequences. The paper defines the concept of test primitives, shows their importance and gives examples to the way they are derived and used in a memory test environment.
{"title":"Fault Diagnosis Using Test Primitives in Random Access Memories","authors":"Z. Al-Ars, S. Hamdioui","doi":"10.1109/ATS.2009.79","DOIUrl":"https://doi.org/10.1109/ATS.2009.79","url":null,"abstract":"As diagnostic testing for memory devices increasingly gains in importance, companies are looking for flexible, cost effective methods to perform diagnostics on their failing devices. This paper proposes the new concept of test primitives as a method to diagnose memory faults. Test primitives provide an easy-to-use, extensible, low-cost memory fault diagnosis method that is universally applicable, since it uses simple platform-independent test sequences. The paper defines the concept of test primitives, shows their importance and gives examples to the way they are derived and used in a memory test environment.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128419201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the random jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-starved inverter, and whose frequency difference from the OR operation and the AND operation is used in calculating the RMS value of the random jitter. Circuit-level simulations show the validity of the proposed technique for up to 20% peak-to-peak jitter in the clock even with process variations. The proposed technique can be applied to BIST solutions for random jitter measurement on a transmitted clock signal.
{"title":"A Random Jitter RMS Estimation Technique for BIST Applications","authors":"Jae Wook Lee, J. Chun, J. Abraham","doi":"10.1109/ATS.2009.38","DOIUrl":"https://doi.org/10.1109/ATS.2009.38","url":null,"abstract":"This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the random jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-starved inverter, and whose frequency difference from the OR operation and the AND operation is used in calculating the RMS value of the random jitter. Circuit-level simulations show the validity of the proposed technique for up to 20% peak-to-peak jitter in the clock even with process variations. The proposed technique can be applied to BIST solutions for random jitter measurement on a transmitted clock signal.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133996065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.
{"title":"A Low Overhead On-Chip Path Delay Measurement Circuit","authors":"Songwei Pei, Huawei Li, Xiaowei Li","doi":"10.1109/ATS.2009.64","DOIUrl":"https://doi.org/10.1109/ATS.2009.64","url":null,"abstract":"In this paper, we present a novel on-chip path delay measurement circuit for efficiently detecting and debugging of delay faults in the fabricated integrated circuits. Several delay stages are employed in the proposed circuit, whose delay ranges are increased by a factor of two gradually from the last to the first delay stage. Thus, the proposed method can achieve a large delay measurement range with a small quantity of delay stages. Experimental results show that a significant reduction in both delay measurement time and area overhead can be obtained compared to the previous Vernier Delay Line based delay measurement schemes. In addition, by conducting delay compensation, the proposed method can achieve both improved delay measurement resolution and measurement accuracy.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125164419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit by some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.
{"title":"Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients","authors":"S. Sindia, Virendra Singh, V. Agrawal","doi":"10.1109/ATS.2009.45","DOIUrl":"https://doi.org/10.1109/ATS.2009.45","url":null,"abstract":"A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the applied input voltage at relevant frequencies in addition to DC. Classification of CUT is based on a comparison of the estimated polynomial coefficients with those of the fault free circuit. This testing method requires no design for test hardware as might be added to the circuit by some other methods. The proposed method is illustrated for a benchmark elliptic filter. It is shown to uncover several parametric faults causing deviations as small as 5% from the nominal values.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127436673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the resolution. We propose deterministic ATPG algorithms to create test vectors within predefined leakage ranges. Even when random pattern generation does not find test vectors, the proposed algorithms identify vectors within the desired range. Experimental results confirm that leakage constraints are effectively handled during test pattern generation without decreasing fault coverage.
{"title":"Deterministic Algorithms for ATPG under Leakage Constraints","authors":"G. Fey","doi":"10.1109/ATS.2009.27","DOIUrl":"https://doi.org/10.1109/ATS.2009.27","url":null,"abstract":"Measuring the steady state leakage current (IDDQ) is very successful in detecting faults not discovered by standard fault models. But vector dependencies of IDDQ decrease the resolution. We propose deterministic ATPG algorithms to create test vectors within predefined leakage ranges. Even when random pattern generation does not find test vectors, the proposed algorithms identify vectors within the desired range. Experimental results confirm that leakage constraints are effectively handled during test pattern generation without decreasing fault coverage.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121041973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we analyze the relationship between calibration and linearity testing of a digitally-calibrated pipelined ADC. Simulation results validate that the calibration process, once converged, could have automatically covered the INL testing of the ADC under test.
{"title":"Calibration as a Functional Test: An ADC Case Study","authors":"Hsiu-Ming Chang, Kuan-Yu Lin, K. Cheng","doi":"10.1109/ATS.2009.25","DOIUrl":"https://doi.org/10.1109/ATS.2009.25","url":null,"abstract":"In this paper, we analyze the relationship between calibration and linearity testing of a digitally-calibrated pipelined ADC. Simulation results validate that the calibration process, once converged, could have automatically covered the INL testing of the ADC under test.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115941234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Diagnosis for delay defects becomes more significant as the CMOS process advances to nanometer regime. The most challenging problems of delay fault diagnosis in nanometer process come from the process variation, which results in small delay variations. Small delay variations are difficult to be diagnosed by using existing methods based on a specific fault model. This paper presents a new estimation method for gate or interconnect delays based on the maximum likelihood estimation. The proposed method outputs most probable gate/interconnect delays that matches the measured path delays under the nominal delay distribution. Unlike the previous diagnosis methods, our method does not take any assumption on defect numbers, sizes and types (models), and thus it can be used to diagnose performance bottlenecks resulted from systematic variations. The experimental results show that the average correlation achieves 0.848 between estimated (by the proposed method) and sampled segment delays (generated from process models) for ISCAS89 benchmarks. There is a substantial improvement of 0.271 over the existing method.
{"title":"A Non-Intrusive and Accurate Inspection Method for Segment Delay Variabilities","authors":"Ying-Yen Chen, J. Liou","doi":"10.1109/ATS.2009.32","DOIUrl":"https://doi.org/10.1109/ATS.2009.32","url":null,"abstract":"Diagnosis for delay defects becomes more significant as the CMOS process advances to nanometer regime. The most challenging problems of delay fault diagnosis in nanometer process come from the process variation, which results in small delay variations. Small delay variations are difficult to be diagnosed by using existing methods based on a specific fault model. This paper presents a new estimation method for gate or interconnect delays based on the maximum likelihood estimation. The proposed method outputs most probable gate/interconnect delays that matches the measured path delays under the nominal delay distribution. Unlike the previous diagnosis methods, our method does not take any assumption on defect numbers, sizes and types (models), and thus it can be used to diagnose performance bottlenecks resulted from systematic variations. The experimental results show that the average correlation achieves 0.848 between estimated (by the proposed method) and sampled segment delays (generated from process models) for ISCAS89 benchmarks. There is a substantial improvement of 0.271 over the existing method.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"196 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116052926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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