Vishwanath Natarajan, S. Devarakond, Shreyas Sen, A. Chatterjee
In this paper, a fast RF BIST-driven post-manufacture tuning methodology for yield improvement of RF transceiver systems is presented. The core algorithms optimize multiple transceiver performance metrics concurrently using a hardware-iterated gradient search algorithm that uses diagnostic BIST data to guide the tuning of circuit and software level parameters. Intelligent “initial guess” values for the circuit and software tuning knobs at the start of the tuning process allow rapid convergence. Power consumption is given key consideration through the tuning process. Further, self-tuning is performed with little or no external tester support. The viability of the proposed scheme has been demonstrated through an experimental RF hardware prototype. Experimental results demonstrate significant yield recovery while allowing up to 10X savings in test/tuning time.
{"title":"BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient Search","authors":"Vishwanath Natarajan, S. Devarakond, Shreyas Sen, A. Chatterjee","doi":"10.1109/ATS.2009.75","DOIUrl":"https://doi.org/10.1109/ATS.2009.75","url":null,"abstract":"In this paper, a fast RF BIST-driven post-manufacture tuning methodology for yield improvement of RF transceiver systems is presented. The core algorithms optimize multiple transceiver performance metrics concurrently using a hardware-iterated gradient search algorithm that uses diagnostic BIST data to guide the tuning of circuit and software level parameters. Intelligent “initial guess” values for the circuit and software tuning knobs at the start of the tuning process allow rapid convergence. Power consumption is given key consideration through the tuning process. Further, self-tuning is performed with little or no external tester support. The viability of the proposed scheme has been demonstrated through an experimental RF hardware prototype. Experimental results demonstrate significant yield recovery while allowing up to 10X savings in test/tuning time.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"30 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116885141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power distribution network (PDN) designs for today's high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and hence defects may be introduced on PDNs during the manufacturing process. Since we cannot afford to over-design the PDNs to tolerate all possible defects, it is necessary to conduct manufacturing test for them. In this paper, we propose novel methodologies to identify those potentially harmful open defects in PDNs and we show how to select a set of patterns that initially target transition faults to achieve high fault coverage for the PDN defects. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.
{"title":"Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution Networks","authors":"Yubin Zhang, Lin Huang, F. Yuan, Q. Xu","doi":"10.1109/ATS.2009.69","DOIUrl":"https://doi.org/10.1109/ATS.2009.69","url":null,"abstract":"Power distribution network (PDN) designs for today's high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and hence defects may be introduced on PDNs during the manufacturing process. Since we cannot afford to over-design the PDNs to tolerate all possible defects, it is necessary to conduct manufacturing test for them. In this paper, we propose novel methodologies to identify those potentially harmful open defects in PDNs and we show how to select a set of patterns that initially target transition faults to achieve high fault coverage for the PDN defects. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed technique.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123457008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Multi-media based applications have increased immensely in the last few years. The need to have better video quality, higher recording and playback time, more video channels and faster time to market (TTM) requires DFT solutions that use core-based testing to allow concurrent IP and SOC development, scalable to support multiple technologies and eases the development of timing constraints. This paper describes the challenges and solutions used to address them.
{"title":"DFT Challenges in Next Generation Multi-media IP","authors":"Mukund Mittal, Subrangshu Das, S. Vishwanath","doi":"10.1109/ATS.2009.73","DOIUrl":"https://doi.org/10.1109/ATS.2009.73","url":null,"abstract":"Multi-media based applications have increased immensely in the last few years. The need to have better video quality, higher recording and playback time, more video channels and faster time to market (TTM) requires DFT solutions that use core-based testing to allow concurrent IP and SOC development, scalable to support multiple technologies and eases the development of timing constraints. This paper describes the challenges and solutions used to address them.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116225644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a design-for-testability (DFT) technique for increasing the effectiveness of LFSR reseeding for unmodeled defects. The proposed method relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations. Simulation results for benchmark circuits show that compared to LFSR reseeding using output deviations alone, the proposed method provides higher coverage for transition-delay and bridging faults, and steeper coverage ramp-up for these faults for the same number of seeds. For the same pattern count (and much fewer seeds), the proposed method provides comparable unmodeled defect coverage. In all cases, complete coverage of modeled stuck-at faults is obtained. We therefore conclude that high test quality can be obtained with the proposed LFSR reseeding method using a smaller number of seeds.
{"title":"Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect Coverage","authors":"Hongxia Fang, K. Chakrabarty, R. Parekhji","doi":"10.1109/ATS.2009.65","DOIUrl":"https://doi.org/10.1109/ATS.2009.65","url":null,"abstract":"We present a design-for-testability (DFT) technique for increasing the effectiveness of LFSR reseeding for unmodeled defects. The proposed method relies on seed selection using the output-deviations metric and the on-chip augmentation of seeds using simple bit-operations. Simulation results for benchmark circuits show that compared to LFSR reseeding using output deviations alone, the proposed method provides higher coverage for transition-delay and bridging faults, and steeper coverage ramp-up for these faults for the same number of seeds. For the same pattern count (and much fewer seeds), the proposed method provides comparable unmodeled defect coverage. In all cases, complete coverage of modeled stuck-at faults is obtained. We therefore conclude that high test quality can be obtained with the proposed LFSR reseeding method using a smaller number of seeds.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Nowadays, Systems-On-Chip are commonly equipped with reconfigurable hardware. The use of hybrid architectures based on a mixture of general purpose processors and reconfigurable components has gained importance across the scientific community allowing a significant improvement of computational performance. Along with the demand for performance, the great sensitivity of reconfigurable hardware devices to physical defects lead to the request of highly dependable and fault tolerant systems. This paper proposes an FPGA-based reconfigurable software architecture able to abstract the underlying hardware platform giving an homogeneous view of it. The abstraction mechanism is used to implement fault tolerance mechanisms with a minimum impact on the system performance.
{"title":"A FPGA-Based Reconfigurable Software Architecture for Highly Dependable Systems","authors":"S. Carlo, P. Prinetto, A. Scionti","doi":"10.1109/ATS.2009.53","DOIUrl":"https://doi.org/10.1109/ATS.2009.53","url":null,"abstract":"Nowadays, Systems-On-Chip are commonly equipped with reconfigurable hardware. The use of hybrid architectures based on a mixture of general purpose processors and reconfigurable components has gained importance across the scientific community allowing a significant improvement of computational performance. Along with the demand for performance, the great sensitivity of reconfigurable hardware devices to physical defects lead to the request of highly dependable and fault tolerant systems. This paper proposes an FPGA-based reconfigurable software architecture able to abstract the underlying hardware platform giving an homogeneous view of it. The abstraction mechanism is used to implement fault tolerance mechanisms with a minimum impact on the system performance.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125727160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose techniques to simultaneously reduce the switching activity and keeping the leakage current under check. The overall average switching activity reduction is 70.01% and reduction in leakage power is about 6.31%, the maximum being 99.33% in switching and 9.92% in leakage.
{"title":"Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption","authors":"Subhadip Kundu, S. K. Kumar, S. Chattopadhyay","doi":"10.1109/ATS.2009.35","DOIUrl":"https://doi.org/10.1109/ATS.2009.35","url":null,"abstract":"Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose techniques to simultaneously reduce the switching activity and keeping the leakage current under check. The overall average switching activity reduction is 70.01% and reduction in leakage power is about 6.31%, the maximum being 99.33% in switching and 9.92% in leakage.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125248455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, M. Fujita
In this paper, we propose a post-silicon debug framework utilizing high-level design description, which provides great advantage of comprehensibility and readability in analyzing erroneous behaviors for debugging complicated post-silicon errors. The framework consists of the following methods; mapping between high-level and RTL, extracting error-relevant portions, and rank them by the degree of relevance with the error. We also exhibit several experimental results to show its effectiveness.
{"title":"A Post-Silicon Debug Support Using High-Level Design Description","authors":"Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, M. Fujita","doi":"10.1109/ATS.2009.28","DOIUrl":"https://doi.org/10.1109/ATS.2009.28","url":null,"abstract":"In this paper, we propose a post-silicon debug framework utilizing high-level design description, which provides great advantage of comprehensibility and readability in analyzing erroneous behaviors for debugging complicated post-silicon errors. The framework consists of the following methods; mapping between high-level and RTL, extracting error-relevant portions, and rank them by the degree of relevance with the error. We also exhibit several experimental results to show its effectiveness.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shiue-Tsung Shen, Weihsing Liu, En-Hua Ma, C. Li, I. Cheng
This paper presents Very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8mm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10V) and very low voltage (7V), followed by a 200 second voltage stress at 30V. Seven unreliable CUT that escape nominal voltage (NV) testing are successfully caught by VLV testing and there is no CUT that is caught by NV testing but escapes VLV testing. The results indicate that VLV testing is more effective than NV testing in screening out unreliable a-Si TFT circuits.
{"title":"Very-Low-Voltage Testing of Amorphous Silicon TFT Circuits","authors":"Shiue-Tsung Shen, Weihsing Liu, En-Hua Ma, C. Li, I. Cheng","doi":"10.1109/ATS.2009.68","DOIUrl":"https://doi.org/10.1109/ATS.2009.68","url":null,"abstract":"This paper presents Very-low-voltage (VLV) testing for digital NMOS circuits based on amorphous silicon thin film transistor (a-Si TFT) technology. The proposed VLV testing is an economic alternative to burn-in because the former is non-destructive and can be easily performed on regular ATE in a short time. 140 circuits under test (CUT) of two different design styles are implemented in 8mm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10V) and very low voltage (7V), followed by a 200 second voltage stress at 30V. Seven unreliable CUT that escape nominal voltage (NV) testing are successfully caught by VLV testing and there is no CUT that is caught by NV testing but escapes VLV testing. The results indicate that VLV testing is more effective than NV testing in screening out unreliable a-Si TFT circuits.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124980311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don’t care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding.
{"title":"Extended Selective Encoding of Scan Slices for Reducing Test Data and Test Power","authors":"Jun Liu, Yinhe Han, Xiaowei Li","doi":"10.1109/ATS.2009.63","DOIUrl":"https://doi.org/10.1109/ATS.2009.63","url":null,"abstract":"Recently, selective encoding of scan slices is proposed to compress test data. This encoding technique, unlike many other compression techniques encoding all the bits, only encodes the target-symbol by specifying single bit index and copying group data. In this paper, we propose an extended selective encoding which presents two new techniques: flexible grouping strategy, X bits exploitation and filling strategy. Flexible grouping strategy is able to decrease the number of encoded groups to improve compression ratio. X bits exploitation and filling strategy can exploit a large number of don’t care bits to reduce testing power with no compression ratio loss. Experimental results show that the proposed technique needs less test data storage volume and reduces average weighted switching activity by 24.7%, peak weighted switching activity by 11.6% during scan shift compared to selective encoding.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116967940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, J. Mekkoth, Jinsong Liu, H. Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang
This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device’s defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.
{"title":"Logic BIST Architecture for System-Level Test and Diagnosis","authors":"J. Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, J. Mekkoth, Jinsong Liu, H. Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang","doi":"10.1109/ATS.2009.34","DOIUrl":"https://doi.org/10.1109/ATS.2009.34","url":null,"abstract":"This paper describes the logic built-in self-test (BIST) architecture for test and diagnosis of ASIC devices at the system level. The proposed architecture supports the at speed staggered launch-on-capture clocking scheme and includes novel features to further increase the device’s defect coverage, place-and-route ability, ease of debug and diagnosis, and reduce test power consumption. These features include equivalent clock merging for routing considerations, programmable shift modes for overheat considerations, configurable capture modes for yield loss and IR-drop considerations, as well as BIST signature diagnosis, masked-chain diagnosis, and one-chain diagnosis at the system level. Experimental results have successfully demonstrated the feasibility of using the proposed features for system-level test and diagnosis.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127737155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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