Xun Tang, Ruifeng Guo, Wu-Tung Cheng, S. Reddy, Yu Huang
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected cells is large. Experimental results on several industrial designs show the effectiveness of the proposed procedures in improving diagnostic resolution, reducing run times of test generation and also reducing the number of test patterns.
{"title":"On Improving Diagnostic Test Generation for Scan Chain Failures","authors":"Xun Tang, Ruifeng Guo, Wu-Tung Cheng, S. Reddy, Yu Huang","doi":"10.1109/ATS.2009.21","DOIUrl":"https://doi.org/10.1109/ATS.2009.21","url":null,"abstract":"In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-cycle scan test patterns. A diagnostic test generation flow to speed up diagnosis is proposed to address the issue of long run times of test generation and large number of test patterns for the cases where the range of suspected cells is large. Experimental results on several industrial designs show the effectiveness of the proposed procedures in improving diagnostic resolution, reducing run times of test generation and also reducing the number of test patterns.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114070178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number of stuck-at fault pairs it distinguishes. We use the static test compaction process as part of a process that constructs the transparent-scan sequence gradually, using test compaction to prevent the length of the sequence from becoming unnecessarily long.
{"title":"Fault Diagnosis under Transparent-Scan","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.2009.12","DOIUrl":"https://doi.org/10.1109/ATS.2009.12","url":null,"abstract":"Transparent-scan provides opportunities for test compaction that do not exist with the conventional test application scheme for scan circuits. However, test compaction can reduce the ability of a transparent-scan sequence to diagnose faults. We describe a static test compaction procedure that reduces the length of a transparent-scan sequence while maintaining its stuck-at fault coverage and the number of stuck-at fault pairs it distinguishes. We use the static test compaction process as part of a process that constructs the transparent-scan sequence gradually, using test compaction to prevent the length of the sequence from becoming unnecessarily long.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132388018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Except for regular arrays, yield enhancement for high performance VLSI systems is usually addressed at the physical layers rather than at the architectural level. In addition, pipelines are prevalent in many SoC architectures. In this paper we present new architectural approaches and results to improve the yield and yield/area of pipelines by using redundancy and steering logic . We present a procedure of time complexity O(n) that finds the minimal number of switches to insert within an n-stage redundant pipeline of order q to improve yield. Experimental results indicate that for parameter values of interests, this procedure also improves the yield/area of the pipeline, especially when the yields for some modules are low.
除常规阵列外，高性能超大规模集成电路系统的良率提升通常在物理层而非架构层进行。此外，流水线在许多 SoC 架构中十分普遍。在本文中，我们介绍了通过使用冗余和转向逻辑提高流水线良率和良率/面积的新架构方法和结果。我们提出了一个时间复杂度为 O(n)的程序，该程序能找到在一个阶数为 q 的 n 级冗余流水线中插入开关的最小数量，从而提高良率。实验结果表明，对于相关参数值，该程序还能提高流水线的产量/面积，尤其是当某些模块的产量较低时。
{"title":"SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement","authors":"M. Mirza-Aghatabar, M. Breuer, S. Gupta","doi":"10.1109/ATS.2009.40","DOIUrl":"https://doi.org/10.1109/ATS.2009.40","url":null,"abstract":"Except for regular arrays, yield enhancement for high performance VLSI systems is usually addressed at the physical layers rather than at the architectural level. In addition, pipelines are prevalent in many SoC architectures. In this paper we present new architectural approaches and results to improve the yield and yield/area of pipelines by using redundancy and steering logic . We present a procedure of time complexity O(n) that finds the minimal number of switches to insert within an n-stage redundant pipeline of order q to improve yield. Experimental results indicate that for parameter values of interests, this procedure also improves the yield/area of the pipeline, especially when the yields for some modules are low.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129173369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chip quality is becoming more difficult to maintain as the process geometry shrinks. Not only is design complexity higher, but new defect types cause DPM (defects per million) to increase. At the same time, the amount of embedded memory in many applications continues to grow, making memory testing a key factor in maintaining low cost and high quality in IC manufacturing. While commercial EDA tools are keeping pace with the need for greater test flow automation, new test algorithms are also needed to minimize the rate of field returns at advanced technology nodes. This paper describes how ASIC vendors can develop customized memory test algorithms to enhance their overall IC testing strategy.
{"title":"Customized Algorithms for High Performance Memory Test in Advanced Technology Node","authors":"S. Chen, N. Huang, Ting-Pu Tai, Actel Niu","doi":"10.1109/ATS.2009.41","DOIUrl":"https://doi.org/10.1109/ATS.2009.41","url":null,"abstract":"Chip quality is becoming more difficult to maintain as the process geometry shrinks. Not only is design complexity higher, but new defect types cause DPM (defects per million) to increase. At the same time, the amount of embedded memory in many applications continues to grow, making memory testing a key factor in maintaining low cost and high quality in IC manufacturing. While commercial EDA tools are keeping pace with the need for greater test flow automation, new test algorithms are also needed to minimize the rate of field returns at advanced technology nodes. This paper describes how ASIC vendors can develop customized memory test algorithms to enhance their overall IC testing strategy.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129426018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An at-speed scan test methodology is proposed for the purpose of the timing optimization and calibration. The proposed method, called TOC-ATPG, addresses both undertesting and overtesting issues of the traditional at-speed scan-based structural test. A pseudo-random pattern-based circuit analysis is first applied to analyze the potential glitches and transitions due to the functional illegal states. A list of state elements to be constrained during ATPG to prevent the sensitization of the functional illegal transitions and glitches are derived. During ATPG the derived constraints are applied to prevent overtesting, and timing-aware transition fault approach is used simultaneously to detect the fault through the timing critical paths to overcome the undertesting issue. The proposed method demonstrates very high correlation to the purely sequential test in functional mode with bounded run time overhead and can be applied to very large design.
{"title":"At-Speed Scan Test Method for the Timing Optimization and Calibration","authors":"Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng","doi":"10.1109/ATS.2009.29","DOIUrl":"https://doi.org/10.1109/ATS.2009.29","url":null,"abstract":"An at-speed scan test methodology is proposed for the purpose of the timing optimization and calibration. The proposed method, called TOC-ATPG, addresses both undertesting and overtesting issues of the traditional at-speed scan-based structural test. A pseudo-random pattern-based circuit analysis is first applied to analyze the potential glitches and transitions due to the functional illegal states. A list of state elements to be constrained during ATPG to prevent the sensitization of the functional illegal transitions and glitches are derived. During ATPG the derived constraints are applied to prevent overtesting, and timing-aware transition fault approach is used simultaneously to detect the fault through the timing critical paths to overcome the undertesting issue. The proposed method demonstrates very high correlation to the purely sequential test in functional mode with bounded run time overhead and can be applied to very large design.","PeriodicalId":106283,"journal":{"name":"2009 Asian Test Symposium","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129607452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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