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2014 26th International Conference on Microelectronics (ICM)最新文献

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Quasi seven-level operation of multilevel converters with selective harmonic elimination 具有选择性谐波消除的多电平变换器的准七电平运行
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071845
M. G. Fakhry, A. Massoud, S. Ahmed
Generally, selective harmonic elimination (SHE) complexity for multilevel inverters increases with the increase in number of levels. In this paper, a novel approach for SHE is introduced. This approach is based on cancelling the 5th and 7th order harmonics irrelevant of the number of levels in three-phase multilevel converters, such that the solution for the angles required for the proposed SHE mimics that of the seven-level inverter (i.e. quasi seven-level operation of an n-level converter). The advantages of the proposed SHE approach are the simplicity in format and independency of number of levels. The proposed approach can be extended for more of low order harmonic cancellation. A method to obtain initial values for the SHE equations according to the reference modulation index M is proposed and investigated thoroughly. Compared with existing methods, the proposed method does not involve complex equation groups and is easier to be utilized in the case of a large number of switching angles, or multiple switching angles per voltage level in multilevel inverters. A 17-level cascaded inverter with different modulation indices working in Quasi Seven-Level Operation is considered as an example to validate the proposed concept. Simulations using MATLAB/SIMULINK platform has been conducted to validate the proposed concept.
一般来说,多电平逆变器的选择性谐波消除(SHE)复杂性随着电平数的增加而增加。本文介绍了一种新的SHE方法。这种方法是基于消除与三相多电平变换器中电平数无关的5阶和7阶谐波,这样,所提出的SHE所需的角度的解决方案模拟了七电平逆变器的角度(即n电平变换器的准七电平操作)。所提出的SHE方法的优点是格式简单,层数独立。该方法可以推广到更多的低阶谐波对消。提出了一种根据参考调制指数M求SHE方程初值的方法,并对其进行了深入的研究。与现有方法相比,该方法不涉及复杂的方程组,在多电平逆变器中开关角较多或每个电压电平有多个开关角的情况下更易于使用。以准七电平工作的17电平不同调制指标级联逆变器为例,验证了所提概念。利用MATLAB/SIMULINK平台进行了仿真以验证所提出的概念。
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引用次数: 7
A multi-sensing reconfigurable platform for gas applications 用于气体应用的多传感可重构平台
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071828
M. Akbar, Amine Ait Si Ali, A. Amira, M. Benammar, F. Bensaali, Saqib Mohamad, Fang Tang, A. Bermak, Mohamed Zgaren, M. Sawan
The production of hazardous gases due to different physicochemical reactions in gas industries have raised the need of autonomous sensor tag. However the adaptation of remotely controlled sensor tag is still suffering with many challenges, among which power consumption, selectivity and durability are the most prominent problems in gas application. Therefore in this paper, a reconfigurable multi-sensing platform is presented for gas applications. A low power ring-oscillator based temperature and tin-oxide based gas sensors are utilized to indicate the temperature and type of the gas with a total power of few μW's. The processing unit is designed on a heterogeneous ZynQ platform and a passive radio frequency identification (RFID) tag is designed to provide communication between the sensors and the processing unit.
气体工业中由于不同的物理化学反应而产生的有害气体提出了对自主传感器标签的需求。然而,远程控制传感器标签的自适应仍然面临着许多挑战,其中功耗、选择性和耐用性是气体应用中最突出的问题。因此,本文提出了一种可重构的气体多传感平台。采用低功率环振温度传感器和氧化锡气体传感器来指示气体的温度和类型,总功率为几μW。处理单元设计在异构ZynQ平台上,无源射频识别(RFID)标签设计用于在传感器和处理单元之间提供通信。
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引用次数: 4
High performance charge plasma based multi zone lateral bipolar junction transistor 基于高性能电荷等离子体的多区横向双极结晶体管
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071796
S. Loan, F. Bashir, M. Rafat, S. A. Abbasi, A. Alamoud
In this paper, we propose a new structure of a lateral bipolar junction transistor (LBJT) on silicon on insulator (SOI), employing multi zone collector drift region. The novelty of the device is the use of charge plasma concept to realize emitter, base and multi zone collector drift regions. Here metals of different work functions are used to realize these regions instead of conventional doping methods of diffusion and ion implantation. The numerical simulation of the proposed multi zone charge plasma LBJT (MZCP-LBJT) on SOI has been performed and the key characteristics have been compared with the conventionally doped LBJT (CD-LBJT) on SOI. A significant improvement in the ON current (ION), current gain, cutoff frequency (fT) and breakdown voltage has been observed in the proposed device. It has been observed that current gain increases by ~ 20 times and ION by 10 times in the proposed device. Further, by using an optimized gap between the collector and base regions, a 34% increase in fT is achieved in the proposed device. Furthermore, the proposed device does not face doping related issues and the requirement of high temperature processing is absent, as it uses charge plasma concept to realize different regions, instead of the conventional doping methods.
本文提出了一种利用多区集电极漂移区在绝缘体硅(SOI)上的横向双极结晶体管(LBJT)结构。该器件的新颖之处在于利用电荷等离子体的概念来实现发射极、基极和多区集电极漂移区。本文采用不同功函数的金属代替传统的扩散和离子注入的掺杂方法来实现这些区域。本文对所提出的多区电荷等离子体LBJT (MZCP-LBJT)在SOI上进行了数值模拟,并与常规掺杂LBJT (CD-LBJT)在SOI上的关键特性进行了比较。该器件在导通电流(ION)、电流增益、截止频率(fT)和击穿电压方面均有显著改善。结果表明,该器件的电流增益提高了20倍,离子增益提高了10倍。此外,通过在集电极和基极区域之间使用优化的间隙,在所提出的器件中实现了34%的fT增加。此外,该器件采用电荷等离子体概念实现不同区域,而不是传统的掺杂方法,不存在掺杂相关问题,也不需要高温处理。
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引用次数: 0
Haralick features for GEI-based human gait recognition 基于gei的人类步态识别的Haralick特征
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071800
Ait O. Lishani, L. Boubchir, A. Bouridane
This paper proposes a supervised feature extraction method which is able to select discriminative features for human gait recognition under the variations of clothing and carrying conditions and hence to improve the recognition performances. The proposed method is based on the use of Haralick's texture features extracted locally from three regions of Gait Energy Images. The performance has been evaluated using CASIA Gait database (dataset B). The experimental using one-against-all SVM classifier yields attractive results when compared to existing and similar techniques.
本文提出了一种有监督特征提取方法,该方法能够在不同的服装和携带条件下选择具有区别性的特征进行步态识别,从而提高识别性能。该方法基于从步态能量图像的三个区域局部提取的Haralick纹理特征。使用CASIA步态数据库(数据集B)对性能进行了评估。与现有的和类似的技术相比,使用单对全SVM分类器的实验产生了有吸引力的结果。
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引用次数: 15
A 0.6-V/1.2-V low power single ended CMOS LNA for multi-standard RF front-ends 用于多标准射频前端的0.6 v /1.2 v低功耗单端CMOS LNA
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071808
A. Slimane, Sid-Ahmed Tedjini-Bailiche, A. Taibi, M. Belaroussi, D. Maafri
This paper presents a design of a low power single ended CMOS LNA for reconfigurable applications including GPS, GSM (DCS1800, PCS1900), 3G (UMTS), WLAN b/g and LTE. Based on a wideband input matching, the LNA stages cover all band of interest while achieving a good trade-off between high gain, low noise figure and low power consumption. For multi-standard aim, the LNA selects the desired bands using a high output resonant impedance with a switching technique. Implemented in 0.13-μm CMOS technology, the simulated LNA results at Vdd = 1.2 V perform a power gain higher than 30 dB, a noise figure below 2.3 dB, an input return loss less than -12 dB, and an IIP3 better than -19 dBm in frequency band 1.5-2.6 GHz. Besides, for the low mode at Vdd = 0.6 V, the power gain is better than 19 dB and the noise figure is about 2.9 dB. For all mentioned standards, the proposed LNA consumes 7.5 mW and 2.7 mW from supply voltage of 1.2 V and 0.6 V, respectively.
本文设计了一种低功耗单端CMOS LNA,可用于GPS、GSM (DCS1800、PCS1900)、3G (UMTS)、WLAN b/g和LTE等可重构应用。基于宽带输入匹配,LNA级覆盖所有感兴趣的频带,同时实现高增益、低噪声和低功耗之间的良好权衡。对于多标准瞄准,LNA使用高输出谐振阻抗和开关技术选择所需的频段。采用0.13 μm CMOS技术实现的仿真LNA在Vdd = 1.2 V时的功率增益高于30 dB,噪声系数低于2.3 dB,输入回波损耗小于-12 dB,在1.5 ~ 2.6 GHz频段的IIP3优于-19 dBm。此外,在Vdd = 0.6 V的低模式下,功率增益优于19 dB,噪声系数约为2.9 dB。对于上述所有标准,建议的LNA分别从1.2 V和0.6 V的电源电压消耗7.5 mW和2.7 mW。
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引用次数: 5
Automatic mapping of AF3 specifications to ARM cortex-M based FRDM platfrom AF3规范自动映射到基于ARM cortex-M的FRDM平台
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071849
Mohammadhossein Askarihemmat, O. Mohamed, M. Boukadoum
A new rapid prototyping methodology for embedded system application is introduced. The proposed methodology uses AutoFOCUS3(AF3), which is a model-based development tool for distributed, reactive, embedded software systems, to generate an executable C code for ARM Cortex-M family processors from the verified model. This methodology provides a clean and clear relation between a high-level model and its low-level executable C-code for the target platform. To execute a model on a target platform, the model needs to be accurately translated, and the translation must be based on the hardware resources. In this respect, this work aims to close the gap between high level description and the implementation. As a case study, using the proposed methodology, we implemented a self stabilizing distributed clock synchronization protocol on a FRDM platform.
介绍了一种新的嵌入式系统快速成型方法。提出的方法使用AutoFOCUS3(AF3),这是一种基于模型的开发工具,用于分布式、响应式、嵌入式软件系统,从经过验证的模型中为ARM Cortex-M系列处理器生成可执行的C代码。这种方法在高级模型和目标平台的低级可执行c代码之间提供了一种清晰的关系。要在目标平台上执行模型,需要对模型进行准确的翻译,并且翻译必须基于硬件资源。在这方面,本工作旨在缩小高层次描述与实现之间的差距。作为一个案例研究,我们使用提出的方法,在FRDM平台上实现了一个自稳定的分布式时钟同步协议。
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引用次数: 1
Agile hierarchical cluster structure-based cooperative spectrum sensing in cognitive radio networks 基于敏捷层次聚类结构的认知无线电网络协同频谱感知
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071803
Faroq A. Awin, E. Abdel-Raheem, M. Ahmadi
Striking a balance between detection performance and overhead in cooperative spectrum sensing is a very critical design factor. For a conventional cluster-based spectrum sensing (CBSS) algorithms, all cognitive radios (CRs) in one cluster forward their local decisions through only one channel which leads to incur large sensing overhead. In this work the multi-levels hierarchical cluster-based spectrum sensing (MH-CBSS) algorithm is used to investigate sensing agility and total energy consumption. Simulation results show that the MHCBSS algorithm provides higher sensing agility and consumes less energy than that consumed by the conventional CBSS algorithm.
在协同频谱感知中,在检测性能和开销之间取得平衡是一个非常关键的设计因素。对于传统的基于集群的频谱感知算法,一个集群中的所有认知无线电(CRs)只通过一个信道转发它们的局部决策,这导致了巨大的感知开销。本文采用基于多层分层聚类的频谱感知(MH-CBSS)算法来研究感知的敏捷性和总能耗。仿真结果表明,与传统的CBSS算法相比,MHCBSS算法具有更高的感知敏捷性和更低的能量消耗。
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引用次数: 7
Improved gait recognition based on gait energy images 基于步态能量图像的改进步态识别
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071801
Imad Rida, Somaya Almaadeed, A. Bouridane
The performance of gait recognition systems are usually affected by clothing, carrying conditions, and other intraclass variations which are also referred to as "covariates". This paper proposes a supervised feature selection method which is able to select relevant features for human recognition to mitigate the impact of covariates and hence improve the recognition performance. The proposed method is evaluated using CASIA Gait Database (Dataset B) and the experimental results suggest that our method yields attractive results when compared to similar ones.
步态识别系统的性能通常受到服装、携带条件和其他类内变化的影响,这些变化也被称为“协变量”。本文提出了一种有监督的特征选择方法,该方法能够选择人类识别的相关特征,以减轻协变量的影响,从而提高识别性能。使用CASIA步态数据库(数据集B)对该方法进行了评估,实验结果表明,与同类方法相比,我们的方法获得了令人满意的结果。
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引用次数: 13
A 4-bit 6GS/s time-based analog-to-digital converter 一个4位6GS/s基于时间的模数转换器
Pub Date : 2014-12-01 DOI: 10.1109/ICM.2014.7071814
Assem Hussein, Mahmoud Fawzy, M. Ismail, Mohamed Refky, H. Mostafa
This paper proposes a 4-bit 6GS/s Time-Based Analog-to-Digital Converter (TADC) to be integrated inside the Software Defined Radio (SDR) receivers. The TADC is mainly composed of two blocks which are the Voltage-to-Time Converter (VTC) and the Time-to-Digital Converter (TDC). A prototype of the proposed TADC is implemented using 65 nm technology with a sampling rate of 6GS/s. An ENOB of 3.68 is achieved for an input frequency of 1.331 GHz. The whole system consumes a total power of 21.4 mW.
本文提出了一种集成在软件定义无线电(SDR)接收机内的4位6GS/s时基模数转换器(TADC)。TDC主要由电压-时间转换器(VTC)和时间-数字转换器(TDC)两个模块组成。采用65nm技术实现了该tdac的原型,采样率为6GS/s。当输入频率为1.331 GHz时,ENOB值为3.68。整个系统的总功耗为21.4 mW。
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引用次数: 3
Efficient relocation of variable-sized hardware tasks for FPGA-based adaptive systems 基于fpga的自适应系统中可变大小硬件任务的有效重定位
Pub Date : 2014-10-14 DOI: 10.1109/ICM.2014.7071847
M. Hannachi, H. Rabah, S. Jovanovic, A. B. Abdelali, A. Mtibaa
Adaptive systems based on FPGA architectures can benefit greatly from the high degree of flexibility offered by Dynamic partial reconfiguration (DPR). Thanks to DPR, hardware tasks composing an adaptive system can be allocated and relocated on demand or depending on the dynamically changing environment. The limitations in the existing tools provided by major FPGA manufacturers do not allow an efficient placement and relocation of variable-sized hardware tasks. This paper presents a design method for relocation of variable-sized hardware task on SRAM-based FPGAs for adaptive systems using dynamic partial reconfiguration (DPR). The proposed relocation procedure takes into account the communication between different reconfigurable regions and static region. This work gives a detailed description of the proposed partial bitsream relocation of variable-sized hardware tasks targeting the Virtex-5 FPGAs.
基于FPGA架构的自适应系统可以从动态部分重构(DPR)提供的高度灵活性中受益匪浅。由于DPR,组成自适应系统的硬件任务可以根据需要或根据动态变化的环境进行分配和重新定位。主要FPGA制造商提供的现有工具的局限性不允许有效地放置和重新定位可变大小的硬件任务。提出了一种基于sram的自适应系统fpga上可变大小硬件任务的动态部分重构设计方法。所提出的重新定位过程考虑了不同可重构区域和静态区域之间的通信。这项工作给出了针对Virtex-5 fpga的可变大小硬件任务的部分位流重定位的详细描述。
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引用次数: 5
期刊
2014 26th International Conference on Microelectronics (ICM)
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