Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071791
A. Senouci, Ilyas Benkhaddra, A. Boukabou, A. Bouridane, A. Ouslimani
The use of rapid prototyping tools such as MATLAB Simulink and Xilinx System Generator becomes increasingly important because of time-to-market constraints. In this paper, we consider Xilinx System Generator for software simulation and real time implementation on FPGA circuit of a pseudo-random number generator (PRNG) based on unified hyperchaotic system. For this purpose, we propose a new PRNG with good randomness characteristics based on a novel conception where a parameter perturbation control to the input and a special function to the output are used in order to drive the unified hyperchaotic system to the PRNG. The design was implemented targeting a Virtex-5 FPGA device (XC5VFX70T- 1FFG1136).
由于上市时间的限制，使用快速原型工具(如MATLAB Simulink和Xilinx System Generator)变得越来越重要。本文采用Xilinx System Generator对基于统一超混沌系统的伪随机数发生器(PRNG)进行软件仿真，并在FPGA电路上实时实现。为此，我们提出了一种新的PRNG，该PRNG基于一种新的概念，即对输入使用参数摄动控制，对输出使用特殊函数来驱动统一超混沌系统到PRNG。该设计是针对Virtex-5 FPGA器件(XC5VFX70T- 1FFG1136)实现的。
{"title":"Implementation and evaluation of a new unified hyperchaos-based PRNG","authors":"A. Senouci, Ilyas Benkhaddra, A. Boukabou, A. Bouridane, A. Ouslimani","doi":"10.1109/ICM.2014.7071791","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071791","url":null,"abstract":"The use of rapid prototyping tools such as MATLAB Simulink and Xilinx System Generator becomes increasingly important because of time-to-market constraints. In this paper, we consider Xilinx System Generator for software simulation and real time implementation on FPGA circuit of a pseudo-random number generator (PRNG) based on unified hyperchaotic system. For this purpose, we propose a new PRNG with good randomness characteristics based on a novel conception where a parameter perturbation control to the input and a special function to the output are used in order to drive the unified hyperchaotic system to the PRNG. The design was implemented targeting a Virtex-5 FPGA device (XC5VFX70T- 1FFG1136).","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121730088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071843
H. M. El-Deeb, A. Massoud, A. Elserougi, A. Abdel-Khalik, S. Ahmed
The control of power electronic converters is subjected to several challenges as measurement sensors drift, malfunction in harsh environments, non-ideal grid, and performance degradation due to the delay of discrete control systems. In this paper, a stationary frame resonant current controller for inverter-based distributed generation (IBDG) with sensor-less grid voltage operation is proposed. The delay sources are taken into account and compensated. The proposed approach is simulated through Matlab/Simulink and verified experimentally.
{"title":"Voltage sensorless current control of low power inverter-based distributed generation systems","authors":"H. M. El-Deeb, A. Massoud, A. Elserougi, A. Abdel-Khalik, S. Ahmed","doi":"10.1109/ICM.2014.7071843","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071843","url":null,"abstract":"The control of power electronic converters is subjected to several challenges as measurement sensors drift, malfunction in harsh environments, non-ideal grid, and performance degradation due to the delay of discrete control systems. In this paper, a stationary frame resonant current controller for inverter-based distributed generation (IBDG) with sensor-less grid voltage operation is proposed. The delay sources are taken into account and compensated. The proposed approach is simulated through Matlab/Simulink and verified experimentally.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123921196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071848
Ryan M. Gibson, A. Amira, P. Casaseca-de-la-Higuera, N. Ramzan, Zeeshan Pervez
Falling can cause significant injury, where quick medical response and fall information are critical to providing aid. In this paper we present a wearable wireless fall detection system utilising a Shimmer accelerometer device, where important additional information is obtained, such as direction and strength of the occurred fall instance. Discrete Wavelet Transforms and multiresolution wavelet analysis are used to accurately determine fall occurrence and additionally determine the strength of the fall. The wavelet signal is additionally evaluated with Principal Component Analysis to generate a decision tree classifier for fall occurrence, strength and direction. Test subjects undertook fall and Activities of Daily Living experiments to generate data for wavelet and Principal Component Analysis. The presented fall detection and diagnostic system obtained highly accurate and robust fall detection with both methods, while the decision tree strength analysis demonstrated a better fall strength response.
{"title":"An efficient user-customisable multiresolution classifier fall detection and diagnostic system","authors":"Ryan M. Gibson, A. Amira, P. Casaseca-de-la-Higuera, N. Ramzan, Zeeshan Pervez","doi":"10.1109/ICM.2014.7071848","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071848","url":null,"abstract":"Falling can cause significant injury, where quick medical response and fall information are critical to providing aid. In this paper we present a wearable wireless fall detection system utilising a Shimmer accelerometer device, where important additional information is obtained, such as direction and strength of the occurred fall instance. Discrete Wavelet Transforms and multiresolution wavelet analysis are used to accurately determine fall occurrence and additionally determine the strength of the fall. The wavelet signal is additionally evaluated with Principal Component Analysis to generate a decision tree classifier for fall occurrence, strength and direction. Test subjects undertook fall and Activities of Daily Living experiments to generate data for wavelet and Principal Component Analysis. The presented fall detection and diagnostic system obtained highly accurate and robust fall detection with both methods, while the decision tree strength analysis demonstrated a better fall strength response.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129474067","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071841
Muhammad Hassan, A. Bermak, Amine Ait Si Ali, A. Amira
Recently, implementation friendly bio-inspired coding schemes have been developed for an electronic nose system to recognise different gases. In these schemes, a logarithmic time-domain encoding technique is used to covert the response vector of the sensor array in an electronic nose into a latency pattern. These schemes assume a unique temporal sequence of latencies, referred to as a rank order, for each target gas. However, poor repeatability and sensor drift limit the performance of these schemes. In this paper, we use angular separation between the latency patterns of the sensor array for gas identification. An electronic nose system containing an array of commercially available gas sensors and a radio frequency module is developed and characterized in the laboratory environment with four gases. Experimental data is used to compare the performance of our coding scheme with existing bio-inspired coding schemes and commonly used pattern recognition algorithms.
{"title":"Gas identification in electronic nose by using similarity measure between latency patterns","authors":"Muhammad Hassan, A. Bermak, Amine Ait Si Ali, A. Amira","doi":"10.1109/ICM.2014.7071841","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071841","url":null,"abstract":"Recently, implementation friendly bio-inspired coding schemes have been developed for an electronic nose system to recognise different gases. In these schemes, a logarithmic time-domain encoding technique is used to covert the response vector of the sensor array in an electronic nose into a latency pattern. These schemes assume a unique temporal sequence of latencies, referred to as a rank order, for each target gas. However, poor repeatability and sensor drift limit the performance of these schemes. In this paper, we use angular separation between the latency patterns of the sensor array for gas identification. An electronic nose system containing an array of commercially available gas sensors and a radio frequency module is developed and characterized in the laboratory environment with four gases. Experimental data is used to compare the performance of our coding scheme with existing bio-inspired coding schemes and commonly used pattern recognition algorithms.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126871890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071830
L. Said, A. Radwan, A. Madian, A. Soliman
Most of electric circuits can be viewed as a two port network with two terminals defined as input and output ports. In this paper, two different concepts are combined together which are the two port network concept and the fractional calculus to design a general fractional order two port network with equal order. An oscillator case study with three impedances structure has been presented. The three impedances are two equal order fractional capacitors and a resistor. Two different two port network are studied which are Op-amp based circuit and nonideal gyrator circuit. The general oscillation frequency and condition for each case have been derived and discussed numerically using Matlab. Spice simulations are presented for some cases to validate the proposed idea where the fractional order oscillator has more degrees of freedom than the integer order.
{"title":"Fractional order two port network oscillator with equal order","authors":"L. Said, A. Radwan, A. Madian, A. Soliman","doi":"10.1109/ICM.2014.7071830","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071830","url":null,"abstract":"Most of electric circuits can be viewed as a two port network with two terminals defined as input and output ports. In this paper, two different concepts are combined together which are the two port network concept and the fractional calculus to design a general fractional order two port network with equal order. An oscillator case study with three impedances structure has been presented. The three impedances are two equal order fractional capacitors and a resistor. Two different two port network are studied which are Op-amp based circuit and nonideal gyrator circuit. The general oscillation frequency and condition for each case have been derived and discussed numerically using Matlab. Spice simulations are presented for some cases to validate the proposed idea where the fractional order oscillator has more degrees of freedom than the integer order.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134293451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071795
A. Meraoumia, S. Chitroub, A. Bouridane
Automatic personal identification has become an important issue in several applications, such as physical buildings and information systems. Nowadays, biometric techniques are an important and effective solution for automatic personal identification. One of the most popular biometric systems is based on the hand due to its ease of use. Hand has several modalities to be extracted, among them, Finger-Knuckle-Print (FKP) and PaLMprint (PLM), has attracted an increasing amount of attention. This paper investigates these modalities for elaborating an efficient multimodal biometric identification system. For that, the texture information of FKP and PLM is characterized by the Local Binary Pattern (LBP). During the matching phase, an Euclidian distance score is employed to measure the similarity between templates. The proposed system is tested and evaluated using a database of 165 users. Our experimental results show the effectiveness and reliability of the proposed system, which brings high identification accuracy rate.
{"title":"Robust human identity identification system by using hand biometric traits","authors":"A. Meraoumia, S. Chitroub, A. Bouridane","doi":"10.1109/ICM.2014.7071795","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071795","url":null,"abstract":"Automatic personal identification has become an important issue in several applications, such as physical buildings and information systems. Nowadays, biometric techniques are an important and effective solution for automatic personal identification. One of the most popular biometric systems is based on the hand due to its ease of use. Hand has several modalities to be extracted, among them, Finger-Knuckle-Print (FKP) and PaLMprint (PLM), has attracted an increasing amount of attention. This paper investigates these modalities for elaborating an efficient multimodal biometric identification system. For that, the texture information of FKP and PLM is characterized by the Local Binary Pattern (LBP). During the matching phase, an Euclidian distance score is employed to measure the similarity between templates. The proposed system is tested and evaluated using a database of 165 users. Our experimental results show the effectiveness and reliability of the proposed system, which brings high identification accuracy rate.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"101 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117278559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071821
Hadi Hayati, M. Ehsanian
This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI). Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH). In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total power consumption as well as design complexity and die area. Verifying functionality of proposed PI-based CRC, the circuit is designed and simulated in 0.18-μm CMOS technology. As simulation results show, the proposed CRC recovers clock at 5GHz in the first unit interval of input data where approximately 40% reduction in power dissipation is achieved. The circuit consumes 2.54mW power from a 1.8-V supply.
{"title":"Low-power burst-mode clock recovery circuit using analog phase interpolator","authors":"Hadi Hayati, M. Ehsanian","doi":"10.1109/ICM.2014.7071821","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071821","url":null,"abstract":"This paper proposes a novel low-power burst-mode clock recovery circuit (CRC) based on analog phase interpolator (PI). Accordingly, we employed a new configuration for PI-based CRC in which a novel architecture is utilized for double-edge triggered sample-and-hold (DT-SH). In the proposed DT-SH one buffer is shared between two single-edge triggered SH (ST-SH) resulting in great reduction of total power consumption as well as design complexity and die area. Verifying functionality of proposed PI-based CRC, the circuit is designed and simulated in 0.18-μm CMOS technology. As simulation results show, the proposed CRC recovers clock at 5GHz in the first unit interval of input data where approximately 40% reduction in power dissipation is achieved. The circuit consumes 2.54mW power from a 1.8-V supply.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123287156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071833
A. El-Samman, A. Radwan, A. Madian
This paper introduces the replacement of four and six resistors with four and six memristors at the same time for the modified single input Op-Amps oscillator. The full independency between the oscillation condition and the oscillation frequency facilitates the study. Mathematical analysis is provided for the double replacement of resistors with memristors. The whole range of operation of the memristor is taken in consideration and examined for all kind of replacements. Also, the poles of the system are presented while the existence of two, four and six memristors.
{"title":"Resistorless memristor based oscillator","authors":"A. El-Samman, A. Radwan, A. Madian","doi":"10.1109/ICM.2014.7071833","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071833","url":null,"abstract":"This paper introduces the replacement of four and six resistors with four and six memristors at the same time for the modified single input Op-Amps oscillator. The full independency between the oscillation condition and the oscillation frequency facilitates the study. Mathematical analysis is provided for the double replacement of resistors with memristors. The whole range of operation of the memristor is taken in consideration and examined for all kind of replacements. Also, the poles of the system are presented while the existence of two, four and six memristors.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126482927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071807
R. Krishnamurthy, M. Hashmi
In this paper, a crossover based delay mechanism accompanied with a circular vernier delay line architecture is proposed to measure path delays. Measurement of propagation delays on critical path with an on-chip circuit has the potential of detecting small delay defects even when the integrated circuit is in operation. The new architecture drastically reduces the count of delay stages to achieve a large measurement range without reducing the measurement resolution. It achieves a maximum range of 100ns at 5M samples/s with a resolution of 10ps, while consuming 8.21mW power and has an area of .023mm2 in 180nm CMOS technology.
{"title":"A low power, high dynamic range and area efficient cyclic on-chip delay measurement architecture","authors":"R. Krishnamurthy, M. Hashmi","doi":"10.1109/ICM.2014.7071807","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071807","url":null,"abstract":"In this paper, a crossover based delay mechanism accompanied with a circular vernier delay line architecture is proposed to measure path delays. Measurement of propagation delays on critical path with an on-chip circuit has the potential of detecting small delay defects even when the integrated circuit is in operation. The new architecture drastically reduces the count of delay stages to achieve a large measurement range without reducing the measurement resolution. It achieves a maximum range of 100ns at 5M samples/s with a resolution of 10ps, while consuming 8.21mW power and has an area of .023mm2 in 180nm CMOS technology.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128308969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071835
Hong Zhu, V. Kursun
Supply voltage scaling is a commonly used technique for saving energy in microprocessors. The scalability of power supply voltage is limited by the data stability and write ability requirements of SRAM cells in memory cache. Noise margins of memory cells shrink, thereby degrading reliability and causing failure at lower power supply voltages. A triple-threshold-voltage nine-transistor SRAM cell that is capable of reliable operation at ultra-low power supply voltage levels down to 390mV is presented in this paper. While offering comparable or higher data stability, the tri-Vt 9T SRAM array lowers the leakage power consumption, energy per read cycle, and energy per write cycle by up to 94.5%, 22.8%, and 34.5%, respectively, as compared to the conventional 6T SRAM arrays that operate at the nominal VDD = 1.2V in a TSMC 65nm CMOS technology.
{"title":"Triple-threshold-voltage 9-transistor SRAM cell for data stability and energy-efficiency at ultra-low power supply voltages","authors":"Hong Zhu, V. Kursun","doi":"10.1109/ICM.2014.7071835","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071835","url":null,"abstract":"Supply voltage scaling is a commonly used technique for saving energy in microprocessors. The scalability of power supply voltage is limited by the data stability and write ability requirements of SRAM cells in memory cache. Noise margins of memory cells shrink, thereby degrading reliability and causing failure at lower power supply voltages. A triple-threshold-voltage nine-transistor SRAM cell that is capable of reliable operation at ultra-low power supply voltage levels down to 390mV is presented in this paper. While offering comparable or higher data stability, the tri-Vt 9T SRAM array lowers the leakage power consumption, energy per read cycle, and energy per write cycle by up to 94.5%, 22.8%, and 34.5%, respectively, as compared to the conventional 6T SRAM arrays that operate at the nominal VDD = 1.2V in a TSMC 65nm CMOS technology.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130481064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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