Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071798
F. Larbi, S. Oussalah, N. Belkhelfa, A. Lounis
This paper presents a new approach of designing a n-in-n ATLAS pixel sensor shape inspired form golden ratio by using the golden ratio in the design of the multi guard rings structure. A new configuration is proposed in the goal of optimizing its layout parameter. The performance of the optimized guard rings structure is evaluated with TCAD simulation. It's shown that the optimized structure related to the guard ring designed with the golden ration leads to the high breakdown voltage. The breakdown behavior of the guard ring structure is studied as a function of the golden ration applied to the guard ring parameters, like the width implant, metal width and overhang.
{"title":"Pixel sensor guard-ring geometry optimization by TCAD simulation","authors":"F. Larbi, S. Oussalah, N. Belkhelfa, A. Lounis","doi":"10.1109/ICM.2014.7071798","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071798","url":null,"abstract":"This paper presents a new approach of designing a n-in-n ATLAS pixel sensor shape inspired form golden ratio by using the golden ratio in the design of the multi guard rings structure. A new configuration is proposed in the goal of optimizing its layout parameter. The performance of the optimized guard rings structure is evaluated with TCAD simulation. It's shown that the optimized structure related to the guard ring designed with the golden ration leads to the high breakdown voltage. The breakdown behavior of the guard ring structure is studied as a function of the golden ration applied to the guard ring parameters, like the width implant, metal width and overhang.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127284207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071815
Ali H. Hassan, Maged Ali, Nabil Mohammed, Ahmed M. A. Ali, Mohammed Hassoubh, M. Wagih Ismail, M. Refky, H. Mostafa
Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing systems, software defined radio receivers, and biomedical systems. This paper introduces a 6-bit Delay Line based Analog to Digital Converter (DL-ADC). This DL-ADC utilizes an inherited sample and hold technique to eliminate the dedicated power hungry sample and hold circuit. A prototype of the proposed DL-ADC is implemented in 65nm CMOS technology, where it consumes 1.8 mW and achieves a maximum SNDR of 35.5 dB with sampling rate 500 MHZ with a corresponding Figure of Merit (FOM) of 74.22 fJ/step.
{"title":"A 500 MS/s 6 bits delay line ADC with inherit sample & hold","authors":"Ali H. Hassan, Maged Ali, Nabil Mohammed, Ahmed M. A. Ali, Mohammed Hassoubh, M. Wagih Ismail, M. Refky, H. Mostafa","doi":"10.1109/ICM.2014.7071815","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071815","url":null,"abstract":"Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing systems, software defined radio receivers, and biomedical systems. This paper introduces a 6-bit Delay Line based Analog to Digital Converter (DL-ADC). This DL-ADC utilizes an inherited sample and hold technique to eliminate the dedicated power hungry sample and hold circuit. A prototype of the proposed DL-ADC is implemented in 65nm CMOS technology, where it consumes 1.8 mW and achieves a maximum SNDR of 35.5 dB with sampling rate 500 MHZ with a corresponding Figure of Merit (FOM) of 74.22 fJ/step.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128003087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071816
A. Hayek, Bashier Machmur, M. Schreiber, J. Börcsök
In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. Furthermore, a SIL3 operating system and a SIL3 middleware are also briefly presented in this paper. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions that are ready for certification.
{"title":"Embedded safety on a chip for SIL3 applications","authors":"A. Hayek, Bashier Machmur, M. Schreiber, J. Börcsök","doi":"10.1109/ICM.2014.7071816","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071816","url":null,"abstract":"In this paper a complete safety controller on a single chip is introduced. The presented chip is a comprehensive solution that includes a certified application specific integrated circuit for safety-critical applications according to the safety standard IEC 61508, meeting the safety integrity level SIL3. Furthermore, a SIL3 operating system and a SIL3 middleware are also briefly presented in this paper. Based on the presented solution, the smallest certified safety controller represents an innovative product and allows system manufacturers to create safe solutions that are ready for certification.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132744883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071792
Marwa Abdallah, H. Mostafa, Mohamed Fathy
The missing fourth passive circuit element, the memristor, attracted a great attention when HP labs developed the first real memristor device in 2008. The memristor manufacturing is facing various challenges due to the difficulty to control its process variation, as it is fabricated at nano-scale geometry's size. Process variation result in deviating the actual electrical behavior of memristors from the desired values. This deviation results in reducing the yield especially in the memristor-based memory design. Therefore, it is very important to understand and characterize the impact of process variation on memristor performance and yield and attempt to maximize the yield of the memristor-based memory arrays.
{"title":"Yield maximization of TiO2>/sub> memristor-based memory arrays","authors":"Marwa Abdallah, H. Mostafa, Mohamed Fathy","doi":"10.1109/ICM.2014.7071792","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071792","url":null,"abstract":"The missing fourth passive circuit element, the memristor, attracted a great attention when HP labs developed the first real memristor device in 2008. The memristor manufacturing is facing various challenges due to the difficulty to control its process variation, as it is fabricated at nano-scale geometry's size. Process variation result in deviating the actual electrical behavior of memristors from the desired values. This deviation results in reducing the yield especially in the memristor-based memory design. Therefore, it is very important to understand and characterize the impact of process variation on memristor performance and yield and attempt to maximize the yield of the memristor-based memory arrays.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130402187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071837
Wafa El-Tarhouni, M. Shaikh, L. Boubchir, A. Bouridane
Local Binary Pattern (LBP) has been widely used for analyzing local texture features of an image. Several new extensions of LBP based texture descriptors have been proposed, focusing on improving the robustness to noise by using different encoding or thresholding schemes where the most widely known are Median Binary Patterns (MBP), Fuzzy LBP (FLBP), Local Quantized Patterns (LQP), and Shift LBP (SLBP). LBP based descriptors are rarely applied in Finger-Knuckle-Print (FKP) recognition and especially, SLBP-based descriptors has not been reported yet. In this paper we propose using the Multi-scale Shift Binary Pattern (MSLBP) descriptor which extends the original SLBP to multi-scale to get more robust and discriminative representation of FKP features. The classification of this new proposed feature is performed by using Principle Component Analysis and Random subspace Linear Discriminant Analysis and the results suggest that they outperform other classifiers in FKP recognition. Experiments are performed using the PolyU FKP database and the results obtained have shown that the proposed FKP recognition method achieves outstanding rank-1 recognition rate up to 95% compared to the state-of-the-art FKP approaches.
{"title":"Multi-scale shift local binary pattern based-descriptor for finger-knuckle-print recognition","authors":"Wafa El-Tarhouni, M. Shaikh, L. Boubchir, A. Bouridane","doi":"10.1109/ICM.2014.7071837","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071837","url":null,"abstract":"Local Binary Pattern (LBP) has been widely used for analyzing local texture features of an image. Several new extensions of LBP based texture descriptors have been proposed, focusing on improving the robustness to noise by using different encoding or thresholding schemes where the most widely known are Median Binary Patterns (MBP), Fuzzy LBP (FLBP), Local Quantized Patterns (LQP), and Shift LBP (SLBP). LBP based descriptors are rarely applied in Finger-Knuckle-Print (FKP) recognition and especially, SLBP-based descriptors has not been reported yet. In this paper we propose using the Multi-scale Shift Binary Pattern (MSLBP) descriptor which extends the original SLBP to multi-scale to get more robust and discriminative representation of FKP features. The classification of this new proposed feature is performed by using Principle Component Analysis and Random subspace Linear Discriminant Analysis and the results suggest that they outperform other classifiers in FKP recognition. Experiments are performed using the PolyU FKP database and the results obtained have shown that the proposed FKP recognition method achieves outstanding rank-1 recognition rate up to 95% compared to the state-of-the-art FKP approaches.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133154891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071802
A. Sohrabi, M. Ehsanian
This paper forcuese on a low phase noise LC-VCO based PLL using CP-AAC circuit for output amplitude control. A wide tuning range (2.796GHz-3.86GHz) is achieved by dividing the total tuning range into 8 sections. As it is needed a digital unit is designed to choose the correct suband. To compensate the KVCO degradation over entire frequency range which cause instability, charge pump current is increased on the opposite direction. Total rms jitter is about 1.5ps. This PLL architecture has been simulated in standard of 0.18μm CMOS technology with 1.8V power supply.
{"title":"A widebound low phase noise LC-VCO based PLL with automatic amplitude control","authors":"A. Sohrabi, M. Ehsanian","doi":"10.1109/ICM.2014.7071802","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071802","url":null,"abstract":"This paper forcuese on a low phase noise LC-VCO based PLL using CP-AAC circuit for output amplitude control. A wide tuning range (2.796GHz-3.86GHz) is achieved by dividing the total tuning range into 8 sections. As it is needed a digital unit is designed to choose the correct suband. To compensate the KVCO degradation over entire frequency range which cause instability, charge pump current is increased on the opposite direction. Total rms jitter is about 1.5ps. This PLL architecture has been simulated in standard of 0.18μm CMOS technology with 1.8V power supply.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"40 4-5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120926079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071819
O. Kerdjidj, K. Ghanem, A. Amira, F. Harizi, F. Chouireb
Compressed Sensing (CS) is a promising method for signal recovery using fewer measurement samples than the ordinarily amount imposed by Shannon's sampling theorem. Many fields may need CS technique, but herein we are solely interested in applying it to the physiological signal acquisition systems, particularly the Electrocardiogram (ECG) biosignal. Since this signal is sparse, it is a perfect candidate for CS processing. This paper investigates the application of two greedy algorithms on ECG raw data, namely the matching pursuit (MP) and the orthogonal matching pursuit (OMP) algorithms. Several tests on various ECG data sets are carried out to make the best choice of the parameters (type of dictionary, maximum number of iterations,etc) that allow a good reconstruction of the original signal. Moreover, we propose to concatenate different dictionaries which is shown to enhance the accuracy by 14 dB. The novelty lies in the choice of the dictionaries and the application of the windowing on the original data that allows to significantly reduce the size of the dictionary.
{"title":"Concatenation of dictionaries for recovery of ECG signals using compressed sensing techniques","authors":"O. Kerdjidj, K. Ghanem, A. Amira, F. Harizi, F. Chouireb","doi":"10.1109/ICM.2014.7071819","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071819","url":null,"abstract":"Compressed Sensing (CS) is a promising method for signal recovery using fewer measurement samples than the ordinarily amount imposed by Shannon's sampling theorem. Many fields may need CS technique, but herein we are solely interested in applying it to the physiological signal acquisition systems, particularly the Electrocardiogram (ECG) biosignal. Since this signal is sparse, it is a perfect candidate for CS processing. This paper investigates the application of two greedy algorithms on ECG raw data, namely the matching pursuit (MP) and the orthogonal matching pursuit (OMP) algorithms. Several tests on various ECG data sets are carried out to make the best choice of the parameters (type of dictionary, maximum number of iterations,etc) that allow a good reconstruction of the original signal. Moreover, we propose to concatenate different dictionaries which is shown to enhance the accuracy by 14 dB. The novelty lies in the choice of the dictionaries and the application of the windowing on the original data that allows to significantly reduce the size of the dictionary.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"1116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116065810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071820
Mounir Bahtat, S. Belkouch, Philippe Elleaume, Phillipe Gall
Modulo scheduling is a software pipelining technique exploiting instruction-level parallelism (ILP) of VLIW architectures to efficiently implement loops. This paper presents a novel enumeration-based resource-constrained heuristic for modulo scheduling. It takes into consideration the criticality of the nodes, generating near optimal schedules in terms of initiation intervals and register requirements. The scheduling algorithm outperformed better-known heuristics in terms of the quality of schedules, while presenting small compilation time enabling it to be used in a production environment. Experimental results on the VLIW TMS320C6678 DSP processor, showed improved performance on a signal processing set of algorithms.
{"title":"Fast enumeration-based modulo scheduling heuristic for VLIW architectures","authors":"Mounir Bahtat, S. Belkouch, Philippe Elleaume, Phillipe Gall","doi":"10.1109/ICM.2014.7071820","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071820","url":null,"abstract":"Modulo scheduling is a software pipelining technique exploiting instruction-level parallelism (ILP) of VLIW architectures to efficiently implement loops. This paper presents a novel enumeration-based resource-constrained heuristic for modulo scheduling. It takes into consideration the criticality of the nodes, generating near optimal schedules in terms of initiation intervals and register requirements. The scheduling algorithm outperformed better-known heuristics in terms of the quality of schedules, while presenting small compilation time enabling it to be used in a production environment. Experimental results on the VLIW TMS320C6678 DSP processor, showed improved performance on a signal processing set of algorithms.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127541647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071824
R. Erfani, Fatemeh Marefat, M. Ehsanian
In this paper, a self-biased resistive-feedback current-reused CMOS low-noise amplifier (LNA) is presented for impulse-radio ultra-wideband (IR-UWB) applications. Wideband input, inter-stage, and output matching are achieved by using two stages of resistive-feedback amplifiers with inductive peaking. Consequently, high and flat power gain (S21), low and highly-flat noise figure (NF), and small group-delay variation are simultaneously achieved. By employing resistive-feedback, not only wideband matching is guaranteed, but also both stages adopt self-biasing technique (power and area saving) which totally removes noise contribution of bias circuitry at the input (better NF performance). As a result, state-of-the-art NF of 1.7dB (@7GHz) is achieved where across the whole frequency band of interest (i.e., 3-11GHz) NF remains below 2 dB. A flat S21 of 12.9±0.45dB and small group-delay variation of 68.5±17.5ps are also achieved. The proposed UWB LNA dissipates 10.35mW under supply of 1.5V in 0.18μm CMOS technology.
{"title":"Self-biased resistive-feedback current-reused CMOS UWB LNA with 1.7dB nf for IR-UWB applications","authors":"R. Erfani, Fatemeh Marefat, M. Ehsanian","doi":"10.1109/ICM.2014.7071824","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071824","url":null,"abstract":"In this paper, a self-biased resistive-feedback current-reused CMOS low-noise amplifier (LNA) is presented for impulse-radio ultra-wideband (IR-UWB) applications. Wideband input, inter-stage, and output matching are achieved by using two stages of resistive-feedback amplifiers with inductive peaking. Consequently, high and flat power gain (S21), low and highly-flat noise figure (NF), and small group-delay variation are simultaneously achieved. By employing resistive-feedback, not only wideband matching is guaranteed, but also both stages adopt self-biasing technique (power and area saving) which totally removes noise contribution of bias circuitry at the input (better NF performance). As a result, state-of-the-art NF of 1.7dB (@7GHz) is achieved where across the whole frequency band of interest (i.e., 3-11GHz) NF remains below 2 dB. A flat S21 of 12.9±0.45dB and small group-delay variation of 68.5±17.5ps are also achieved. The proposed UWB LNA dissipates 10.35mW under supply of 1.5V in 0.18μm CMOS technology.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126436029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/ICM.2014.7071817
Z. Zafar, M. A. Maktoomi, M. Hashmi
A study on two new circuits to generate square/triangular waveforms are presented. Circuit-I consists of a CCII, a capacitor, an OTA and a voltage divider network. The frequency can be changed by changing the voltage division ratio or the time-constant and amplitude by a combination thereof. As an extension of this concept, in the proposed circuit-II a CCCII is used in place of CCII to get electronic control through a bias current. Again, the frequency of the waveform can be adjusted by the bias current of the CCCII or the voltage division ratio and amplitude by a combination thereof. The circuits have been fully analyzed to deduce both ideal as well as non-ideal design equations. Proposed circuits have been extensively studied using the LTspice circuit simulator and one of them is experimentally verified with components available in our lab. The measured waveforms perfectly match with the theoretical/simulated waveforms. Finally, a comparison with the recently proposed works is also included.
{"title":"A new adjustable square/triangular-wave generator using CCII/CCCII and OTA","authors":"Z. Zafar, M. A. Maktoomi, M. Hashmi","doi":"10.1109/ICM.2014.7071817","DOIUrl":"https://doi.org/10.1109/ICM.2014.7071817","url":null,"abstract":"A study on two new circuits to generate square/triangular waveforms are presented. Circuit-I consists of a CCII, a capacitor, an OTA and a voltage divider network. The frequency can be changed by changing the voltage division ratio or the time-constant and amplitude by a combination thereof. As an extension of this concept, in the proposed circuit-II a CCCII is used in place of CCII to get electronic control through a bias current. Again, the frequency of the waveform can be adjusted by the bias current of the CCCII or the voltage division ratio and amplitude by a combination thereof. The circuits have been fully analyzed to deduce both ideal as well as non-ideal design equations. Proposed circuits have been extensively studied using the LTspice circuit simulator and one of them is experimentally verified with components available in our lab. The measured waveforms perfectly match with the theoretical/simulated waveforms. Finally, a comparison with the recently proposed works is also included.","PeriodicalId":107354,"journal":{"name":"2014 26th International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131084971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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